Cypress Semiconductor CY7C1024DV33 User manual

Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600
Document Number: 001-08353 Rev. *C Revised November 6, 2008
CY7C1024DV33
3-Mbit (128K X 24) Static RAM
Features
■ High speed
❐ t
AA
= 10 ns
■ Low active power
❐ I
CC
= 175 mA at 10 ns
■ Low CMOS standby power
❐ I
SB2
= 25 mA
■ Operating voltages of 3.3 ± 0.3V
■ 2.0V data retention
■ Automatic power down when deselected
■ TTL compatible inputs and outputs
■ Easy memory expansion with CE
1
, CE
2
, and CE
3
features
■ Available in Pb-free standard 119-ball PBGA
Functional Description
The CY7C1024DV33 is a high performance CMOS static RAM
organized as 128K words by 24 bits. This device has an
automatic power down feature that significantly reduces power
consumption when deselected.
To write to the device, enable the chip (CE
1
LOW, CE
2
HIGH,
and CE
3
LOW), while forcing the Write Enable (WE) input LOW.
Toreadfromthedevice,enablethechipbytakingCE
1
LOW,CE
2
HIGH, and CE
3
LOW while forcing the Output Enable (OE) LOW
and the Write Enable (WE) HIGH. See the Truth Table on page
7 for a complete description of Read and Write modes.
The 24 I/O pins (I/O
0
to I/O
23
) are placed in a high impedance
state when the device is deselected (CE
1
HIGH, CE
2
LOW, or
CE
3
HIGH) or when the output enable (OE) is HIGH during a
write operation. (CE
1
LOW, CE
2
HIGH, CE
3
LOW, and WE
LOW).
Logic Block Diagram
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
128K x 24
ARRAY
I/O
0
– I/O
23
OE
CE
1
, CE
2
, CE
3
WE
CONTROL LOGIC
A
(9:0)
A
(16:10)
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CY7C1024DV33
Document Number: 001-08353 Rev. *C Page 2 of 9
Selection Guide
Description –10 Unit
Maximum Access Time 10 ns
Maximum Operating Current 175 mA
Maximum CMOS Standby Current 25 mA
Pin Configuration
Figure 1. 119-Ball PBGA Top View
[1]
1234567
ANCAAAAANC
BNC A A CE
1
AANC
CI/O
12
NC CE
2
NC CE
3
NC I/O
0
DI/O
13
V
DD
V
SS
V
SS
V
SS
V
DD
I/O
1
EI/O
14
V
SS
V
DD
V
SS
V
DD
V
SS
I/O
2
FI/O
15
V
DD
V
SS
V
SS
V
SS
V
DD
I/O
3
GI/O
16
V
SS
V
DD
V
SS
V
DD
V
SS
I/O
4
HI/O
17
V
DD
V
SS
V
SS
V
SS
V
DD
I/O
5
JNC V
SS
V
DD
V
SS
V
DD
V
SS
NC
KI/O
18
V
DD
V
SS
V
SS
V
SS
V
DD
I/O
6
LI/O
19
V
SS
V
DD
V
SS
V
DD
V
SS
I/O
7
MI/O
20
V
DD
V
SS
V
SS
V
SS
V
DD
I/O
8
NI/O
21
V
SS
V
DD
V
SS
V
DD
V
SS
I/O
9
PI/O
22
V
DD
V
SS
V
SS
V
SS
V
DD
I/O
10
RI/O
23
NC NC NC NC NC I/O
11
TNC A A WE AANC
UNC A A OE AANC
Note
1. NC pins are not connected on the die.
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CY7C1024DV33
Document Number: 001-08353 Rev. *C Page 3 of 9
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Supply Voltage on V
CC
Relative to GND
[2]
....–0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State
[2]
...................................–0.5V to V
CC
+ 0.5V
DC Input Voltage
[2]
...............................–0.5V to V
CC
+ 0.5V
Current into Outputs (LOW) ........................................20 mA
Static Discharge Voltage............................................>2001V
(MIL-STD-883, Method 3015)
Latch Up Current.....................................................>200 mA
Operating Range
Range Ambient
Temperature V
CC
Industrial –40°C to +85°C3.3V±0.3V
DC Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions
[3]
–10 Unit
Min Max
V
OH
Output HIGH Voltage V
CC
= Min, I
OH
= –4.0 mA 2.4 V
V
OL
Output LOW Voltage V
CC
= Min, I
OL
= 8.0 mA 0.4 V
V
IH
Input HIGH Voltage 2.0 V
CC
+ 0.3 V
V
IL[2]
Input LOW Voltage –0.3 0.8 V
I
IX
Input Leakage Current GND < V
I
< V
CC
–1 +1 μA
I
OZ
Output Leakage Current GND < V
OUT
<V
CC
, output disabled –1 +1 μA
I
CC
V
CC
Operating Supply
Current V
CC
= Max, f = f
MAX
= 1/t
RC
I
OUT
= 0 mA CMOS levels 175 mA
I
SB1
Automatic CE Power Down
Current —TTL Inputs Max V
CC
, CE > V
IH
V
IN
> V
IH
or V
IN
< V
IL
, f = f
MAX
30 mA
I
SB2
Automatic CE Power Down
Current — CMOS Inputs Max V
CC
, CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V, or V
IN
< 0.3V, f = 0 25 mA
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions Max Unit
C
IN
Input Capacitance T
A
= 25°C, f = 1 MHz, V
CC
= 3.3V 8 pF
C
OUT
I/O Capacitance 10 pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions 119-Ball
PBGA Unit
Θ
JA
Thermal Resistance
(Junction to Ambient) Still air, soldered on a 3 × 4.5 inch, four layer printed circuit board 20.31 °C/W
Θ
JC
Thermal Resistance
(Junction to Case) 8.35 °C/W
Notes
2. V
IL
(min) = –2.0V andV
IH
(max) = V
CC
+ 2V for pulse durations of less than 20 ns.
3. CErefers toacombinationofCE
1
,CE
2
,and CE
3
.CEis LOWwhenCE
1
,CE
3
areLOWandCE
2
is HIGH. CE isHIGHwhen CE
1
isHIGH, or CE
2
is LOW, or CE
3
isHIGH.
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CY7C1024DV33
Document Number: 001-08353 Rev. *C Page 4 of 9
Figure 2. AC Test Loads and Waveform
[4]
AC Switching Characteristics
Over the Operating Range
[5]
Parameter Description –10 Unit
Min Max
Read Cycle
t
power[6]
V
CC
(Typical) to the First Access 100 μs
t
RC
Read Cycle Time 10 ns
t
AA
Address to Data Valid 10 ns
t
OHA
Data Hold from Address Change 3 ns
t
ACE
CE Active LOW to Data Valid
[3]
10 ns
t
DOE
OE LOW to Data Valid 5 ns
t
LZOE
OE LOW to Low Z
[7]
1ns
t
HZOE
OE HIGH to High Z
[7]
5ns
t
LZCE
CE Active LOW to Low Z
[3, 7]
3ns
t
HZCE
CE Deselect HIGH to High Z
[3, 7]
5ns
t
PU
CE Active LOW to Power Up
[3, 8]
0ns
t
PD
CE Deselect HIGH to Power Down
[3, 8]
10 ns
90%
10%
3.0V
GND
90%
10%
All input pulses
3.3V
OUTPUT 5 pF*
(a) (b)
R1 317 Ω
R2
351Ω
Fall Time:> 1V/ns
(c)
OUTPUT 50Ω
Z0= 50Ω
V
TH
= 1.5V
30 pF*
*Capacitive Load consists of all
components of the test environment
Rise Time > 1V/ns
*
Including jig
and scope
Notes
4. Valid SRAM operation does not occur until the power supplies have reached the minimum operating V
DD
(3.0V). 100 μs (t
power
) after reaching the minimum operating
V
DD
, normal SRAM operation can begin including reduction in V
DD
to the data retention (V
CCDR
, 2.0V) voltage.
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V. Test conditions for the read cycle use
output loading as shown in part a) of Figure 2, unless specified otherwise.
6. t
POWER
gives the minimum amount of time that the power supply is at typical V
CC
values until the first memory access is performed.
7. t
HZOE
, t
HZCE
, t
HZWE
, t
LZOE
, t
LZCE
, and t
LZWE
are specified with a load capacitance of 5 pF as in part (b) of Figure 2. Transition is measured ±200 mV from steady state
voltage.
8. These parameters are guaranteed by design and are not tested.
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CY7C1024DV33
Document Number: 001-08353 Rev. *C Page 5 of 9
Write Cycle
[9, 10]
t
WC
Write Cycle Time 10 ns
t
SCE
CE active LOW to Write End
[3]
7ns
t
AW
Address Setup to Write End 7 ns
t
HA
Address Hold from Write End 0 ns
t
SA
Address Setup to Write Start 0 ns
t
PWE
WE Pulse Width 7 ns
t
SD
Data Setup to Write End 5.5 ns
t
HD
Data Hold from Write End 0 ns
t
LZWE
WE HIGH to Low Z
[7]
3ns
t
HZWE
WE LOW to High Z
[7]
5ns
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions
[3]
Min Typ Max Unit
V
DR
V
CC
for Data Retention 2 V
I
CCDR
Data Retention Current V
CC
= 2V, CE > V
CC
– 0.2V,
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V 25 mA
t
CDR [11]
Chip Deselect to Data Retention Time 0 ns
t
R [12]
Operation Recovery Time t
RC
ns
Data Retention Waveform
AC Switching Characteristics (continued)
Over the Operating Range
[5]
Parameter Description –10 Unit
Min Max
3.0V3.0V
t
CDR
V
DR
> 2V
DATA RETENTION MODE
t
R
CE
V
CC
Notes
9. The internal write time of the memory is defined by the overlap of CE
1
and CE
2
and CE
3
LOW and WE LOW. Chip enables must be active and WE must be LOW to
initiate a write. The transition of any of these signals terminate the write. The input data setup and hold timing is referenced to the leading edge of the signal that
terminates the write.
10.The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
11. Tested initially and after any design or process changes that may affect these parameters.
12.Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min)
> 50 μs or stable at V
CC(min)
> 50 μs.
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CY7C1024DV33
Document Number: 001-08353 Rev. *C Page 6 of 9
Switching Waveforms
Figure 3. Read Cycle No. 1 (Address Transition Controlled)
[13, 14]
Figure 4. Read Cycle No. 2 (OE Controlled)
[3, 14, 15]
Figure 5. Write Cycle No. 1 (CE Controlled)
[3, 16, 17]
PREVIOUS DATA VALID DATA VALID
RC
t
AA
t
OHA
t RC
ADDRESS
DATA OUT
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
t
HZOE
t
HZCE
t
PD
HIGH
ICC
ISB
IMPEDANCE
OE
CE
ADDRESS
DATA OUT
V
CC
SUPPLY
CURRENT
t
WC
DATA VALID
t
AW
t
SA
t
PWE
t
HA
t
HD
t
SD
t
SCE
t
SCE
CE
WE
DATA I/O
ADDRESS
Notes
13.Device is continuously selected. OE, CE = V
IL
.
14.WE is HIGH for read cycle.
15.Address valid before or similar to CE transition LOW.
16.Data I/O is high impedance if OE = V
IH
.
17.If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
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CY7C1024DV33
Document Number: 001-08353 Rev. *C Page 7 of 9
Figure 6. Write Cycle No. 2 (WE Controlled, OE HIGH During Write)
[3, 16, 17]
Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW)
[3, 17]
Truth Table
CE
1
CE
2
CE
3
OE WE I/O
0
– I/O
23
Mode Power
HXXXXHighZ PowerDown Standby(I
SB
)
X L X X X High Z Power Down Standby (I
SB
)
X X H X X High Z Power Down Standby (I
SB
)
L H L L H Full Data Out Read Active (I
CC
)
L H L X L Full Data In Write Active (I
CC
)
L H L H H High Z Selected, Outputs Disabled Active (I
CC
)
Switching Waveforms (continued)
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZOE
DATA
IN
VALID
NOTE 18
CE
ADDRESS
WE
DATA I/O
OE
DATA VALID
t
HD
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZWE
NOTE 18
CE
ADDRESS
WE
DATA I/O
Note
18.During this period, the I/Os are in the output state and input signals are not applied.
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CY7C1024DV33
Document Number: 001-08353 Rev. *C Page 8 of 9
Ordering Information
Speed
(ns) Ordering Code Package Name Package Type Operating Range
10 CY7C1024DV33-10BGXI 51-85115 119-Ball Plastic Ball Grid Array (14 x 22 x 2.4 mm) (Pb-Free) Industrial
Package Diagram
Figure 8. 119-Ball PBGA (14 x 22 x 2.4 mm)
51-85115-*B
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CY7C1024DV33
© Cypress Semiconductor Corporation, 2006-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction witha Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-08353 Rev. *C Revised November 6, 2008 Page 9 of 9
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Document Title: CY7C1024DV33, 3-Mbit (128K X 24) Static RAM
Document Number: 001-08353
Rev. ECN No. Orig. of
Change Submission Date Description of Change
** 469517 NXR See ECN New data sheet
*A 499604 NXR See ECN Added note 1 for NC pins
Changed I
CC
specification from 150 mA to 185 mA
Updated Test Condition for I
CC
in DC Electrical Characteristics table
Added note for t
ACE
, t
LZCE
, t
HZCE
, t
PU
, t
PD
, t
SCE
in AC Switching Characteristics Table
on page 4
*B 1462586 VKN/SFV See ECN Converted from preliminary to final
Updated block diagram
Changed I
CC
specification from 185 mA to 225 mA
Updated thermal specs
*C 2604677 VKN/PYRS 11/12/08 Removed Commercial operating range, Added Industrial operating range
Removed 8 ns speed bin, Added 10 ns speed bin
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