Cypress Semiconductor CY7C150 User manual

1Kx4 Static RAM
CY7C150
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05024 Rev. ** Revised August 24, 2001
50
Features
• Memory reset function
• 1024x4staticRAMforcontrolstoreinhigh-speedcom-
puters
• CMOS for optimum speed/power
• High speed
—10 ns (commercial)
—12 ns (military)
• Low power
—495 mW (commercial)
—550 mW (military)
• Separate inputs and outputs
•5-voltpowersupply±10%toleranceinbothcommercial
and military
•Capable of withstanding greater than 2001V static dis-
charge
•TTL-compatible inputs and outputs
Functional Description
The CY7C150 is a high-performance CMOS static RAM de-
signed for use in cache memory, high-speed graphics, and
data-acquisitionapplications.TheCY7C150hasamemoryre-
set feature that allows the entire memory to be reset in two
memory cycles.
Separate I/O paths eliminates the need to multiplex data in
and data out, providing for simpler board layout and faster sys-
tem performance. Outputs are three-stated during write, reset,
deselect, or when output enable (OE) is held HIGH, allowing
for easy memory expansion.
Reset is initiated by selecting the device (CS = LOW) and tak-
ing the reset (RS) input LOW. Within two memory cycles all
bits are internally cleared to zero. Since chip select must be
LOW for the device to be reset, a global reset signal can be
employed, withonly selected devices being clearedat any giv-
en time.
Writing to the device is accomplished when the chip select
(CS) and write enable (WE) inputs are both LOW. Data on the
four data inputs (D0−D3) is written into the memory location
specified on the address pins (A0through A9).
Reading the device is accomplished by taking chip select (CS)
and output enable (OE) LOW while write enable (WE) remains
HIGH. Under these conditions, the contents of the memory
location specified on the address pins will appear on the four
output pins (O0through O3).
The output pins remain in high-impedance state when chip
enable (CE) or output enable (OE) is HIGH, or write enable
(WE) or reset (RS) is LOW.
A die coat is used to insure alpha immunity.
Logic Block Diagram PinConfiguration
C150–1
64x64
ARRA
Y
A0
A1
A2
A3
A4
COLUMNDECODER
ROW DECODER
SENSE AMPS
DATAINPUT
CONTROL
O0
O1
O2
O3
A6A7A8
D0D1D2D3
COLUMN
DECODER
OE
WE
CS
RS
1
2
3
4
5
6
7
8
9
10
11
12 13
14
18
17
16
15
19
22
21
20
Top View
DIP/SOIC
7C150
A3
A4
A5
A6
A7
O2
VCC
A2
WE
CS
OE
O3
D2
D3
C150-2
A8
A9
D0
O0
D1
23
24
A1
A0
RS
O1
GND
A5
A9
Selection Guide
7C150−10 7C150−12 7C150−15 7C150−25 7C150−35
Maximum Access Time (ns) Commercial 10 12 15 25
Military 12 15 25 35
Maximum Operating Current (mA) Commercial 90 90 90 90 90
Military 100 100 100 100
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CY7C150
Document #: 38-05024 Rev. ** Page 2 of 11
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ......................................−65°C to+150°C
Ambient Temperature with
Power Applied...................................................−55°C to+125°C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12)..................................................−0.5V to+7.0V
DC Voltage Applied to Outputs
in High Z State......................................................−0.5V to+7.0V
DC Input Voltage.................................................−3.0V to +7.0V
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage.......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Operating Range
Range Ambient Temperature VCC
Commercial 0°C to +70°C 5V ±10%
Military[1] −55°C to +125°C 5V ±10%
Note:
1. TAis the “instant on”case temperature.
Electrical Characteristics Over the Operating Range[2]
Parameter Description Test Conditions 7C150 UnitMin. Max.
VOH Output HIGH Voltage VCC = Min., IOH = −0.4 mA 2.4 V
VOL Output LOW Current VCC = Min., IOL = 12 mA 0.4 V
VIH Input HIGH Level 2.0 VCC V
VIL Input LOW Level −3.0 0.8 V
IIX Input Load Current GND < VI< VCC −10 +10 µA
IOZ Output Current (High Z) VOL < VOUT <VOH,
Output Disabled −50 +50 µA
IOS Output Short Circuit Current[3] VCC = Max., VOUT = GND −300 mA
ICC VCC Operating Supply Current VCC = Max.,
IOUT = 0 mA Commercial 90 mA
Military 100 mA
Notes:
2. See the last page of this specification for Group A subgroup testing information.
3. Not more than 1 output should be shorted at a time. Duration of the short circuit should not exceed 30 seconds.
Capacitance[4]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA= 25°C, f = 1 MHz,
VCC = 5.0V 10 pF
COUT Output Capacitance 10 pF
Note:
4. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
3.0V
5V
OUTPUT
R1329Ω
R2
202Ω
30 pF GND 90% 90%
10%
<3ns <3ns
5V
OUTPUT
C150–3
R2
202Ω
5pF
C150–4
OUTPUT 1.9V
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
R1329Ω
Equivalent to: THÉVENIN EQUIVALENT
10%
ALL INPUT PULSES
(a) (b)
125Ω
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CY7C150
Document #: 38-05024 Rev. ** Page 3 of 11
Switching Characteristics Over the Operating Range[2,5]
Parameter Description
7C150−10 7C150−12 7C150−15 7C150−25 7C150−35
UnitMin. Max. Min. Max. Min. Max. Min. Max. Min. Max.
READ CYCLE
tRC Read Cycle Time 10 12 15 25 35 ns
tAA Address to Data Valid 10 12 15 25 35 ns
tOHA Output Hold from Address
Change 2 2 2 2 2 ns
tACS CS LOW to Data Valid 810 12 15 20 ns
tLZCS CS LOW to Low Z[6] 0 0 0 0 0 ns
tHZCS CS HIGH to High Z[6,7] 6 8 11 20 25 ns
tDOE OE LOW to Data Valid 6 8 10 15 20 ns
tLZOE OE LOW to Low Z[6] 0 0 0 0 0 ns
tHZOE OE HIGH to High Z[6,7] 6 8 9 20 25 ns
WRITE CYCLE[8]
tWC Write Cycle Time 10 12 15 25 35 ns
tSCS CS LOW to Write End 6 8 11 15 20 ns
tAW Address Set-Up to Write End 810 13 20 30 ns
tHA Address Hold from Write End 2 2 2 5 5 ns
tSA Address Set-Up to Write Start 2 2 2 5 5 ns
tPWE WE Pulse Width 6 8 11 15 20 ns
tSD Data Set-Up to Write End 6 8 11 15 20 ns
tHD Data Hold from Write End 2 2 2 5 5 ns
tLZWE WE HIGH to Low Z[6] 0 0 0 0 0 ns
tHZWE WE LOW to High Z[6,7] 6 8 12 20 25 ns
RESET CYCLE
tRRC Reset Cycle Time 20 24 30 50 70 ns
tSAR Address Valid to Beginning of
Reset 0 0 0 0 0 ns
tSWER Write Enable HIGH to Beginning
of Reset 0 0 0 0 0 ns
tSCSR Chip Select LOW to Beginning of
Reset 0 0 0 0 0 ns
tPRS Reset Pulse Width 10 12 15 20 30 ns
tHCSR Chip Select Hold After End of
Reset 0 0 0 0 0 ns
tHWER Write Enable Hold After End of
Reset 812 15 30 40 ns
tHAR Address Hold After End of Reset 10 12 15 30 40 ns
tLZRS Reset HIGH to Output in Low Z[6] 0 0 0 0 0 ns
tHZRS Reset LOW to Output in
High Z[6,7] 6 8 12 20 25 ns
Notes:
5. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, andoutputloading of the specified
IOL/IOH and 30-pF load capacitance.
6. At any given temperature and voltage condition, tHZ is less than tLZ for any given device.
7. tHZCS, tHZOE, tHZR, and tHZWE are tested with CL= 5 pF as in part (b) of AC Test Loads. Transition is measured±500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CSLOW and WE LOW. Both signals must be LOW toinitiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be reference to the rising edge of the signal that terminates the write.
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CY7C150
Document #: 38-05024 Rev. ** Page 4 of 11
Switching Waveforms
Notes:
9. WEis HIGH for read cycle.
10. Device is continuously selected, CSand OE = VIL.
11. Address prior to or coincident with CStransition LOW.
ReadCycleNo.1
ADDRESS
C150-5
DATA OUT PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
[9,10]
Read CycleNo. 2
Write CycleNo.1(WEControlled)
DATA VALID
tRC
tACS
tDOE
tLZOE
tLZCS
DATA OUT HIGH IMPEDANCE IMPEDANCE
tHZOE
tHZCS
OE
CE
HIGH
C150-6
tWC
DATA UNDEFINED HIGH IMPEDANCE
tSCS
tAW
tSA tPWE tHA
tHD
tHZWE tLZWE
tSD
C150-7
CE
WE
DATA IN
DATA I/O
ADDRESS
DATAIN VALID
[9,11]
[8]
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CY7C150
Document #: 38-05024 Rev. ** Page 5 of 11
Notes:
12. If CS goes HIGH with WE HIGH, the output remains in a high-impedance state.
13. Reset cycle is defined by the overlap of RS and CS for the minimum reset pulse width.
Switching Waveforms (continued)
Write CycleNo.2(CSControlled) tWC
DATA UNDEFINED HIGH IMPEDANCE
tSCS
tAW
tSA
tPWE
tHA
tHD
tHZWE
tSD
ADDRESS
CE
WE
DATA IN
DATA I/O
C150-8
DATAIN VALID
[8,12]
Reset Cycle
tRRC
OUTPUT VALID ZERO
tSAR
tHCSR
tHAR
tLZRS
ADDRESS
WE
CS
DATA I/O
C150-9
tPRS
HIGH
IMPEDANCE
tHZRS
tSWER
tSCSR
RESET
tHWER
[13]
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Document #: 38-05024 Rev. ** Page 6 of 11
Typical DC and AC Characteristics
1.2
1.4
1.0
0.6
0.4
0.2
4.0 4.5 5.0 5.5 6.0
1.6
1.4
1.2
1.0
0.8
−55 25 125
−55 25 125
1.2
1.0
0.8
NORMALIZED t
AA
60
50
40
30
20
10
0.0 1.0 2.0 3.0 4.0
OUTPUT SOURCE CURRENT (mA)
SUPPLYVOLTAGE(V)
NORMALIZED SUPPLY CURRENT
vs.SUPPLY VOLTAGE
NORMALIZED ACCESS TIME
vs.AMBIENT TEMPERATURE
AMBIENT TEMPERATURE(°C)
NORMALIZED SUPPLY CURRENT
vs.AMBIENT TEMPERATURE
AMBIENT TEMPERATURE(°C) OUTPUT VOLTAGE(V)
OUTPUT SOURCE CURRENT
vs.OUTPUT VOLTAGE
0.0
0.8
1.4
1.3
1.2
1.1
1.0
0.9
4.0 4.5 5.0 5.5 6.0
NORMALIZED t
AA
SUPPLY VOLTAGE(V)
NORMALIZED ACCESS TIME
vs.SUPPLY VOLTAGE 150
125
75
50
25
0.0 1.0 2.0 3.0 4.0
OUTPUT SINK CURRENT (mA)
0
100
OUTPUT VOLTAGE(V)
OUTPUT SINK CURRENT
vs.OUTPUT VOLTAGE
0.6
0.4
0.2
0.0
NORMALIZED I, I
CC SB
NORMALIZED I, I
CC SB
ISB
VCC =5.0V
VIN =5.0V
ICC
ICC
VCC =5.0V
VCC =5.0V
TA=25°C
ISB
TA=25°C
0.6
0.8
0
VCC =5.0V
TA=25°C
5.0
3.0
2.5
2.0
1.5
1.0
0.5
0.0 1.0 2.0 3.0 4.0
NORMALIZED I
PO
SUPPLY VOLTAGE(V)
TYPICALPOWER–ONCURRENT
vs.SUPPLYVOLTAGE 30
20
10
0 200 400 600 800
DELTA t (ns)
AA
CAPACITANCE (pF)
TYPICAL ACCESS TIME CHANGE
vs.OUTPUT LOADING 1.1
1.0
0.9
10 20 30 40
NORMALIZED I
CC
CYCLE FREQUENCY (MHz)
NORMALIZED ICC vs.CYCLETIME
0.0 5.0 01000 0.8
VCC =4.5V
TA=25°C
VCC =5.0V
TA=25°C
VCC =0.5V
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CY7C150
Document #: 38-05024 Rev. ** Page 7 of 11
Truth Table
Inputs Outputs ModeCS WE OE RS
H X X X High Z Not Selected
L H X L High Z Reset
L L X H High Z Write
L H L H O0−O3Read
L X H H High Z Output Disable
Ordering Information
Speed
(ns) Ordering Code Package Name Package Type Operating Range
10 CY7C150−10PC P13A 24-Lead (300-Mil) Molded DIP Commercial
CY7C150−10SC S13 24-Lead Molded SOIC
12 CY7C150−12PC P13A 24-Lead (300-Mil) Molded DIP Commercial
CY7C150−12SC S13 24-Lead Molded SOIC
CY7C150−12DMB D14 24-Lead (300-Mil) CerDIP Military
15 CY7C150−15PC P13A 24-Lead (300-Mil) Molded DIP Commercial
CY7C150−15SC S13 24-Lead Molded SOIC
CY7C150−15DMB D14 24-Lead (300-Mil) CerDIP Military
25 CY7C150−25PC P13A 24-Lead (300-Mil) Molded DIP Commercial
CY7C150−25SC S13 24-Lead Molded SOIC
CY7C150−25DMB D14 24-Lead (300-Mil) CerDIP Military
35 CY7C150−35DMB D14 24-Lead (300-Mil) CerDIP Military
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CY7C150
Document #: 38-05024 Rev. ** Page 8 of 11
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameter Subgroups
VOH 1, 2, 3
VOL 1, 2, 3
VIH 1, 2, 3
VIL Max. 1, 2, 3
IIX 1, 2, 3
IOZ 1, 2, 3
ICC 1, 2, 3
Switching Characteristics
Parameter Subgroups
READ CYCLE
tRC 7, 8, 9, 10, 11
tAA 7, 8, 9, 10, 11
tOHA 7, 8, 9, 10, 11
tACS 7, 8, 9, 10, 11
WRITE CYCLE
tWC 7, 8, 9, 10, 11
tSCS 7, 8, 9, 10, 11
tAW 7, 8, 9, 10, 11
tHA 7, 8, 9, 10, 11
tSA 7, 8, 9, 10, 11
tPWE 7, 8, 9, 10, 11
tSD 7, 8, 9, 10, 11
tHD 7, 8, 9, 10, 11
RESET CYCLE
tRRC 7, 8, 9, 10, 11
tSAR 7, 8, 9, 10, 11
tSWER 7, 8, 9, 10, 11
tSCSR 7, 8, 9, 10, 11
tPRS 7, 8, 9, 10, 11
tHCSR 7, 8, 9, 10, 11
tHWER 7, 8, 9, 10, 11
tHAR 7, 8, 9, 10, 11
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CY7C150
Document #: 38-05024 Rev. ** Page 9 of 11
Package Diagrams
24-Lead (300-Mil) CerDIP D14
MIL-STD-1835 D- 9Config.A
24-Lead (300-Mil) Molded DIP P13/P13A
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CY7C150
Document #: 38-05024 Rev. ** Page 10 of 11
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in aCypress Semiconductorproduct. Nor does itconvey or imply any license underpatent or other rights. CypressSemiconductor doesnot authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
Package Diagrams (continued)
24-Lead Molded SOIC S13
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