Cypress Semiconductor STK11C88 User manual

STK11C88
256 Kbit (32K x 8) SoftStore nvSRAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600
Document Number: 001-50591 Rev. ** Revised January 29, 2009
Features
■ 25 ns and 45 ns access times
■ Pin compatible with industry standard SRAMs
■ Software initiated STORE and RECALL
■ Automatic RECALL to SRAM on power up
■ Unlimited Read and Write endurance
■ Unlimited RECALL cycles
■ 1,000,000 STORE cycles
■ 100 year data retention
■ Single 5V+10% power supply
■ Commercial and Industrial Temperatures
■ 28-pin (300 mil and 330 mil) SOIC packages
■ RoHS compliance
Functional Description
The Cypress STK11C88 is a 256 Kb fast static RAM with a
nonvolatile element in each memory cell. The embedded
nonvolatile elements incorporate QuantumTrap
™
technology
producing the world’s most reliable nonvolatile memory. The
SRAM provides unlimited read and write cycles, while
independent, nonvolatile data resides in the highly reliable
QuantumTrap cell. Data transfers under Software control from
SRAM to the nonvolatile elements (the STORE operation). On
power up, data is automatically restored to the SRAM (the
RECALL operation) from the nonvolatile memory. RECALL
operations are also available under software control.
Logic Block Diagram
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STK11C88
Document Number: 001-50591 Rev. ** Page 2 of 15
Pin Configurations
Figure 1. Pin Diagram - 28-Pin SOIC
Table 1. Pin Definitions - 28-Pin SOIC
Pin Name Alt IO Type Description
A
0
–A
14
Input Address Inputs. Used to select one of the 32,768 bytes of the nvSRAM.
DQ
0
-DQ
7
Input or
Output Bidirectional Data IO lines. Used as input or output lines depending on operation.
WE WInput Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the
IO pins is written to the specific address location.
CE EInput Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the
chip.
OE GInput Output Enable, Active LOW. The active LOW OE input enables the data output buffers
during read cycles. Deasserting OE HIGH causes the IO pins to tri-state.
V
SS
Ground Ground for the Device.The device is connected to the ground of the system.
V
CC
Power Supply Power Supply Inputs to the Device.
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STK11C88
Document Number: 001-50591 Rev. ** Page 3 of 15
Device Operation
The STK11C88 is a versatile memory chip that provides several
modes of operation. The STK11C88 can operate as a standard
32K x 8 SRAM. A 32K x 8 array of nonvolatile storage elements
shadow the SRAM. SRAM data can be copied from nonvolatile
memory or nonvolatile data can be recalled to the SRAM.
SRAM Read
The STK11C88 performs a READ cycle whenever CE and OE
are LOW, while WE is HIGH. The address specified on pins
A
0–14
determines the 32,768 data bytes accessed. When the
READ is initiated by an address transition, the outputs are valid
after a delay of t
AA
(READ cycle 1). If the READ is initiated by
CE or OE, the outputs are valid at t
ACE
or at t
DOE
, whichever is
later (READ cycle 2). The data outputs repeatedly respond to
address changes within the t
AA
access time without the need for
transitions on any control input pins, and remain valid until
another address change or until CE or OE is brought HIGH.
SRAM Write
A WRITE cycle is performed whenever CE and WE are LOW.
The address inputs must be stable prior to entering the WRITE
cycle and must remain stable until either CE or WE goes HIGH
at the end of the cycle. The data on the common IO pins DQ
0–7
are written into the memory if it has valid t
SD
, before the end of
a WE controlled WRITE or before the end of an CE controlled
WRITE. Keep OE HIGH during the entire WRITE cycle to avoid
data bus contention on common IO lines. If OE is left LOW,
internal circuitry turns off the output buffers t
HZWE
after WE goes
LOW.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The STK11C88 software STORE
cycle is initiated by executing sequential CE controlled READ
cycles from six specific address locations in exact order. During
the STORE cycle, an erase of the previous nonvolatile data is
first performed, followed by a program of the nonvolatile
elements. When a STORE cycle is initiated, input and output are
disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used
forSTOREinitiation,it is importantthatno otherREADor WRITE
accesses intervene in the sequence. If they intervene, the
sequence is aborted and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following READ
sequence is performed:
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0FC0, Initiate STORE cycle
The software sequence is clocked with CE controlled READs.
When the sixth address in the sequence is entered, the STORE
cycle commences and the chip is disabled. It is important that
READ cycles and not WRITE cycles are used in the sequence.
It is not necessary that OE is LOW for a valid sequence. Afterthe
t
STORE
cycle time is fulfilled, the SRAM is again activated for
READ and WRITE operation.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiatedwith a sequenceof READoperations ina mannersimilar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled READ operations is
performed:
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0C63, Initiate RECALL cycle
Internally, RECALL isatwo step procedure.First, theSRAMdata
is cleared, and then the nonvolatile information is transferredinto
the SRAM cells. After the t
RECALL
cycle time, the SRAM is once
again ready for READ and WRITE operations. The RECALL
operation does not alter the data in the nonvolatile elements. The
nonvolatile data can be recalled an unlimited number of times.
Hardware RECALL (Power Up)
During power up or after any low power condition (V
CC
<V
RESET
),
an internal RECALL request is latched. When V
CC
once again
exceeds the sense voltage of V
SWITCH
, a RECALL cycle is
automatically initiated and takes t
HRECALL
to complete.
If the STK11C88 is in a WRITE
state at the end of power up
RECALL, the SRAM
data is corrupted. To help avoid this
situation, a 10 Kohm resistor is connected either between WE
and system V
CC
or between CE and system V
CC
.
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STK11C88
Document Number: 001-50591 Rev. ** Page 4 of 15
Hardware Protect
The STK11C88 offers hardware protection against inadvertent
STORE operation and SRAM WRITEs during low voltage
conditions. When V
CC
<V
SWITCH
, all externally initiated
STORE operations and SRAM WRITEs are inhibited.
Noise Considerations
The STK11C88 is a high speed memory. It must have a high
frequency bypass capacitor of approximately 0.1 µF
connected between V
CC
and V
SS,
using leads and traces that
are as short as possible. As with all high speed CMOS ICs,
careful routing of power, ground, and signals help prevent
noise problems.
Low Average Active Power
CMOS technology provides the STK11C88 the benefit of
drawing significantly less current when it is cycled at times
longer than 50 ns. Figure 2 and Figure 3 show the relationship
between I
CC
and READ or WRITE cycle time. Worst case
current consumption is shown for both CMOS and TTL input
levels (commercial temperature range, VCC = 5.5V, 100
percent duty cycle on chip enable). Only standby current is
drawn when the chip is disabled. The overall average current
drawn by the STK11C88 depends on the following items:
1. The duty cycle of chip enable
2. The overall cycle rate for accesses
3. The ratio of READs to WRITEs
4. CMOS versus TTL input levels
5. The operating temperature
6. The V
CC
level
7. IO loading
Best Practices
nvSRAM products have been used effectively for over 15
years. While ease-of-use is one of the product’s main system
values, the experience gained working with hundreds of appli-
cations has resulted in the following suggestions as best
practices:
■ The nonvolatile cells in a nvSRAM are programmed on the
test floor during final test and quality assurance. Incoming
inspection routines at customer or contract manufacturer’s
sites,sometimes,reprogramthesevalues.Final NV patterns
are typically repeating patterns of AA, 55, 00, FF, A5, or 5A.
The end product’s firmware should not assume that a NV
array is in a set programmed state. Routines that check
memorycontentvaluestodeterminefirsttimesystemconfig-
urationandcoldorwarmbootstatus,shouldalwaysprogram
a unique NV pattern (for example, a complex 4-byte pattern
of 46 E6 49 53 hex or more random bytes) as part of the final
system manufacturing test to ensure these system routines
work consistently.
■ PowerupbootfirmwareroutinesshouldrewritethenvSRAM
into the desired state. While the nvSRAM is shipped in a
preset state, best practice is to again rewrite the nvSRAM
into the desired state as a safeguard against events that
might flip the bit inadvertently (program bugs or incoming
inspection routines).
Figure 2. Icc (max) Reads
Figure 3. Icc (max) Writes
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STK11C88
Document Number: 001-50591 Rev. ** Page 5 of 15
Table 2. Software STORE/RECALL Mode Selection
CE WE A
13
– A
0
Mode IO Notes
L H 0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile STORE
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
[1, 2]
L H 0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
[1, 2]
Notes
1. The six consecutive addresses must be in the order listed. WE must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle.
2. While there are 15 addresses on the STK11C88, only the lower 14 are used to control software modes.
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STK11C88
Document Number: 001-50591 Rev. ** Page 6 of 15
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage Temperature .................................–65°C to +150°C
Temperature under bias..............................–55°C to +125°C
Supply Voltage on V
CC
Relative to GND..........–0.5V to 7.0V
Voltage on Input Relative to Vss............–0.6V to V
CC
+ 0.5V
Voltage on DQ
0-7
...................................–0.5V to Vcc + 0.5V
Power Dissipation .........................................................1.0W
DC Output Current (1 output at a time, 1s duration)....15 mA
Operating Range
Range Ambient Temperature V
CC
Commercial 0°C to +70°C 4.5V to 5.5V
Industrial -40°C to +85°C 4.5V to 5.5V
DC Electrical Characteristics
Over the operating range (V
CC
= 4.5V to 5.5V)
Parameter Description Test Conditions Min Max Unit
I
CC1
Average V
CC
Current t
RC
= 25 ns
t
RC
= 45 ns
Dependent on output loading and cycle rate.
Values obtained without output loads.
I
OUT
= 0 mA.
Commercial 97
70 mA mA
Industrial 100
70 mA mA
I
CC2
Average V
CC
Current
during STORE All Inputs Do Not Care, V
CC
= Max
Average current for duration t
STORE
3mA
I
CC3
Average V
CC
Current
at t
RC
= 200 ns, 5V,
25°C Typical
WE > (V
CC
– 0.2V). All other inputs cycling.
Dependent on output loading and cycle rate. Values obtained
without output loads.
10 mA
I
SB1[3]
Average V
CC
Current
(Standby, Cycling
TTL Input Levels)
t
RC
=25ns, CE > V
IH
t
RC
=45ns, CE > V
IH
Commercial 30
22 mA
Industrial 31
23 mA
I
SB2[3]
V
CC
Standby Current
(Standby, Stable
CMOS Input Levels)
CE > (V
CC
– 0.2V). All others V
IN
<0.2V or > (V
CC
– 0.2V). 750 μA
I
IX
Input Leakage
Current V
CC
= Max, V
SS
< V
IN
<V
CC
-1 +1 μA
I
OZ
Off State Output
Leakage Current V
CC
= Max, V
SS
< V
IN
<V
CC
, CE or OE > V
IH
or WE < V
IL
-5 +5 μA
V
IH
Input HIGH Voltage 2.2 V
CC
+
0.5 V
V
IL
Input LOW Voltage V
SS
–
0.5 0.8 V
V
OH
Output HIGH Voltage I
OUT
= –4 mA 2.4 V
V
OL
Output LOW Voltage I
OUT
= 8 mA 0.4 V
Data Retention and Endurance
Parameter Description Min Unit
DATA
R
Data Retention 100 Years
NV
C
Nonvolatile STORE Operations 1,000 K
Note
3. CE > V
IH
will not produce standby current levels until any nonvolatile cycle in progress has timed out.
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STK11C88
Document Number: 001-50591 Rev. ** Page 7 of 15
Capacitance
In the following table, the capacitance parameters are listed.
[4]
Parameter Description Test Conditions Max Unit
C
IN
Input Capacitance T
A
= 25°C, f = 1 MHz,
V
CC
= 0 to 3.0 V 5pF
C
OUT
Output Capacitance 7 pF
Thermal Resistance
In the following table, the thermal resistance parameters are listed.
[4]
Parameter Description Test Conditions 28-SOIC
(300 mil) 28-SOIC (330 mil) Unit
Θ
JA
Thermal Resistance
(Junction to Ambient) Test conditions follow standard test methods and procedures for measuring thermal impedance,
per EIA / JESD51.
TBD TBD °C/W
Θ
JC
Thermal Resistance
(Junction to Case) TBD TBD °C/W
Figure 4. AC Test Loads
AC Test Conditions
5.0V
Output
30 pF
R1 480Ω
R2
255Ω
Input Pulse Levels..................................................0 V to 3 V
Input Rise and Fall Times (10% - 90%)........................ <5 ns
Input and Output Timing Reference Levels................... 1.5 V
Note
4. These parameters are guaranteed by design and are not tested.
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STK11C88
Document Number: 001-50591 Rev. ** Page 8 of 15
AC Switching Characteristics
SRAM Read Cycle
Parameter Description 25 ns 45 ns Unit
Min Max Min Max
Cypress
Parameter Alt
t
ACE
t
ELQV
Chip Enable Access Time 25 45 ns
t
RC [5]
t
AVAV,
t
ELEH
Read Cycle Time 25 45 ns
t
AA [6]
t
AVQV
Address Access Time 25 45 ns
t
DOE
t
GLQV
Output Enable to Data Valid 10 20 ns
t
OHA [6]
t
AXQX
Output Hold After Address Change 5 5 ns
t
LZCE [7]
t
ELQX
Chip Enable to Output Active 5 5 ns
t
HZCE [7]
t
EHQZ
Chip Disable to Output Inactive 10 15 ns
t
LZOE [7]
t
GLQX
Output Enable to Output Active 0 0 ns
t
HZOE [7]
t
GHQZ
Output Disable to Output Inactive 10 15 ns
t
PU [4]
t
ELICCH
Chip Enable to Power Active 0 0 ns
t
PD [4]
t
EHICCL
Chip Disable to Power Standby 25 45 ns
Switching Waveforms
Figure 5. SRAM Read Cycle 1: Address Controlled
[5, 6]
Figure 6. SRAM Read Cycle 2: CE and OE Controlled
[5]
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Notes
5. WE must be HIGH during SRAM Read Cycles and LOW during SRAM WRITE cycles.
6. I/O state assumes CE and OE < V
IL
and WE > V
IH
; device is continuously selected.
7. Measured ±200 mV from steady state output voltage.
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STK11C88
Document Number: 001-50591 Rev. ** Page 9 of 15
SRAM Write Cycle
Parameter Description 25 ns 45 ns Unit
Min Max Min Max
Cypress
Parameter Alt
t
WC
t
AVAV
Write Cycle Time 25 45 ns
t
PWE
t
WLWH,
t
WLEH
Write Pulse Width 20 30 ns
t
SCE
t
ELWH,
t
ELEH
Chip Enable To End of Write 20 30 ns
t
SD
t
DVWH,
t
DVEH
Data Setup to End of Write 10 15 ns
t
HD
t
WHDX,
t
EHDX
Data Hold After End of Write 0 0 ns
t
AW
t
AVWH,
t
AVEH
Address Setup to End of Write 20 30 ns
t
SA
t
AVWL,
t
AVEL
Address Setup to Start of Write 0 0 ns
t
HA
t
WHAX,
t
EHAX
Address Hold After End of Write 0 0 ns
t
HZWE [7,8]
t
WLQZ
Write Enable to Output Disable 10 15 ns
t
LZWE [7]
t
WHQX
Output Active After End of Write 5 5 ns
Switching Waveforms
Figure 7. SRAM Write Cycle 1: WE Controlled
[9]
Figure 8. SRAM Write Cycle 2: CE Controlled
[9]
t
WC
t
SCE
t
HA
t
AW
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
ADDRESS
CE
WE
DATA IN
DATA OUT
DATA VALID
HIGH IMPEDANCE
PREVIOUS DATA
t
WC
ADDRESS
t
SA
t
SCE
t
HA
t
AW
t
PWE
t
SD
t
HD
CE
WE
DATA IN
DATA OUT
HIGH IMPEDANCE
DATA VALID
Notes
8. If WE is Low when CE goes Low, the outputs remain in the high impedance state.
9. CE or WE must be greater than V
IH
during address transitions.
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STK11C88
Document Number: 001-50591 Rev. ** Page 10 of 15
STORE INHIBIT or Power Up RECALL
Parameter Alt Description STK11C88 Unit
Min Max
t
HRECALL [10]
t
RESTORE
Power up RECALL Duration 550 μs
t
STORE [6]
t
HLHZ
STORE Cycle Duration 10 ms
V
RESET
Low Voltage Reset Level 3.6 V
V
SWITCH
Low Voltage Trigger Level 4.0 4.5 V
Switching Waveforms
Figure 9. STORE INHIBIT/Power Up RECALL
V
CC
V
SWITCH
V
RESET
POWER-UP RECALL
DQ (DATA OUT)
STORE INHIBIT
5V
tHRECALL
POWER-UP
RECALL
BROWN OUT
STORE INHIBIT
NO RECALL
(VCC DID NOT GO
BELOW VRESET)
BROWN OUT
STORE INHIBIT
NO RECALL
(VCC DID NOT GO
BELOW VRESET)
BROWN OUT
STORE INHIBIT
RECALL WHEN
VCC RETURNS
ABOVE VSWITCH
Notes
10.t
HRECALL
starts from the time V
CC
rises above V
SWITCH
.
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