Fujitsu FR Series Installation and operating instructions

Fujitsu Microelectronics Europe
Application Note
MCU-AN-300059-E-V11
FR FAMILY
32-BIT MICROCONTROLLER
MB91460
DIRECT MEMORY ACCESS
APPLICATION NOTE

DIRECT MEMORY ACCESS
Revision History
MCU-AN-300059-E-V11 - 2 - © Fujitsu Microelectronics Europe GmbH
Revision History
Date Issue
2008-04-22 First Version; MPi
2009-06-29 V1.1;MSt
Completed chapter 2.4.3 DMA Transfer and Interrupts
This document contains 29 pages.

DIRECT MEMORY ACCESS
Warranty and Disclaimer
©Fujitsu Microelectronics Europe GmbH - 3 - MCU-AN-300059-E-V11
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DIRECT MEMORY ACCESS
Contents
MCU-AN-300059-E-V11 - 4 - © Fujitsu Microelectronics Europe GmbH
Contents
REVISION HISTORY............................................................................................................ 2
WARRANTY AND DISCLAIMER ......................................................................................... 3
CONTENTS .......................................................................................................................... 4
1INTRODUCTION.............................................................................................................. 6
1.1 Key Features........................................................................................................... 6
2DIRECT MEMORY ACCESS ........................................................................................... 7
2.1 Block Diagram......................................................................................................... 7
2.2 Outline..................................................................................................................... 8
2.2.1 Single Transfer .......................................................................................... 8
2.2.2 Mult iple Transfers ..... . . . .... . . . . .... . . . . .... . . . ..... . . . .... . . . . .... . . . . .... . . . .... . . . . .... . . . . .... . . . . 9
2.3 Registers............................................................................................................... 10
2.3.1 Control/Status Registers A (DMACA0-4).................................................. 10
2.3.2 Control/Status Registers B (DMACB0-4).................................................. 11
2.3.3 Transfer Source Address Setting Register (DMASA0-4)........................... 12
2.3.4 Transfer Destination Address Setting Register (DMADA0-4).................... 12
2.3.5 DMAC All-Channel Control Register (DMACR).......................................... 13
2.4 Operation .............................................................................................................. 14
2.4.1 Transfer Mode ......................................................................................... 14
2.4.1.1 Step Transfer ........................................................................... 14
2.4.1.2 Block Transfer.......................................................................... 14
2.4.1.3 Burst Transfer .......................................................................... 15
2.4.1.4 Demand Transfer..................................................................... 15
2.4.2 Transfer Type .......................................................................................... 16
2.4.2.1 2-cycle Transfer ....................................................................... 16
2.4.2.2 Fly-by Transfer......................................................................... 16
2.4.3 DMA Transfer and Interrupts.................................................................... 16
2.4.4 External Transfer Requests ..................................................................... 17
2.4.5 External Bus Request Arbitration (BRQ) .................................................. 18
3DMAC EXAMPLES ........................................................................................................ 19
3.1 DMAC Example with External Bus......................................................................... 19
3.2 DMAC Example with UART................................................................................... 25
4ADDITIONAL INFORMATION ....................................................................................... 27
LIST OF FIGURES ............................................................................................................. 28

DIRECT MEMORY ACCESS
Contents
©Fujitsu Microelectronics Europe GmbH - 5 - MCU-AN-300059-E-V11
LIST OF TABLES............................................................................................................... 29

DIRECT MEMORY ACCESS
Chapter 1 Introduction
MCU-AN-300059-E-V11 - 6 - © Fujitsu Microelectronics Europe GmbH
1 Introduction
This application note describes the functionality of the Direct Memory Access Controller
(DMAC) and gives some examples.
The DMAC is mainly used to transfer data between a source and a destination memory
location without any CPU load. The direction can be from resource (peripheral) to memory
and vice versa. This transfer can be a single transfer or multiple transfers from single
address or an address area. DMA is always triggered by a resource interrupt and does not
interrupt the CPU until the transfer has ended.
1.1 KeyFeatures
•Byte / Half-word / Word Transfer
•Transfer from External Area / Built-in I/O / Internal RAM to External Area / Built-in I/O
/Internal RAM
•Entire space of 32-bit is addressable
•Step / Block / Bulk / Demand Transfers with possibility of update (increment or
decrement) of source and destination address with Reload
•Block Count and Transfer Count (with reload) registers available
•External input pin or built-in peripherals or software requests as DMAC transfer
request sources
•External Transfer requests available on DMAC channels 0 to 3
•DMA can be stopped by STOP request (supported by UART-Receive interrupt, in
case of receive error)

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2 Direct Memory Access
THE BASIC FUNCTIONALITY OF THE DMAC
2.1 BlockDiagram
The below figure shows the block diagram of DMAC of FR
Figure 2-1: Block Diagram of DMAC

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2.2 Outline
The DMAC is used to transfer data from one address (space) to another without involving
the CPU. The address space includes RAM, ROM, resource (except DMAC) registers or
external area.
2.2.1 SingleTransfer
The following diagram shows a standard interrupt sequence and a single transfer DMA
sequence:
Figure 2-2: Single Transfer
For a single transfer the DMA does not offer a real advantage against a standard interrupt.
Standard
Interrupt Sequence
DMA Sequence
Interrupt occurs
CPU Task CPU Task DMA Task
Application
Peripheral Interrupt
Service Routine
Application
Application
DMA Transfer
Interrupt occurs
DMAC Interrupt
Service Routine
Application
Application
End of DMA interrupts Application

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2.2.2 MultipleTransfers
The following diagram shows a standard interrupt sequence and a multiple transfer DMA
sequence:
Figure 2-3: Multiple Transfers
For a multiple transfer the DMAC advantage is obvious. During Transfer 3and 2the
application is not interrupted as in the standard interrupt sequence. Only after the Transfer 1,
the interrupt service routine of the DMAC is executed.
However, it should be also noted that the DMAC shares the same bus as of CPU, hence
during the time DMA is engaged in the data transfer the CPU is either waiting for the DMA to
finish the transfer or it is executing the code from the pre-fetch queue.
Standard
Interrupt Sequence
DMA Sequence
Interrupt occurs
CPU Task CPU Task DMA Task
Application
Peripheral Interrupt
Service Routine
Application
Application
Interrupt occurs
DMAC Interrupt
Service Routine
DMA Transfer 3Application
Application
End of DMA interrupts Application
Interrupt occurs
DMA Transfer 2
Application
Peripheral Interrupt
Service Routine
Application
Interrupt occurs
DMA Transfer 1
Application
Application
Interrupt occurs
Interrupt occurs
Peripheral Interrupt
Service Routine

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2.3 Registers
2.3.1 Control/Status Registers A (DMACA0-4)
These registers control the operation of the corresponding DMAC channel.
Bit
No. Name Explanation
Initial
Value Value Operation
31 DENB DMA Enable10
0Disables DMA operation on the
corresponding channel
1Enables DMA operation on the
corresponding channel
30 PAUS Pause 0
0Enables DMA operation on the
corresponding channel
1Temporarily stops DMA operation
on the corresponding channel
29 STRG Software
Trigger200Disabled
1DMA transfer request
28
…
24
IS4
…
IS0
Input Select30,0,0
,0,0
01110 -
10010
Selects the source for the transfer
request
23
…
20
EIS3
…
EIS0
Extended Input
Select3
0,0,0
,0
0000
-
0111
Selects the source for the transfer
request along with IS4-0 bits
19
…
16
BLK3
…
BLK0
Block Size4x
0000
-
1111
Selects the block size for
corresponding DMAC channel
15
…
0
DTC15
…
DTC00
DMA Terminal
Count x
0x0000
–
0xFFFF
Stores the transfer count for
corresponding DMAC channel
Table 2-1: DMACAn
1When the transfer on the corresponding channel reached the specified count, this bit gets cleared to
0.
2The software transfer request by the STRG bit function is always valid regardless of the setting of
these bits IS and EIS bits.
3Please refer the hardware manual for the transfer source selection.
4If all the bits of block size are 0, then the block size is 16 (times one transfer unit).

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2.3.2 Control/Status Registers B (DMACB0-4)
These registers control the operation of the corresponding DMAC channel.
Bit
No. Name Explanation
Initial
Value Value Operation
31
…
30
TYPE Transfer Type 0,0
0,0 2-cycle transfer
0,1 Fly-by: External Memory --> external
I/O transfer
1,0 Fly-by: external I/O --> external
memory transfer
1,1 Setting disabled
29
…
28
MOD Transfer Mode 0,0
0,0 Block/Step transfer
0,1 Burst transfer
1,0 Demand transfer
1,1 Setting disabled
27
…
26
WS Data Width 0,0
0,0 Byte transfer
0,1 Half-word transfer
1,0 Word transfer
1,1 Setting disabled
25 SADM
Source
Address Count
Mode Select
0
0Increment transfer source address
1Decrement transfer source address
24 DADM
Destination
Address Count
Mode Select
0
0Increment transfer destination
address
1Decrement transfer destination
address
23 DTCR
Transfer Count
Register
Reload
0
0Transfer count register reloading
disabled
1Transfer count register reloading
enabled
22 SADR
Source
Address
Register
Reload5
0
0Source address register reloading
disabled
1Source address register reloading
enabled
21 DADR
Destination
Address
Register
Reload5
0
0Destination address register reloading
disabled
1Destination address register reloading
enabled
20 ERIE
Error Interrupt
Request
Enable
00Error Interrupt Request enabled
1Error Interrupt Request disabled
19 EDIE
End Interrupt
Request
Enable
00End Interrupt Request enabled
1End Interrupt Request disabled
Table 2-2: DMACBn
5Source and destination address register reload feature is only valid if the Transfer count register
reload feature is enabled (DTCR = 1).

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Bit
No. Name Explanation
Initial
Value Value Operation
18 DSS2 End Code-1 0
0Initial Value
1DMA stopped temporarily due to
DMAH bit or PAUS bit or an interrupt)
17
…
16
DSS1
…
DSS0
End Code-2 0,0
0,0 Initial Value
0,1 Address error (underflow/overflow) –
ERIE
1,0 Transfer stop request – ERIE
1,1 Transfer ended normally – EDIE
15
…
8
SASZ7
…
SASZ0
Source
Address Count
Size
x -
Specifies the increment or decrement
width for the transfer source address
(DMASA)of the corresponding channel
in each transfer operation.
7
…
0
DASZ7
…
DASZ0
Destination
Address Count
Size
x -
Specifies the increment or decrement
width for the transfer destination
address (DMADA)of the
corresponding channel in each
transfer operation.
Table 2-3: DMACBn-II
2.3.3 Transfer Source Address Setting Register (DMASA0-4)
These registers select transfer source address.
2.3.4 Transfer Destination Address Setting Register (DMADA0-4)
These registers select transfer destination address.
Transfer source and destination address setting registers can’t be read when the transfer is
going on. If one tries to read them while the ongoing transfer, the address before the transfer
is read and if read after the transfer then the next access address is read.

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2.3.5 DMAC All-Channel Control Register (DMACR)
This register offers the master control for all five DMAC channels.
Bit
No. Name Explanation
Initial
Value Value Operation
31 DMAE DMA Enable 0
0DMAC transfer on all channels
disabled
1DMAC transfer on all channels
enabled
30
…
29
--x x -
28 PM01 Priority Mode 0
0Fixed priority (ch0 > ch1)
1Alternating priority (ch1 > ch0)
27
…
24
DMAH3
…
DMAH0
DMA Halt 0
0,0,0,0 DMAC operation on all channels
enabled
0,0,0,1
-
1,1,1,1
DMAC operation on all channels
temporarily stopped
23
…
0
--x x -
Table 2-4: DMACR

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2.4 Operation
The DMAC has 5 channels and all these 5 channel functions can be set independently of
each other.
2.4.1 TransferMode
Each DMAC channel performs transfer according to the transfer mode set by the MOD[1:0]
bits of its DMACB register.
2.4.1.1 StepTransfer
Step transfer is performed when the block size (BLK[3:0] of DMACA)is specified as 1 in the
block transfer mode (MOD[1:0] = 0 of DMABA).
1. In case of step transfer after the transfer request is received, one transfer operation
(of single byte/half-word/word as specified by WS[1:0] bits of DMABA)is performed.
2. The peripheral interrupt, if any, which had initiated the transfer request gets cleared
by DMAC
3. Then the transfer is stopped with DSS[1:0] of DMABA register gets set to B’11
indicating transfer ended normally.
4. After the transfer end the DMASA,DMADA registers and BLK[1:0] and DTC[15:00]
bits of DMACA register gets updated accordingly.
If there is one more transfer request during the transfer is happening then it would be
ignored.
2.4.1.2 BlockTransfer
Block transfer is performed when the block size (BLK[3:0] of DMACA)is specified as any
value greater than 1 in the block transfer mode (MOD[1:0] = B’00 of DMABA).
1. In case of block transfer after the transfer request is received, a single block transfer
unit is transferred and then the transfer is stopped. If WS[1:0] of DMABA is B’10 and
BLK[3:0] of DMACA is B’1010, then the single block transfer unit would be 10 (32-
bit) words.
2. After this the DMASA,DMADA registers gets updated accordingly.
3. TheBLK[1:0] of DMACA register become 0 and DTC[15:0] bits of DMACA register
gets decremented by 1.
4. The peripheral interrupt, if any, which had initiated the transfer request, gets cleared
by DMAC.
5. Then the DMAC waits for next transfer request. During this time the CPU can get
access of the buses until the DMAC gets next transfer request.
6. Upon getting the next such transfer requests steps 1 to 4 are performed unless and
until the DTC[15:0] becomes 0.
7. OncetheDTC[15:0] becomes 0, the transfer is stopped with DSS[1:0] of DMABA
register gets set to B’11 indicating transfer ended normally.
8. If the reload is enabled then the DMAC waits for next transfer request.

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2.4.1.3 BurstTransfer
For the burst transfer mode, MOD[1:0] bits of DMABA needs to be set as B’01.
1. In case of block transfer after the transfer request is received, transfer is carried out
continuously as specified by the transfer count and then the transfer is stopped. If
WS[1:0] of DMABA is B’10, BLK[3:0] of DMACA is B’1010 and DTC[15:0] is 0x10
then transfer would be carried out continuously until 160 (32-bit)words are
transferred.
2. DTC[15:0] bits of DMACA register would get decremented to 0.
3. After this the DMASA,DMADA registers gets updated accordingly.
4. OncetheDTC[15:0] becomes 0, the transfer is stopped with DSS[1:0] of DMABA
register gets set to B’11 indicating transfer ended normally.
5. The peripheral interrupt, if any, which had initiated the transfer request, gets cleared
by DMAC.
6. If the reload is enabled then the DMAC waits for next transfer request.
7. During this time the CPU can get access of the buses until the DMAC gets next
transfer request.
2.4.1.4 DemandTransfer
For the demand transfer mode, MOD[1:0] bits of DMABA needs to be set as B’10. The
number of block remain always 1 and the BLK[3:0] bit setting of DMACA is ignored. The
transfer source should be selected as high level or low level at DMAC external pin (DREQ)
by configuring IS[4:0] bits of DMACA register as B’01110 or B’01111 respectively. As long
as the level at the DREQ pin is maintained as per the configuration of IS[4:0] bits, the
transfer request is considered to be active.
1. In case of demand transfer after the transfer request is received (that is the signal
level at the DREQ pin is as per as per the configuration of IS[4:0] bits), a single
transfer is performed. If WS[1:0] of DMABA is B’10 then one (32-bit) word would be
transferred.
2. DTC[15:0] bits of DMACA register gets decremented by 1.
3. After this the DMASA,DMADA registers gets updated accordingly.
4. If the transfer request is not active anymore then the DMAC waits for the transfer
request (configured level at DREQ). During this time the CPU can get access of the
buses until the DMAC gets next transfer request.
5. If the transfer request is still active steps 1 to 3 are repeated until the DTC[15:0]
becomes 0.
6. OncetheDTC[15:0] becomes 0, the transfer is stopped with DSS[1:0] of DMABA
register gets set to B’11 indicating transfer ended normally.
7. The peripheral interrupt, if any, which had initiated the transfer request, gets cleared
by DMAC.
8. If the reload is enabled then the DMAC waits for next transfer request.

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2.4.2 TransferType
2.4.2.1 2-cycleTransfer
In 2-cycle transfer the DMAC performs 2 operations sequentially. Upon receiving the
transfer request it reads the data from an address specified in the transfer source register
DMASA and then writes it to the address as specified by transfer destination register DMADA.
In case of block/step 2-cycle transfer all areas accessible by 32-bit addressing are
specifiable, however for demand 2-cycle transfer make sure to set an external area address
as transfer source or transfer destination or both.
2.4.2.2 Fly-byTransfer
Fly-by transfer is used when the data needs to be transferred from one external peripheral to
the other or vice a versa such as external memory, external I/O etc.
External Memory to External I/O:
In this case the DMAC operates using a read operation as its unit of operation. DMAC issues
afly-by transfer (read) request to the bus controller and the bus controller in turn issues the
read command to the external memory and at the same time it also issues write command to
the external I/O. Simultaneously the bus controller floats the address and data bus with the
appropriate content. Hence two sequential operations (read followed by write) are replaced
by two simultaneous operations (read with write).
External I/O to External Memory:
In this case the DMAC operates using a write operation as its unit of operation. DMAC
issues a fly-by transfer (read) request to the bus controller and the bus controller in turn
issues the write command to the external memory and at the same time it also issues read
command to the external I/O. Simultaneously the bus controller floats the address and data
bus with the appropriate content. Hence two sequential operations (read followed by write)
are replaced by two simultaneous operations (read with write).
For Fly-by transfer the value configured in the transfer destination address register DMADA is
used as the address for access and it should point to the external area where as the transfer
destination address register DMASA is ignored.
2.4.3 DMA Transfer and Interrupts
By default the DMAC has the access of D-Bus. Whether the CPU is executing any function
or interrupt service routine the DMAC can request the CPU for the D-Bus by asserting D-Bus
hold request (DHREQ), the CPU in turn would respond to this DMA request by D-Bus hold
acknowledge (DHACK) granting the access of the D-Bus to the DMA.
In such situation NMI or peripheral interrupt can cancel the hold request (depending upon
configuration of LVL bits if HRCL register) and gain the access of the bus while
corresponding ISR executes. Upon execution of RETI instruction the DMA would gain
access to the D-Bus again (provided the MHALTI flag and the corresponding peripheral
interrupt flag is cleared in the ISR).
During DMA transfer, interrupts are generally not accepted until the transfer ends.
•If a DMA transfer request occurs during interrupt processing, the transfer request is
accepted and interrupt processing is stopped until the transfer is completed.
•If, as an exception, an NMI request or an interrupt request with a higher level than the hold
suppress level set by the interrupt controller occurs, DMAC temporarily cancels the transfer
request via the bus controller at a transfer unit boundary (one block) to temporarily stop the
transfer until the interrupt request is cleared. In the meantime, the transfer request is
retained internally. After the interrupt request is cleared, DMAC reissues a transfer request
to the bus controller to acquire the right to use the bus and then restarts DMA transfer.

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When the high priority interrupt occurs (NMI or interrupt priority higher than that specified by
LVL bits if HRCL register) during the DMAC transfer, the DMAC transfer gets temporarily
stopped by the hold request cancel request from NMI or by the peripheral. The
corresponding ISR starts getting executed. Now within this ISR if the corresponding interrupt
flag is cleared then DMAC transfer is restarted. In this case to continue suppressing the
DMAC transfer, the DMAH[3:0] bits of DMACR register should be incremented by 1 before
clearing the interrupt flag and it should be decremented by 1 before leaving the ISR. This is
how the DMAC transfer would be suppressed until the execution of ISR. In such case the
DMAC transfer would be continued before the execution of RETI instruction.
In case of nested interrupts the DMAC transfer would be only continued after the lowest
priority interrupt (interrupt with the lowest priority among the pending interrupt but priority
higher than that specified by LVL bits if HRCL register) finishes execution.
2.4.4 External Transfer Requests
Sr.
No
Pin
Name Description Functionality
1DREQ ExternalTransfer
Request Input Pin

External transfer request can be issued over
DREQ pin.
The configurable levels are low level or high level
and the configurable edges are rising edge or
falling edge.
It should be noted that the minimum width of the
signal appearing at DREQ should be 5 system
clock cycles.
2DACKX External Transfer
Request
Acknowledgement
Output Pin

This is an acknowledgement signal with reference
to DREQ. It indicates that the external transfer
with respect to the transfer request is performed
and usually being asserted during the external bus
access.
In the 2-cycle transfer it is asserted either while the
external source or while the external destination is
being accessed.
In the fly-by transfer it is continuous asserted since
the source as well as the destination is external.
3DEOP DMA End Output
Pin

Signal on this pin indicates that the DMAC transfer
is performed for specified number of times.
DEOP is asserted while the last data item of the
last block is being transferred
If the transfer source and destination is internal
then the DEOP is not asserted.
4DEOTX External Transfer
Stop Pin

Using this pin the ongoing DMAC transfer can be
forcibly stopped.
If the transfer is stopped using this pin then the
DMAH[2:0] bits of the DMACB register would
transfer stop request. Interrupt may be generated if
it is enabled.
It should be noted that this pin shared with DEOP.
The minimum width of the signal appearing at
DEOTX pin should be 5 system clock cycles.
Table 2-5: External Transfer Request

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2.4.5 External Bus Request Arbitration (BRQ)
When a device is operating in external bus extended mode, an external bus request (BRQ)
function can be used. Using BRQ pin any external peripheral can request to use the external
bus for the configured chip select area.
While the BRQ is asserted by any external device and the access is granted. Then such
external device controls the external bus and performs the data transfer. During such
transfer, if DMAC requires to use the external bus for the transfer, the DMAC has to wait
until the BRQ is active. Once BRQ is released the DMAC can use external bus.
If the DMAC is already using the external bus and the BRQ is asserted DMAC transfer is
temporarily stopped. Once BRQ is released the DMAC can use external bus.
If the DMAC transfer through the external bus and BRQ is simultaneous then DMAC waits till
the external device finishes transfer and then DMAC takes over.

DIRECT MEMORY ACCESS
Chapter 3 DMAC Examples
©Fujitsu Microelectronics Europe GmbH - 19 - MCU-AN-300059-E-V11
3DMAC Examples
EXAMPLES FOR DIRECT MEMORY ACCESS CONTROLLER
3.1 DMAC Example with External Bus
The following example demonstrates how to configure the DMAC channel 0 with external
transfer requests. Here the falling edge on DREQ0 pin triggers the DMAC transfer. Upon
such trigger the DMA transfers 1 block of data (which comprises of 4 words) from the
internal RAM to the external ram connected via external bus starting from address
0x20000000.The DTC is set as 4, hence after transferring such 4 blocks of data (in
response to 4 falling edges), the DMAC0 interrupt is generated. In the DMAC0 ISR the
source and destination array is compared. If there is any mismatch then 0xAA is ouput on
LEDs connected to Port 16, otherwise 0xFF is ouput on the LEDs.
In order to place the dst_buff[] at the external area starting from address 0x20000000,
the ROM/RAM area needs to be set up as below:
Figure 3-1: Setup ROM/RAM Area
The above dialog box can be reached as mentioned below…
Project -> Setup Project -> Linker -> Disposition Connection -> ROM/RAM Area List -> Set
After doing this, the external bus should be configured using the Start91460.asm as below:
Enabling External Bus interface
;======================================================================================
; 4.8 External Bus Interface
; The rest of the configuration is only applicable for devices with an external bus
; interface.
; If the device does not offer an external bus interface, the configuration can be
; stopped at this point.
;=======================================================================================
;
#set EXTBUS ON ; <<< Ext. Bus on/off
;
; Note: This feature is not supported by every device. Please check the data sheet. The
; Following devices for example do not offer an external bus interface: MB91464A,
; MB91467C, MB91465K, MB91463N, MB91465X.
;
;=======================================================================================

DIRECT MEMORY ACCESS
Chapter 3 DMAC Examples
MCU-AN-300059-E-V11 - 20 - © Fujitsu Microelectronics Europe GmbH
Enabling chip select 
Set momory addressing 
; 4.8.1 Select Chip select (Only EXTBUS == ON)
;======================================================================================
;
#set CS0 OFF ; <<< select CS (ON/OFF)
#set CS1 ON ; <<< select CS (ON/OFF)
#set CS2 OFF ; <<< select CS (ON/OFF)
#set CS3 OFF ; <<< select CS (ON/OFF)
#set CS4 OFF ; <<< select CS (ON/OFF)
#set CS5 OFF ; <<< select CS (ON/OFF)
#set CS6 OFF ; <<< select CS (ON/OFF)
#set CS7 OFF ; <<< select CS (ON/OFF)
#set SDRAM OFF ; <<< select if a SDRAM is connected
;
#set ENACSX B'00000010 ; <<< set CS, ENACSX
; ||||||||
; ||||||||__ CS0 bit, enable/disable CS0 (1/0)
; |||||||___ CS1 bit, enable/disable CS1 (1/0)
; ||||||____ CS2 bit, enable/disable CS2 (1/0)
; |||||_____ CS3 bit, enable/disable CS3 (1/0)
; ||||______ CS4 bit, enable/disable CS4 (1/0)
; |||_______ CS5 bit, enable/disable CS5 (1/0)
; ||________ CS6 bit, enable/disable CS6 (1/0)
; |_________ CS7 bit, enable/disable CS7 (1/0)
;
; Note: If the SWB Monitor Debugger is used, set the CS1 (external RAM only) or CS0 and
; CS 1 (external RAM and flash) to off.
; Note: Not all Chip selects are supported by the different devices. Please check the
; data sheet.
;======================================================================================
; 4.8.2 Set memory addressing for Chip selects (only EXTBUS == ON)
;======================================================================================
#set AREASEL0 0x0020 ; <<< set start add. for CS0, ASR0
#set AREASEL1 0x2000
; <<< set start add. for CS1, ASR1
#set AREASEL2 0x0000 ; <<< set start add. for CS2, ASR2
#set AREASEL3 0x0000 ; <<< set start add. for CS3, ASR3
#set AREASEL4 0x0000 ; <<< set start add. for CS4, ASR4
#set AREASEL5 0x0000 ; <<< set start add. for CS5, ASR5
#set AREASEL6 0x3000 ; <<< set start add. for CS6, ASR6
#set AREASEL7 0x0000 ; <<< set start add. for CS7, ASR7
; Configure the starting address of each used Chip select. Chip selects which are not
; used (not set to ON in "Select Chip select") need not be set (setting ignored).
;
; NOTE: Just the upper 16-bit of the start address must be set, e.g. when using start
; a
ddress 0x00080000 set 0x0008.