Nuvoton Mini51 Series Product manual

NuMicro™ Mini51 Technical Reference Manual
ARM Cortex™-M0
32-BIT MICROCONTROLLER
NUMICRO™ MINI51 TECHNICAL REFERENCE MANUAL
NuMicro™Family
Mini51 Series
Technical Reference Manual
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based system
design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com

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CONTENTS
1GENERAL DESCRIPTION ...................................................................................................10
2FEATURES ...........................................................................................................................11
3PARTS INFORMATION LIST AND PIN CONFIGURATION ................................................14
3.1 NuMicro Mini51Series Product Selection Guide ....................................................14
3.2 PIN CONFIGURATION ..............................................................................................15
3.2.1 LQFP 48-pin .................................................................................................................. 15
3.2.2 QFN 33-pin.................................................................................................................... 16
3.3 Pin Description ...........................................................................................................17
4BLOCK DIAGRAM ................................................................................................................21
4.1 NuMicro Mini51™ Block Diagram ..............................................................................21
5FUNCTIONAL DESCRIPTION..............................................................................................22
5.1 Memory Organization.................................................................................................22
5.1.1 Overview........................................................................................................................ 22
5.1.2 System Memory Map..................................................................................................... 23
5.2 Nested Vectored Interrupt Controller (NVIC) .............................................................24
5.2.1 Overview........................................................................................................................ 24
5.2.2 Features ........................................................................................................................ 24
5.2.3 Exception Model and System Interrupt Map.................................................................. 24
5.2.4 Vector Table .................................................................................................................. 26
5.2.5 NVIC Operation ............................................................................................................. 27
5.2.6 NVIC Control Registers ................................................................................................. 28
5.2.7 Interrupt Source Control Registers ................................................................................ 41
5.3 System Manager ........................................................................................................47
5.3.1 Overview........................................................................................................................ 47
5.3.2 System Reset ................................................................................................................ 47
5.3.3 System Power Distribution............................................................................................. 47
5.3.4 Memory Mapping Table................................................................................................. 49
5.3.5 System Manager Control Registers............................................................................... 50
5.4 Clock Controller..........................................................................................................75
5.4.1 Overview........................................................................................................................ 75
5.4.2 Clock Generator............................................................................................................. 75
5.4.3 System Clock and SysTick Clock .................................................................................. 76
5.4.4 AHB Clock Source Selection......................................................................................... 77
5.4.5 Peripheral Clock Source Selection ................................................................................ 78
5.4.6 Power-down Mode Clock............................................................................................... 80
5.4.7 Frequency Divider Output.............................................................................................. 81
5.4.8 Clock Control Register Map........................................................................................... 82
5.4.9 Clock Control Register................................................................................................... 83
5.5 Comparator Controller (CMPC)..................................................................................98
5.5.1 Overview........................................................................................................................ 98
5.5.2 Features ........................................................................................................................ 98
5.5.3 Block Diagram ............................................................................................................... 99
5.5.4 Functional Description................................................................................................. 100

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5.5.5 Comparator Reference Voltage (CRV)........................................................................ 101
5.5.6 Register Map ............................................................................................................... 102
5.5.7 Register Description .................................................................................................... 103
5.6 Analog-to-Digital Converter (ADC) Controller ..........................................................107
5.6.1 Overview...................................................................................................................... 107
5.6.2 Features ...................................................................................................................... 107
5.6.3 Block Diagram ............................................................................................................. 108
5.6.4 ADC Operation Procedure........................................................................................... 108
5.6.5 ADC Register Map....................................................................................................... 111
5.6.6 ADC Register............................................................................................................... 112
5.7 Flash Memory Controller (FMC)...............................................................................121
5.7.1 Overview...................................................................................................................... 121
5.7.2 Features ...................................................................................................................... 121
5.7.3 Block Diagram ............................................................................................................. 121
5.7.4 Functional Description................................................................................................. 123
5.7.5 Flash Control Register Map......................................................................................... 133
5.7.6 Flash Control Register................................................................................................. 134
5.8 General Purpose I/O ................................................................................................142
5.8.1 Overview...................................................................................................................... 142
5.8.2 Features ...................................................................................................................... 142
5.8.3 Functional Description................................................................................................. 142
5.8.4 Port 0-5 Control Register Map..................................................................................... 145
5.8.5 Port 0-5 Control Register............................................................................................. 149
5.9 I2C Serial Interface Controller (Master/Slave)..........................................................167
5.9.1 Overview...................................................................................................................... 167
5.9.2 Features ...................................................................................................................... 167
5.9.3 I2C Protocol.................................................................................................................. 168
5.9.4 I2C Protocol Registers ................................................................................................. 171
5.9.5 Register Mapping......................................................................................................... 174
5.9.6 Register Description .................................................................................................... 175
5.9.7 Operation Modes......................................................................................................... 184
5.9.8 Master Transmitter Mode............................................................................................. 184
5.9.9 Master Receiver Mode................................................................................................. 184
5.9.10 Slave Receiver Mode................................................................................................. 184
5.9.11 Slave Transmitter Mode............................................................................................. 184
5.9.12 Data Transfer Flow in Five Operation Modes ............................................................ 184
5.10 Enhanced PWM Generator ......................................................................................191
5.10.1 Overview.................................................................................................................... 191
5.10.2 Features .................................................................................................................... 191
5.10.3 PWM Block Diagram.................................................................................................. 193
5.10.4 PWM Function........................................................................................................... 195
5.10.5 PWM Operation Modes ............................................................................................. 203
5.10.6 Polarity Control.......................................................................................................... 204
5.10.7 PWM for Motor Control Interrupt Architecture............................................................ 206
5.10.8 PWM Brake Function................................................................................................. 206
5.10.9 PWM Controller Register Map................................................................................... 207

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5.10.10 PWM Controller Register......................................................................................... 208
5.11 Serial Peripheral Interface (SPI) Controller..............................................................228
5.11.1 Overview.................................................................................................................... 228
5.11.2 Features .................................................................................................................... 228
5.11.3 SPI Block Diagram..................................................................................................... 228
5.11.4 Functional Description............................................................................................... 229
5.11.5 SPI Serial Interface Control Register Map................................................................. 239
5.11.6 Register Description .................................................................................................. 240
5.12 Timer Controller........................................................................................................251
5.12.1 Overview.................................................................................................................... 251
5.12.2 Features .................................................................................................................... 251
5.12.3 Block Diagram ........................................................................................................... 252
5.12.4 Functional Description............................................................................................... 253
5.12.5 Register Map ............................................................................................................. 257
5.12.6 Register Description .................................................................................................. 258
5.13 UART Interface Controller........................................................................................267
5.13.1 Overview.................................................................................................................... 267
5.13.2 Features .................................................................................................................... 269
5.13.3 Block Diagram ........................................................................................................... 270
5.13.4 Functional Description............................................................................................... 273
5.13.5 Registers Map............................................................................................................ 278
5.13.6 Register Description .................................................................................................. 279
5.14 Watchdog Timer.......................................................................................................302
5.14.1 Overview.................................................................................................................... 302
5.14.2 Features .................................................................................................................... 303
5.14.3 Block Diagram ........................................................................................................... 303
5.14.4 Watchdog Timer Control Registers Map.................................................................... 305
5.14.5 Register Description .................................................................................................. 306
6ARM®CORTEX™-M0 CORE .............................................................................................309
6.1 Overview...................................................................................................................309
6.2 Features ...................................................................................................................310
6.3 System Timer (SysTick) ...........................................................................................311
6.3.1 System Timer Control Register Map............................................................................ 312
6.3.2 System Timer Control Register.................................................................................... 313
6.4 System Control Registers.........................................................................................316
6.4.1 System Control Register Memory Map........................................................................ 316
6.4.2 System Control Register.............................................................................................. 317
7APPLICATION CIRCUIT.....................................................................................................324
8ELECTRICAL CHARACTERISTICS...................................................................................325
8.1 Absolute Maximum Ratings......................................................................................325
8.2 DC Electrical Characteristics....................................................................................326
8.3 AC Electrical Characteristics....................................................................................331
8.3.1 External Input Clock..................................................................................................... 331
8.3.2 External 4 ~ 24 MHz XTAL Oscillator.......................................................................... 331

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8.3.3 Typical Crystal Application Circuit................................................................................ 331
8.3.4 External 32.768 KHz XTAL Oscillator.......................................................................... 332
8.3.5 Internal 22.1184 MHz RC Oscillator ............................................................................ 332
8.3.6 Internal 10 KHz RC Oscillator...................................................................................... 333
8.4 Analog Characteristics .............................................................................................334
8.4.1 Brown-Out Reset (BOD).............................................................................................. 334
8.4.2 Low Voltage Reset (LVR)............................................................................................ 334
8.4.3 Analog Comparator...................................................................................................... 334
8.4.4 Analog Comparator Reference Voltage (CRV)............................................................ 335
8.4.5 10-bit ADC................................................................................................................... 335
8.4.6 Flash Memory Characteristics ..................................................................................... 337
9PACKAGE DIMENSION......................................................................................................338
9.1 48-pin LQFP.............................................................................................................338
9.2 33-pin QFN (4mm x 4mm)........................................................................................339
9.3 33-pin QFN (5mm x 5mm)........................................................................................340
10 REVISION HISTORY..........................................................................................................341

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List of Figures
Figure 3.1-1 NuMicro Mini51Series Product Selection Guide....................................................14
Figure 3.2-1 NuMicro Mini51Series LQFP 48-pin Assignment ..................................................15
Figure 3.2-2 NuMicro Mini51Series QFN 33-pin Assignment....................................................16
Figure 4.1-1 NuMicro Mini51Series Block Diagram ...................................................................21
Figure 5.3-1 NuMicro Mini51Series Power Distribution Diagram...............................................48
Figure 5.4-1 Clock Generator Block Diagram................................................................................75
Figure 5.4-2 System Clock Block Diagram ....................................................................................76
Figure 5.4-3 SysTick Clock Control Block Diagram.......................................................................76
Figure 5.4-4 AHB Clock Source for HCLK.....................................................................................77
Figure 5.4-5 Peripherals Clock Source Selection for PCLK...........................................................78
Figure 5.4-6 Clock Source of Frequency Divider...........................................................................81
Figure 5.4-7 Block Diagram of Frequency Divider.........................................................................81
Figure 5.5-1 Analog Comparator Block Diagram...........................................................................99
Figure 5.5-2 Comparator Controller Interrupt Sources ................................................................100
Figure 5.5-3 Comparator Reference Voltage Block Diagram ......................................................101
Figure 5.6-1 ADC Controller Block Diagram................................................................................108
Figure 5.6-2 ADC Clock Control...................................................................................................109
Figure 5.6-3 A/D Conversion Result Monitor Logics Diagram.....................................................110
Figure 5.6-4 A/D Controller Interrupt............................................................................................110
Figure 5.7-1 Flash Memory Control Block Diagram.....................................................................122
Figure 5.7-2 Flash Memory Organization.....................................................................................124
Figure 5.7-3 Flash Memory Structure ..........................................................................................126
Figure 5.7-4 ISP Procedure..........................................................................................................130
Figure 5.7-5 ISP Operation Flow..................................................................................................131
Figure 5.8-1 Push-Pull Output......................................................................................................143
Figure 5.8-2 Open-Drain Output ..................................................................................................143
Figure 5.8-3 Quasi-bidirectional I/O Mode ...................................................................................144
Figure 5.9-1 Bus Timing...............................................................................................................167
Figure 5.9-2 I2C Protocol..............................................................................................................168
Figure 5.9-3 Master Transmits Data to Slave ..............................................................................168
Figure 5.9-4 Master Reads Data from Slave................................................................................169
Figure 5.9-5 START and STOP Condition...................................................................................169
Figure 5.9-6 Bit Transfer on the I2C Bus......................................................................................170
Figure 5.9-7 Acknowledge on the I2C Bus ...................................................................................171
Figure 5.9-8 I2C Data Shifting Direction.......................................................................................172

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Figure 5.9-9 I2C Time-out Count Block Diagram..........................................................................173
Figure 5.9-10 Legend for the Following Five Figures ..................................................................185
Figure 5.9-11 Master Transmitter Mode.......................................................................................186
Figure 5.9-12 Master Receiver Mode...........................................................................................187
Figure 5.9-13 Slave Transmitter Mode.........................................................................................188
Figure 5.9-14 Slave Receiver Mode.............................................................................................189
Figure 5.9-15 GC Mode................................................................................................................190
Figure 5.10-1 Application Circuit Diagram ...................................................................................192
Figure 5.10-2 PWM Block Diagram..............................................................................................193
Figure 5.10-3 PWM Generator 0 Architecture Diagram...............................................................193
Figure 5.10-4 PWM Generator 2 Architecture Diagram...............................................................194
Figure 5.10-5 PWM Generator 4 Architecture Diagram...............................................................194
Figure 5.10-6 Edge-aligned PWM................................................................................................196
Figure 5.10-7 PWM Edge-aligned Waveform Output ..................................................................196
Figure 5.10-8 Edge-aligned Flow Diagram ..................................................................................197
Figure 5.10-9 Legend of Internal Comparator Output of PWM-Timer .........................................198
Figure 5.10-10 PWM Timer Operation Timing.............................................................................198
Figure 5.10-11 Center-aligned Mode ...........................................................................................199
Figure 5.10-12 PWM Center-aligned Waveform Output..............................................................200
Figure 5.10-13 Center-aligned Flow Diagram (INT_TYPE = 0)...................................................201
Figure 5.10-14 PWM Double Buffering Illustration.......................................................................202
Figure 5.10-15 PWM Controller Output Duty Ratio......................................................................202
Figure 5.10-16 Dead-zone Insertion ............................................................................................203
Figure 5.10-17 Initial State and Polarity Control with Rising Edge Dead-zone Insertion.............205
Figure 5.10-18 Motor Control PWM Architecture.........................................................................206
Figure 5.11-1 SPI Block Diagram.................................................................................................228
Figure 5.11-3 SPI Slave Mode Application Block Diagram..........................................................229
Figure 5.11-4 Two Transfer (Burst Mode) in One Transaction....................................................231
Figure 5.11-5 Word Suspend Mode.............................................................................................231
Figure 5.11-6 Byte Reorder..........................................................................................................232
Figure 5.11-7 Byte Suspend Mode ..............................................................................................232
Figure 5.11-8 Variable Serial Clock Frequency...........................................................................233
Figure 5.11-9 SPI Timing in Master Mode ...................................................................................234
Figure 5.11-10 SPI Timing in Master Mode (Alternate Phase of SPICLK) ..................................235
Figure 5.11-11 SPI Timing in Slave Mode ...................................................................................235
Figure 5.11-12 SPI Timing in Slave Mode (Alternate Phase of SPICLK) ....................................236

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Figure 5.12-1 Timer Controller Block Diagram.............................................................................252
Figure 5.12-2 Clock Source of Timer Controller...........................................................................252
Figure 5.12-3 Continuous Counting Mode...................................................................................254
Figure 5.13-1 UART Clock Control Diagram................................................................................270
Figure 5.13-2 UART Block Diagram.............................................................................................271
Figure 5.13-3 Auto Flow Control Block Diagram..........................................................................273
Figure 5.13-4 IrDA Block Diagram ...............................................................................................274
Figure 5.13-5 IrDA TX/RX Timing Diagram..................................................................................275
Figure 5.13-6 Structure of RS-485 Frame....................................................................................277
Figure 5.14-1 Timing of Interrupt and Reset Signal.....................................................................303
Figure 5.14-2 Watchdog Timer Clock Control..............................................................................303
Figure 5.14-3 Watchdog Timer Block Diagram............................................................................304
Figure 6.1-1 Functional Block Diagram........................................................................................309
Figure 8.3-1 Typical Crystal Application Circuit ...........................................................................332

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List of Tables
Table 3.3-1 NuMicro Mini51Series Pin Description....................................................................20
Table 5.1-1 Address Space Assignments for On-Chip Modules....................................................23
Table 5.2-1 Exception Model .........................................................................................................25
Table 5.2-2 System Interrupt Map..................................................................................................26
Table 5.2-3 Vector Table Format...................................................................................................26
Table 5.3-1 Memory Mapping Table..............................................................................................49
Table 5.4-1 Peripherals Engine Clock Source Selection Table.....................................................79
Table 5.4-2 Power-down Mode Control Table ...............................................................................85
Table 5.7-1 Memory Address Map...............................................................................................123
Table 5.7-2 Boot Selection Table.................................................................................................125
Table 5.7-3 Data Flash Table.......................................................................................................125
Table 5.7-4 Data Flash Configuration Example...........................................................................129
Table 5.7-5 ISP Command Table.................................................................................................132
Table 5.11-1 Byte Order and Byte Clock Idle Internal Conditions ...............................................233
Table 5.12-1 Input Capture Mode Operation ...............................................................................255
Table 5.13-1 UART Baud Rate Setting Table..............................................................................267
Table 5.13-2 UART Baud Rate Setting Table..............................................................................267
Table 5.13-3 UART Interrupt Sources and Flags Table In Software Mode .................................294
Table 5.13-4 UART Baud Rate Setting Table..............................................................................297
Table 5.14-1 Watchdog Time-out Interval Selection....................................................................302

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1 GENERAL DESCRIPTION
The NuMicro Mini51™series 32-bit microcontroller is embedded with an ARM®Cortex™-M0 core
for industrial controls and applications which require high performance, high integration, and low
cost. The Cortex™-M0 is the newest ARM embedded processor with 32-bit performance at a cost
equivalent to the traditional 8-bit microcontroller.
The NuMicro Mini51™series can run up to 24 MHz, and thus can afford to support a variety of
industrial controls and applications requiring high CPU performance. The NuMicro Mini51™series
provides 4K/8K/16K-byte embedded program flash, size configurable data flash (shared with
program flash), 2K-byte flash for the ISP, and 2K-byte embedded SRAM.
A number of system-level peripheral functions, such as I/O Port, Timer, UART, SPI, I2C, PWM,
ADC, Watchdog Timer, and low voltage detector, have been incorporated in the NuMicro Mini51™
series to reduce component count, board space, and system cost. These useful functions make
the NuMicro Mini51™series powerful for a wide range of applications.
Additionally, the NuMicro Mini51™series is equipped with ISP (In-System Programming) and ICP
(In-Circuit Programming) functions, allowing user to update program memory without removing a
chip from an actual end product.

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2 FEATURES
Core
ARM®Cortex™-M0 core running up to 24 MHz
One 24-bit system timer
Supports low power Idle mode
A single-cycle 32-bit hardware multiplier
NVIC for 32 interrupt inputs, each with 4-level priority
Supports Serial Wire Debug (SWD) with 2 watchpoints/4 breakpoints
Built-in LDO for Wide Operating Voltage Range: 2.5V to 5.5V
Memory
4KB/8KB/16KB flash memory for program memory (APROM)
Configurable flash memory for data memory (Data Flash)
2KB flash memory for loader (LDROM)
2KB SRAM for internal scratch-pad RAM (SRAM)
In-System Programming (ISP) and In-Circuit Programming (ICP)
Clock Control
Programmable system clock source
Switch clock sources on-the-fly
4 ~ 24 MHz crystal oscillator (HXT)
32.768K crystal oscillator (LXT) for idle wake-up and system operation clock
22.1184 MHz internal oscillator (HIRC) (1% accuracy at 250C, 5V)
Dynamically calibrating the HIRC OSC to 22.0 MHz ±1% from -400C to 850C
by external 32.768K crystal oscillator (LXT)
10 KHz internal low-power oscillator (LIRC) for watchdog and idle wake-up
I/O Port
Up to 30 GPIO (General Purpose I/O) pins for LQFP-48 package
Software-configured I/O type
Quasi-bidirectional input/output
Push-pull output
Open-drain output
Input-only (high impendence)
Optional Schmitt trigger input
Timer
Two 24-bit Timers with 8-bit prescaler
Supports Event Counter mode
Supports Toggle Output mode

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Supports external trigger in Pulse Width Measurement mode
Supports external trigger in Pulse Width Capture mode
Watchdog Timer
Programmable clock source and time-out period
Supports wake-up function in Power-down mode and Idle mode
Interrupt or reset selectable when time-out happens
PWM
Up to three built-in 16-bit PWM generators with six PWM outputs or three
complementary paired PWM outputs
Supports edge alignment or center alignment
Supports fault detection
Individual clock source, clock divider, 8-bit prescalar and dead-zone generator for
each PWM generator
PWM interrupt synchronized to PWM period
UART (Universal Asynchronous Receiver/Transmitters)
One UART device
Buffered receiver and transmitter with 16-byte FIFO
Optional flow control function (CTSn and RTSn)
Supports IrDA (SIR) function
Programmable baud-rate generator up to 1/16 system clock
Supports RS-485 function
SPI (Serial Peripheral Interface)
One SPI device
Masters up to 12 MHz, and Slaves up to 4 MHz
Supports SPI Master/Slave mode
Full duplex synchronous serial data transfer
Variable length of transfer data from 1 to 32 bits
MSB or LSB first data transfer
Rx and Tx on both rising or falling edge of serial clock independently
Byte Suspend mode in 32-bit transmission
I2C
Supports Master/Slave mode
Bi-directional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of
serial data on the bus
Serial clock synchronization allowing devices with different bit rates to

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NUMICRO™ MINI51 TECHNICAL REFERENCE MANUAL
communicate via one serial bus
Serial clock synchronization used as a handshake mechanism to suspend and
resume serial transfer
Programmable clocks allowing for versatile rate control
Supports multiple address recognition (4 slave addresses with mask option)
ADC (Analog-to-Digital Converter)
10-bit SAR ADC with 150K SPS
Up to 8-ch single-end input and one internal input from band-gap
Conversion started by software or external pin
Analog Comparator
Two analog comparators with programmable 16-level internal voltage reference
Built-in CRV (comparator reference voltage)
BOD (Brown-Out Detection) Reset
Three programmable threshold levels: 3.8V/2.7V/2.0V (default as 2.0V)
Optional BOD interrupt or reset
96-bit unique ID
Operating Temperature: -40℃~85℃
Packages:
Green package (RoHS)
LQFP 48-pin (7x7), QFN 33-pin (5x5), QFN 33-pin (4x4)

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3 PARTS INFORMATION LIST AND PIN CONFIGURATION
3.1 NuMicro Mini51Series Product Selection Guide
Part Number
APROM
RAM
Data Flash
ISP
Loader
ROM
I/O
Timer
Connectivity
Comp.
PWM
ADC
ISP
ICP
IRC
22.1184
MHz
Package
UART
SPI
I2C
MINI51LAN
4 KB
2 KB
Configurable
2 KB
up to 30
2x32-bit
1
1
1
2
6
8x10-bit
v
v
LQFP48
MINI51ZAN
4 KB
2 KB
Configurable
2 KB
up to 29
2x32-bit
1
1
1
2
6
8x10-bit
v
v
QFN33(5x5)
MINI51TAN
4 KB
2 KB
Configurable
2 KB
up to 29
2x32-bit
1
1
1
2
6
8x10-bit
v
v
QFN33(4x4)
MINI52LAN
8 KB
2 KB
Configurable
2 KB
up to 30
2x32-bit
1
1
1
2
6
8x10-bit
v
v
LQFP48
MINI52ZAN
8 KB
2 KB
Configurable
2 KB
up to 29
2x32-bit
1
1
1
2
6
8x10-bit
v
v
QFN33(5x5)
MINI52TAN
8 KB
2 KB
Configurable
2 KB
up to 29
2x32-bit
1
1
1
2
6
8x10-bit
v
v
QFN33(4x4)
MINI54LAN
16 KB
2 KB
Configurable
2 KB
up to 30
2x32-bit
1
1
1
2
6
8x10-bit
v
v
LQFP48
MINI54ZAN
16 KB
2 KB
Configurable
2 KB
up to 29
2x32-bit
1
1
1
2
6
8x10-bit
v
v
QFN33(5x5)
MINI54TAN
16 KB
2 KB
Configurable
2 KB
up to 29
2x32-bit
1
1
1
2
6
8x10-bit
v
v
QFN33(4x4)
Figure 3.1-1 NuMicro Mini51Series Product Selection Guide

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3.2 PIN CONFIGURATION
3.2.1 LQFP 48-pin
2
44
1
4
3
6
5
8
7
10
9
11
48 42 41 40 39 38 37
32
33
30
31
28
29
26
27
25
13 14 15 16 18 19 20 21 22
12
17 23 24
34
35
36
46 47 43 45
Mini51
LQFP 48-pin
NC
CPP0, AIN5, P1.5
/RESET
AVSS
P5.4
CPP1, AIN7, P3.1
SDA, T0, P3.4
SCL, T1, P3.5
T0EX, STADC, INT0, P3.2
P5.1,XTAL2 P5.0,XTAL1 VSS
P5.2, INT1
LDO_CAP
P2.2, PWM0 P2.3, PWM1 P2.4, PWM2
P5.5
P3.6, CKO,T1EX,CPO0
P0.7, SPICLK
P4.6, ICE_CLK
P0.6, MISO
P0.5, MOSI
P0.4, SPISS,PWM5
P2.5, PWM3
P2.6, PWM4, CPO1
NC
P4.7, ICE_DAT
NC
TX ,AIN3,P1.3
RX ,AIN2, P1.2
CPN0,AIN4,P1.4
AIN1,P1.0
AIN0,P5.3
NC
AVDD
NC
TX, CTSn, P0.0
SPISS, RX, RTSn, P0.1
VDD
NC
CPN1, AIN6, P3.0
NC NC
NC
NC
NC
NC
Figure 3.2-1 NuMicro Mini51Series LQFP 48-pin Assignment

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NUMICRO™ MINI51 TECHNICAL REFERENCE MANUAL
3.2.2 QFN 33-pin
CPP0,AIN5, P1.5
P5.4
CPN1,AIN6, P3.0
CPP1,AIN7, P3.1
SDA, T0, P3.4
SCL, T1, P3.5
P5.1,XTAL2 P5.0,XTAL1 VSS P5.2,INT1 P2.2, PWM0 P2.3, PWM1 P2.4, PWM2 P3.6, CKO,T1EX,CPO0
P0.7, SPICLK
P4.6, ICE_CLK
P0.6, MISO
P0.5, MOSI
P0.4, SPISS,PWM5
P2.5, PWM3
P2.6, PWM4,CPO1
P4.7, ICE_DAT
TX, AIN3, P1.3
RX, AIN2, P1.2
CPN0,AIN4, P1.4
AIN1, P1.0
TX,CTSn, P0.0
VDD
SPISS,RX,RTSn, P0.1
AIN0,P5.3
33 VSS
32
1 24
Mini51
QFN 33-pin
31 30 29 28 27 26 25
23
22
21
20
19
18
17
109 11 12 13 14 15 16
2
3
4
5
6
7
8
top transparent view
T0EX,STADC,INT0, P3.2
/RESET
Figure 3.2-2 NuMicro Mini51Series QFN 33-pin Assignment

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NUMICRO™ MINI51 TECHNICAL REFERENCE MANUAL
3.3 Pin Description
Pin Number
Pin Name
Pin Type
Description
LQFP
48-pin
QFN
33-pin
1
NC
Not connected
2
1
P1.5
I/O
Digital GPIO pin
AIN5
AI
ADC analog input pin
CPP0
AI
Analog comparator Positive input pin
3
2
/RESET
I(ST)
The Schmitt trigger input pin for hardware device reset. A
“Low” on this pin for 768 clock counter of Internal RC
22.1184 MHz while the system clock is running will reset the
device. /RESET pin has an internal pull-up resistor allowing
power-on reset by simply connecting an external capacitor to
GND.
4
3
P3.0
I/O
Digital GPIO pin
AIN6
AI
ADC analog input pin
CPN1
AI
Analog comparator negative input pin
5
AVSS
AP
Ground pin for analog circuit
6
4
P5.4
I/O
Digital GPIO pin
7
5
P3.1
I/O
Digital GPIO pin
AIN7
AI
ADC analog input pin
CPP1
AI
Analog comparator positive input pin
8
6
P3.2
I/O
Digital GPIO pin
INT0
I
External interrupt 0 input pin
STADC
I
ADC external trigger input pin
T0EX
I
Timer 0 external capture/reset trigger input pin
9
7
P3.4
I/O
Digital GPIO pin
T0
I/O
Timer 0 external event counter input pin
SDA
I/O
I2C data I/O pin
10
8
P3.5
I/O
Digital GPIO pin
T1
I/O
Timer 1 external event counter input pin
SCL
I/O
I2C clock I/O pin
11
NC
Not connected
12
NC
Not connected
13
NC
Not connected

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NUMICRO™ MINI51 TECHNICAL REFERENCE MANUAL
Pin Number
Pin Name
Pin Type
Description
LQFP
48-pin
QFN
33-pin
14
9
P3.6
I/O
Digital GPIO pin
CPO0
O
Analog comparator output pin
CKO
O
Frequency divider output pin
T1EX
I
Timer 1 external capture/reset trigger input pin
15
10
P5.1
I/O
Digital GPIO pin
XTAL2
O
The output pin from the internal inverting amplifier. It emits
the inverted signal of XTAL1.
16
11
P5.0
I/O
Digital GPIO pin
XTAL1
I
The input pin to the internal inverting amplifier. The system
clock could be from external crystal or resonator.
17
12
VSS
P
Ground pin for digital circuit
33
18
LDO_CA
P
P
LDO output pin
19
P5.5
I/O
Digital GPIO pin
User program must enable pull-up resistor in the QFN-33
package.
20
13
P5.2
I/O
Digital GPIO pin
INT1
I
External interrupt 1 input pin
21
NC
Not connected
22
14
P2.2
I/O
Digital GPIO pin
PWM0
O
PWM0 output of PWM unit
23
15
P2.3
I/O
Digital GPIO pin
PWM1
O
PWM1 output of PWM unit
24
16
P2.4
I/O
Digital GPIO pin
PWM2
O
PWM2 output of PWM unit
25
17
P2.5
I/O
Digital GPIO pin
PWM3
O
PWM3 output of PWM unit
26
18
P2.6
I/O
Digital GPIO pin
PWM4
O
PWM4 output of PWM unit
CPO1
O
Analog comparator output pin
27
NC
Not connected

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NUMICRO™ MINI51 TECHNICAL REFERENCE MANUAL
Pin Number
Pin Name
Pin Type
Description
LQFP
48-pin
QFN
33-pin
28
NC
Not connected
29
19
P4.6
I/O
Digital GPIO pin
ICE_CLK
I
Serial wired debugger clock pin
30
20
P4.7
I/O
Digital GPIO pin
ICE_DAT
I/O
Serial wired debugger data pin
31
NC
Not connected
32
21
P0.7
I/O
Digital GPIO pin
SPICLK
I/O
SPI serial clock pin
33
22
P0.6
I/O
Digital GPIO pin
MISO
I/O
SPI MISO (master in/slave out) pin
34
23
P0.5
I/O
Digital GPIO pin
MOSI
O
SPI MOSI (master out/slave in) pin
35
24
P0.4
I/O
Digital GPIO pin
SPISS
I/O
SPI slave select pin
PWM5
O
PWM5 output of PWM unit
36
NC
Not connected
37
25
P0.1
I/O
Digital GPIO pin
RTSn
O
UART RTS pin
RX
I
UART data receiver input pin
SPISS
I/O
SPI slave select pin
38
26
P0.0
I/O
Digital GPIO pin
CTSn
I
UART CTS pin
TX
O
UART transmitter output pin
39
NC
Not connected
40
NC
Not connected
41
27
P5.3
I/O
Digital GPIO pin
AIN0
AI
ADC analog input pin
42
28
VDD
P
Power supply for digital circuit
43
AVDD
P
Power supply for analog circuit
44
29
P1.0
I/O
Digital GPIO pin

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NUMICRO™ MINI51 TECHNICAL REFERENCE MANUAL
Pin Number
Pin Name
Pin Type
Description
LQFP
48-pin
QFN
33-pin
AIN1
AI
ADC analog input pin
45
30
P1.2
I/O
Digital GPIO pin
AIN2
AI
ADC analog input pin
RX
I
UART data receiver input pin
46
31
P1.3
I/O
Digital GPIO pin
AIN3
AI
ADC analog input pin
TX
O
UART transmitter output pin
47
32
P1.4
I/O
Digital GPIO pin
AIN4
I/O
PWM5: PWM output/Capture input
CPN0
AI
Analog comparator negative input pin
48
NC
Not connected
Table 3.3-1 NuMicro Mini51Series Pin Description
[1] I/O type description: I: input, O: output, I/O: quasi bi-direction, D: open-drain, P: power pin,
ST: Schmitt trigger, A: Analog input.