Digi NS9750 Application guide

NS9750 Hardware Reference
90000624_G

Part number/version: 90000624_G
Release date: March 2008
www.digiembedded.com
NS9750 Hardware Reference

Digi International
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www.digiembedded.com
©2008 Digi International Inc.
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Contents
iii
Chapter 1: About NS9750 ...............................................................................................1
NS9750 Features ......................................................................... 2
System-level interfaces................................................................. 8
System boot .............................................................................10
Reset......................................................................................10
RESET_DONE as an input........................................................11
RESET_DONE as an output......................................................11
System clock.............................................................................13
USB clock.................................................................................15
Chapter 2: NS9750 Pinout ...........................................................................................17
Pinout and signal descriptions........................................................18
System Memory interface ......................................................18
System Memory interface signals..............................................22
Ethernet interface...............................................................25
Clock generation/system pins .................................................26
bist_en_n, pll_test_n, and scan_en_n........................................28
PCI interface......................................................................28
GPIO MUX .........................................................................34
LCD module signals..............................................................42
I2C interface......................................................................43
USB interface.....................................................................43
JTAG interface for ARM core/boundary scan................................43
Reserved ..........................................................................45
Power ground.....................................................................46

iv
Chapter 3: Working with the CPU ......................................................................47
About the processor....................................................................48
Instruction sets..........................................................................49
ARM instruction set..............................................................50
Thumb instruction set...........................................................50
Java instruction set .............................................................50
System control processor (CP15) registers..........................................51
ARM926EJ-S system addresses .................................................51
Accessing CP15 registers........................................................52
Terms and abbreviations .......................................................52
Register summary................................................................53
R0: ID code and cache type status registers.................................55
R1: Control register .............................................................58
R2: Translation Table Base register...........................................61
R3: Domain Access Control register...........................................61
R4 register ........................................................................62
R5: Fault Status registers.......................................................62
R6: Fault Address register......................................................64
R7: Cache Operations register.................................................64
R8:TLB Operations register.....................................................68
R9: Cache Lockdown register ..................................................69
R10: TLB Lockdown register....................................................73
R11 and R12 registers ...........................................................74
R13: Process ID register.........................................................75
R14 register.......................................................................77
R15: Test and debug register ..................................................77
Jazelle (Java) ...........................................................................77
DSP........................................................................................78
Memory Management Unit (MMU)....................................................78
MMU Features ....................................................................78
Address translation..............................................................81
MMU faults and CPU aborts.....................................................95
Domain access control ..........................................................98
Fault checking sequence .......................................................99
External aborts..................................................................102
Enabling the MMU...............................................................103
Disabling the MMU ..............................................................104

v
TLB structure....................................................................104
Caches and write buffer..............................................................105
Cache features..................................................................105
Write buffer .....................................................................106
Enabling the caches ............................................................107
Cache MVA and Set/Way formats ............................................109
Noncachable instruction fetches....................................................111
Self-modifying code ............................................................112
AHB behavior ....................................................................112
Instruction Memory Barrier...........................................................113
IMB operation....................................................................113
Sample IMB sequences .........................................................114
Chapter 4: System Control Module ................................................................. 115
System Control Module features ....................................................116
Bus interconnection...................................................................116
System bus arbiter.....................................................................116
Arbiter configuration examples ..............................................120
Address decoding ......................................................................123
Programmable timers.................................................................125
Software watchdog timer......................................................125
General purpose timers/counters............................................125
Interrupt controller ...................................................................129
Vectored interrupt controller (VIC) flow....................................132
System attributes......................................................................133
PLL configuration ...............................................................133
Bootstrap initialization ........................................................134
System configuration registers ......................................................138
AHB Arbiter Gen Configuration register.....................................144
BRC0, BRC1, BRC2, and BRC3 registers......................................145
Timer 0–15 Reload Count registers...........................................146
Timer 0–15 Read register ......................................................147
Interrupt Vector Address Register Level 0–31 ..............................147
Int (Interrupt) Config (Configuration) registers (0–31)....................148
ISRADDR register................................................................150
Interrupt Status Active.........................................................151

vi
Interrupt Status Raw ...........................................................152
Timer Interrupt Status register...............................................153
Software Watchdog Configuration register .................................153
Software Watchdog Timer register ..........................................155
Clock Configuration register ..................................................155
Reset and Sleep Control register.............................................157
Miscellaneous System Configuration and Status register .................158
PLL Configuration register.....................................................161
Active Interrupt Level Status register .......................................163
Timer 0–15 Control registers..................................................163
System Memory Chip Select 0 Dynamic Memory Base and Mask registers..
165
System Memory Chip Select 1 Dynamic Memory Base and Mask registers..
166
System Memory Chip Select 2 Dynamic Memory Base and Mask registers..
167
System Memory Chip Select 3 Dynamic Memory Base and Mask registers..
168
System Memory Chip Select 0 Static Memory Base and Mask registers.169
System Memory Chip Select 1 Static Memory Base and Mask registers.170
System Memory Chip Select 2 Static Memory Base and Mask registers.171
System Memory Chip Select 3 Static Memory Base and Mask registers.172
Gen ID register ..................................................................173
External Interrupt 0–3 Control register......................................175
Chapter 5: Memory Controller .............................................................................177
Features.................................................................................178
System overview................................................................179
Low-power operation ..........................................................180
Memory map.....................................................................180
Static memory controller.............................................................183
Write protection ................................................................184
Extended wait transfers .......................................................184
Memory mapped peripherals..................................................185
Static memory initialization ..................................................185
Byte lane control ...............................................................211
Address connectivity ...........................................................212
Byte lane control and databus steering .....................................216

vii
Dynamic memory controller .........................................................224
Write protection ................................................................224
Access sequencing and memory width ......................................224
Address mapping................................................................225
Registers ................................................................................264
Register map ....................................................................264
Reset values .....................................................................266
Control register .................................................................267
Status register...................................................................269
Configuration register..........................................................269
Dynamic Memory Control register............................................270
Dynamic Memory Refresh Timer register ...................................272
Dynamic Memory Read Configuration register .............................274
Dynamic Memory Precharge Command Period register...................275
Dynamic Memory Active to Precharge Command Period register .......276
Dynamic Memory Self-refresh Exit Time register..........................277
Dynamic Memory Last Data Out to Active Time register .................278
Dynamic Memory Data-in to Active Command Time register ............279
Dynamic Memory Write Recovery Time register ...........................280
Dynamic Memory Active to Active Command Period register............281
Dynamic Memory Auto Refresh Period register ............................282
Dynamic Memory Exit Self-refresh register.................................283
Dynamic Memory Active Bank A to Active Bank B Time register ........284
Dynamic Memory Load Mode register to Active Command Time register..
285
Static Memory Extended Wait register ......................................286
Dynamic Memory Configuration 0–3 registers ..............................287
Dynamic Memory RAS and CAS Delay 0–3 registers ........................291
Static Memory Configuration 0–3 registers..................................292
Static Memory Write Enable Delay 0–3 registers...........................296
Static Memory Output Enable Delay 0–3 registers .........................297
Static Memory Read Delay 0–3 registers.....................................298
Static Memory Page Mode Read Delay 0–3 registers.......................299
Static Memory Write Delay 0–3 registers....................................300
Static Memory Turn Round Delay 0–3 registers.............................301
Chapter 6: Ethernet Communication Module ......................................315

viii
Overview................................................................................316
Ethernet MAC...........................................................................317
Station address logic (SAL)....................................................321
Statistics module ...............................................................321
Ethernet front-end module ..........................................................323
Receive packet processor .....................................................324
Transmit packet processor ....................................................327
Ethernet Slave Interface.......................................................330
Interrupts ........................................................................331
Resets.............................................................................332
External CAM filtering ................................................................334
Ethernet Control and Status registers..............................................337
Ethernet General Control Register #1 .......................................339
Ethernet General Control Register #2 .......................................342
Ethernet General Status register.............................................344
Ethernet Transmit Status register............................................344
Ethernet Receive Status register.............................................347
MAC Configuration Register #1 ...............................................348
MAC Configuration Register #2 ...............................................351
Back-to-Back Inter-Packet-Gap register.....................................354
Non Back-to-Back Inter-Packet-Gap register...............................355
Collision Window/Retry register .............................................355
Maximum Frame register ......................................................357
PHY Support register...........................................................358
MII Management Configuration register .....................................359
MII Management Command register..........................................360
MII Management Address register ............................................361
MII Management Write Data register ........................................362
MII Management Read Data register .........................................363
MII Management Indicators register..........................................363
Station Address registers ......................................................364
Station Address Filter register................................................366
Register Hash Tables ...........................................................366
Statistics registers..............................................................368
RX_A Buffer Descriptor Pointer register.....................................383
RX_B Buffer Descriptor Pointer register.....................................383
RX_C Buffer Descriptor Pointer register.....................................384