ELAN Microelectronics Corporation EM78P911A User manual

2005/12/19
EM78P911A
8-BIT MICRO-CONTROLLER
ELAN MICROELECTRONICS CORP.
No. 12, Innovation 1
st
RD., Science-Based Industrial Park
Hsin Chu City, Taiwan
TEL: [phone]
FAX: [phone] (SA2)
Version 2.1

EM78P911A
8-bit Micro-controller
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to change without notice.
~ ~
112/19/2005 (V2.1)
Version history
Date Version number Description Note
2005/12/19 2.1 Add DTMF detail description in page 33

EM78P911A
8-bit Micro-controller
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to change without notice.
~ ~
212/19/2005 (V2.1)
I.General Description
The EM78P911A is an 8-bit CID (Call Identification) RISC type microprocessor with low power, high speed CMOS
technology. Integrated onto a single chip are on_chip watchdog (WDT), RAM, ROM, programmable real time clock /counter,
internal interrupt, power down mode, LCD driver, FSK decoder, CALL WAITING decoder, SDT decoder, DTMF generator,
MEI(Multiple Extension Internetworking) and RTF(Request To Flash) functions, and tri-state I/O . The EM78P911A
provides a single chip solution to design a CID of calling message_display.
II.Feature
CPU
‧Operating voltage range : 2.5V～5.5V
‧16K×13 on chip Electrical One Time Programmable Read Only Memory (OTP-ROM)
‧2.8K×8 on chip RAM
‧Up to 36 bi-directional tri-state I/O ports
‧8 level stack for subroutine nesting
‧8-bit real time clock/counter (TCC)
‧Two sets of 8 bit counters can be interrupt sources
‧Selective signal sources and trigger edges , and with overflow interrupt
‧Programmable free running on chip watchdog timer
‧99.9％single instruction cycle commands
‧Four modes (internal clock 3.579MHz)
1. Sleep mode : CPU and 3.579MHz clock turn off, 32.768KHz clock turn off
2. Idle mode : CPU and 3.579MHz clock turn off, 32.768KHz clock turn on
3. Green mode : 3.579MHz clock turn off, CPU and 32.768KHz clock turn on
4. Normal mode : 3.579MHz clock turn on , CPU and 32.768KHz clock turn on
‧Ring on voltage detector
‧ Universal Low battery detector
‧Input port wake up function
‧9 interrupt source , 4 external , 5 internal
‧100 pin QFP or chip
‧Port key scan function
‧Clock frequency 32.768KHz
‧Eight R-option pins
CID
‧Operation Volltage 3.5 ～6V for FSK
‧Operation Volltage 2.5 ～6V for DTMF
‧Bell 202 , V.23 FSK demodulator
‧DTMF generator
‧Ring detector on chip
CALL WAITING
‧Operation Volltage 3.6 ～5.5V
‧Compatible with Bellcore special report SR-TSV-002476
‧ Call-Waiting (2130Hz plus 2750Hz) Alert Signal Detector
‧Good talkdown and talkoff performance
‧ Sensitivity compensated by adjusting input OP gain
‧ Minimum access frequency deviation ± 0.5% for U.S. Call waiting spec. (EM78P911A)
SDT
‧ Stuttered Dial Tone (350Hz plus 440Hz) Signal Detect
MEI/RTF
‧Compatible with TIA/EIA-777(TIA SP-4078)
‧MEI(Multiplex Extension Internetworking) and RTF(Request To Flash) functions

EM78P911A
8-bit Micro-controller
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to change without notice.
~ ~
312/19/2005 (V2.1)
LCD
‧LCD operation voltage chosen by software
‧Common driver pins : 16
‧Segment driver pins : 60
‧1/4 bias
‧1/8,1/16 duty
PACKAGE
‧100 pin QFP (EM78P911AAQ, POVD disable) (EM78P911ABQ, POVD enable),
100 pin Chip or 102 pin Chip (with MEI and RTF functions)
III.Application
1. adjunct units
2. answering machines
3. feature phones
IV.Pin Configuration
EM78P911AAQ, EM78P911ABQ
Fig.1a Pin assignment
AVSS
DTMF
PLLC
RINGTIME
RDET1
RING
TIP
GAIN
CWTIP
XIN
XOUT
AVDD
COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39
VSS
TEST
COM8/P60 COM9/P61
COM10/P62 COM11/P63 COM12/P64 COM13/P65 COM14/P66 COM15/P67
SEG40/P54 SEG41/P55 SEG42/P56 SEG43/P57 SEG44/P80 SEG45/P81 SEG46/P82 SEG47/P83 SEG48/P84 SEG49/P85
SEG50/P86
SEG51/P87
SEG52/P90
SEG53/P91
SEG54/P92
SEG55/P93
SEG56/P94
SEG57/P95
SEG58/P96
SEG59/P97
P70/INT0
P71/INT1
P72/INT2
P73/INT3
P74
P75
P76
LBD/P77
/RESET
VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

EM78P911A
8-bit Micro-controller
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to change without notice.
~ ~
412/19/2005 (V2.1)
100 pin die(w/o RTF, MEI pin out)
102 pin die(with RTF,MEI pin out)
Fig.1b Pin assignment
OTP writer PIN NAME MASK ROM PIN NAME P.S.
1.VDD VDD,AVDD
2.VPP /RESET
3.DINCK P77
4.ACLK P76
5.PGMB P75
6.OEB P74
7.DATA P73
8.GND VSS,AVSS,TEST
AVSS
DTMF
PLLC
RINGTIME
RDET1
RING
TIP
GAIN
CWTIP
XIN
XOUT
AVDD
COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39
VSS
TEST
COM8/P60 COM9/P61
COM10/P62 COM11/P63 COM12/P64 COM13/P65 COM14/P66 COM15/P67
SEG40/P54 SEG41/P55 SEG42/P56 SEG43/P57 SEG44/P80 SEG45/P81 SEG46/P82 SEG47/P83 SEG48/P84 SEG49/P85
SEG50/P86
SEG51/P87
SEG52/P90
SEG53/P91
SEG54/P92
SEG55/P93
SEG56/P94
SEG57/P95
SEG58/P96
SEG59/P97
P70/INT0
P71/INT1
P72/INT2
P73/INT3
P74
P75
P76
LBD/P77
/RESET
VDD
1 2 3 6 7 8 9
10
11
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
102
RTF
MEI 4
5
101
100

EM78P911A
8-bit Micro-controller
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to change without notice.
~ ~
512/19/2005 (V2.1)
V.Functional Block Diagram
Fig.2 Block diagram1
Fig.3 Block diagram2
CP
U
CPU
TIMING
CONTROL
TIMING
CONTROL
TIME
R
TIMER
RO
M
ROM
RA
M
RAM
LCD
DRIVER
LCD
DRIVER LCD
IO
PORT
IO
PORT I/O
FSK
DTMF
CALL WAITING
SDT
MEI&RTF
Xin Xout
Oscillator
timing control
Control sleep
and wake-up
on I/O port
R1(TCC)
WDT timer
prescalar
GENERAL
RAM
R4
Interruption
control
ROM
Instruction
register
Instruction
decoder
R2 STACK
ALU
ACC
R3
R5
DATA & CONTROL BUS
2.5 k RAM
PORT6
IOC6 R6
P60~P67
PORT7
IOC7 R7
P70~P77
PORT8
IOC8 R8
P80~P87
PORT9
IOC9 R9
P90~P97
PORT5
IOC5 R5
P54~P57
FSK
DTMF
CALL WAITING
SDT
MEI&RTF

EM78P911A
8-bit Micro-controller
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to change without notice.
~ ~
612/19/2005 (V2.1)
VI.Pin Descriptions
PIN I/O DESCRIPTION
VDD
AVDD POWER digital power analog power
GND
AVSS POWER digital ground analog ground
Xtin I Input pin for 32.768 kHz oscillator
Xtout O Output pin for 32.768 kHz oscillator
COM0..COM7
COM8..COM15 O O (PORT6) Common driver pins of LCD drivers
SEG0...SEG43
SEG44..SEG51
SEG52..SEG59
O
O (PORT8)
O (PORT9)
Segment driver pins of LCD drivers
PORT9 AS FUNCTION KEY CAN WAKE UP WATCHDOG.
PLLC I Phase loop lock capacitor, connect a capacitor 0.01u to 0.047u with
AVSS
RTF I Return to flash input. Detect line DC voltage changed
MEI I Multiple extension internetworking input. 1.2 DC voltage detection can
be used as on-hook/off-hook detection.
TIP I Should be connected with TIP side of twisted pair lines for FSK.
RING I Should be connected with RING side of twisted pair lines for FSK.
CWTIP I Should be connected with TIP side of twisted pair lines for CW.
GAIN I OP output pin for gain adjustment.
RDET1 I Detect the energy on the twisted pair lines . These two pins coupled to
the twisted pair lines through an attenuating network.
/RING TIME I Determine if the incoming ring is valid.An RC network may be
connected to the pin.
INT0
INT1
INT2
INT3
PORT7(0)
PORT7(1)
PORT7(2)
PORT7(3)
PORT7(4:7)
PORT7(0)~PORT7(3) signal can be interrupt signals.
Int2 and int3 has the same interrupt flag.
IO port
P5.4 ~P5.7 PORT5 PORT 5 can be INPUT or OUTPUT port each bit.
Shared with LCD segment signals
P6.0 ~P6.7 PORT6 PORT 6 can be INPUT or OUTPUT port each bit.
Shared with LCD common signals
P7.0 ~P7.7 PORT7 PORT 7 can be INPUT or OUTPUT port each bit.
Internal Pull high function.
Key scan function.
P8.0 ~P8.7 PORT8 PORT 8 can be INPUT or OUTPUT port each bit.
And shared with Segment signal.
P9.0 ~P9.7 PORT9 PORT 9 can be INPUT or OUTPUT port each bit.
And can be set to wake up watch dog timer.
And shared with Segment signal.
TEST I Test pin into test mode , normal low
DTMF O DTMF tone output
RESET I

EM78P911A
8-bit Micro-controller
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to change without notice.
~ ~
712/19/2005 (V2.1)
VII.Functional Descriptions
VII.1 Operational Registers
1. R0 (Indirect Addressing Register)
* R0 is not a physically implemented register. It is useful as indirect addressing pointer. Any instruction using R0 as
register actually accesses data pointed by the RAM Select Register (R4).
2. R1 (TCC)
* Increased by an external signal edge applied to TCC , or by the instruction cycle clock.
Written and read by the program as any other register.
3. R2 (Program Counter)
* The structure is depicted in Fig. 4.
* Generates 16K ×13 on-chip ROM addresses to the relative programming instruction codes.
* "JMP" instruction allows the direct loading of the low 10 program counter bits.
* "CALL" instruction loads the low 10 bits of the PC, PC+1, and then push into the stack.
* "RET'' ("RETL k", "RETI") instruction loads the program counter with the contents at the top of stack.
* "MOV R2,A" allows the loading of an address from the A register to the PC, and the ninth and tenth bits are
cleared to "0''.
* "ADD R2,A" allows a relative address be added to the current PC, and contents of the ninth and tenth bits are
cleared to "0''.
* "TBL" allows a relative address be added to the current PC, and contents of the ninth and tenth bits don't change. The
most significant bit (A10~A13) will be loaded with the content of bit PS0~PS3 in the status register (R5) upon the
execution of a "JMP'', "CALL'', "ADD R2,A'', or "MOV R2,A'' instruction.
Fig.4 Program counter organization
PC A13 A12 A11 A10 A9 A8 A7~A0
0000 PAGE0 0000~03FF
0001 PAGE1 0400~07FF
1110 PAGE14 3800~3BFF
1111 PAGE15 3C00~3FFF
0010 PAGE3 0800~0BFF
STACK1
STACK2
STACK3
STACK4
STACK5
STACK6
STACK7
STACK8
CALL
RET
RETL
RETI

EM78P911A
8-bit Micro-controller
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to change without notice.
~ ~
812/19/2005 (V2.1)
Fig.5 Data memory configuration
4. R3 (Status Register)
7 6 5 4 3 2 1 0
CAS PAGE /SDT T P Z DC C
* Bit 0 (C) Carry flag
* Bit 1 (DC) Auxiliary carry flag
* Bit 2 (Z) Zero flag
* Bit 3 (P) Power down bit. Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP"
command.
* Bit 4 (T) Time-out bit. Set to 1 by the "SLEP" and "WDTC" command, or during power up and reset to 0 by WDT
timeout.
EVENT T P REMARK
WDT wake up from
sleep mode
00
WDT time out (not sleep mode) 0 1
/RESET wake up from sleep 1 0
power up 1 1
Low pulse on /RESET x x x .. don't care
* Bit 5 (/SDT) : (Read Only)(Stuttered dial tone signal detect output), 0/1 => SDT signal valid/SDT signal invalid
* Bit 6 (PAGE) : change IOCB ~ IOCE to another page , 0/1 => page0 / page1
* Bit 7 (CAS) : CALL WAITING Output), 0/1= CW data valid/No data
5.R4 (RAM Select Register)
* Bits 0 ~ 5 are used to select up to 64 registers in the indirect addressing mode.
* Bits 6 ~ 7 determine which bank is activated among the 4 banks.
* See the configuration of the data memory in Fig. 5.
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
R0
R1(TCC)
R2(PC)
R3(STATUS)
R4(RSR)
R5(ROM PAGE & R5)
R6(PORT6)
R7(PORT7)
R8(PORT8)
R9(PORT9)
RA(CLK,FSK)
RB(DTMF)
RC(2.5K RAM ADDRESS)
RD(2.5K RAM DATA)
RE(WDT)
RF(INT FLAG)
10
:
1F
16X8
COMMON
REGISTER
20
:
3F
BANK0 ~BANK3
32X8 ~32X8
REGISTER
IOC6
IOC7
IOC8
IOC9
IOCA
IOCB(LCD ADDRESS)
IOCC(LCD DATA)
IOCD(PULL HIGH)
IOCE(IO, LCD)
IOCF(INT CONTROL)
IOCB(COUNTER1)
IOCC(COUNTER2)
IOCD(R-OPTION)
page0
page1
BANK1 BANK2 …………..BANK10
256X8 256X8 …………….256X8
RC(ADDRESS) RD(DATA)
0
:
255
ADDRESS REGISTER CONTROL REGISTER
(PAGE0) CONTROL REGISTER (PAGE1)

EM78P911A
8-bit Micro-controller
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to change without notice.
~ ~
912/19/2005 (V2.1)
6. R5 (Program Page Select Register)
7 6 5 4 3 2 1 0
R57 R56 R55 R54 PS3 PS2 PS1 PS0
* Bit 0 (PS0) ~ 3 (PS3) Page select bits
Page select bits
PS3 PS2 PS1 PS0 Program memory page (Address)
0 0 0 0 Page 0
0 0 0 1 Page 1
0 0 1 0 Page 2
0 0 1 1 Page 3
0 1 0 0 Page 4
0 1 0 1 Page 5
0 1 1 0 Page 6
0 1 1 1 Page 7
1 0 0 0 Page 8
1 0 0 1 Page 9
1 0 1 0 Page 10
1 0 1 1 Page 11
1 1 0 0 Page 12
1 1 0 1 Page 13
1 1 1 0 Page 14
1 1 1 1 Page 15
*User can use PAGE instruction to change page. To maintain program page by user. Otherwise, user can use far
jump (FJMP) or far call (FCALL) instructions to program user's code. And the program page is maintained by
EMC's complier. It will change user's program by inserting instructions within program.
*Bit4~7 : PORT5 4-bit I/O register
6. R6 ~ R9 (Port 6 ~ Port 9)
* Four 8-bit I/O registers.
7. RA (FSK Status Register)(bit 0,1,2,4 read only)
7 6 5 4 3 2 1 0
IDLE /358E /LPD /LOW_BAT /FSKPWR DATA /CD /RD
* Bit0 (Read Only) (Ring detect signal)0/1 : Ring Valid/Ring Invalid
* Bit1(Read Only)(Carrier detect signal) 0/1 : Carrier Valid/Carrier Invalid
* Bit2(Read Only)(FSK demodulator output signal)
Fsk data transmitted in a baud rate 1200 Hz.
* Bit3(read/write)(FSK block power up signal)
1/0 : FSK demodulator block power up/FSK demodulator power down
When FSK is powered on, PLL is also enabled regardless of RA bit6(/358E). When FSK is powered off,
PLL status is depended on RA bit6(/358E) setting.
* The relation between Bit0 to Bit3 is shown in Fig.6.

EM78P911A
8-bit Micro-controller
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to change without notice.
~ ~
10 12/19/2005 (V2.1)
sleep mode
wake up
mode
/RINGTIME ='0'
FSK decoder
begin its work
/FSKPWR='1'
DATA transfer
to Micro
/RD and /CD ='1' and
nothing to do for 30
sec , /FSKPWR='0'
or external keys
pressed
/RD and /CD ='1'
SLEEP MODE
Begin
set /FSKPWR='0'
/RINGTIME ='0'
or external keys
pressed
WAKE UP MODE
8-bit wake up and
set /FSKPWR='1'
accept data from
FSK decoder
/RD and /CD ='1'
data end and 30
sec nothing to do.
Yes No
No
Yes
STATE Diagram between 8-bit
and FSK decoder
Flow Diagram between 8-bit
and FSK decoder
Fig.6 The relation between Bit0 to Bit3.
* Bit4(Read Only)(Low battery signal) 0/1 = Battery voltage is low/Normal .
Low battery detect level is set by external resisters R1 and R2. The detect level VbL = 0.87V*(1+ R1/R2). If
Vbattery is under VbL, then send a ‘0’ signal to /LOW_BAT bit; othwise a ‘1’ signal to this bit. Select pin P77/LBD
as LBD by setting IOCE PAGE0 bit1 to ‘0’. LBD pin is used as low battery detect input.
* Bit5(read/Write)(Low battery detect enable)
0/1 = low battery detect DISABLE/ENABLE.
The relation between /LPD,/POVD and /LOW_BAT can see Fig7.
Fig.7 Universal low battery detect with /LPD,/POVD and /LOW_BAT
* Bit6(read/write)(PLL enable signal)
0/1=DISABLE/ENABLE
The relation between 32.768kHz and 3.579MHz can see Fig.8.
Fig.8 The relation between 32.768kHz and 3.579MHz .
Sub-clock
32.768KHz
PLL
3.579M Hz
RA bit6 sw itch To system clock
1
0
VDD
Vref
s2
1 on
0 off 1 on
To reset
+
-
1 on
SW
LBD/P77 P77
+
-
0.87V
/POVD
/LPD
LBD/P77
/LOW_BAT
0 enable
0 on
Vbattery
R1
R2
2.2V

EM78P911A
8-bit Micro-controller
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to change without notice.
~ ~
11 12/19/2005 (V2.1)
* Bit7 IDLE: sleep mode selection bit
0/1=sleep mode/IDLE mode. This bit will decide SLEP instruction which mode to go.
These two modes can be waken up by TCC clock or Watch Dog or PORT9 and run from “SLEP” next instruction.
Wakeup signal SLEEP mode IDLE mode GREEN mode NORMAL mode
RA(7,6)=(0,0)
+ SLEP RA(7,6)=(1,0) + SLEP RA(7,6)=(x,0) no SLEP RA(7,6)=(x,1) no SLEP
TCC time out X Wake-up
+ Interrupt
+ Next instruction
Interrupt
Interrupt
WDT time out RESET Wake-up
+ Next instruction RESET RESET
Port9
/RINGTIME pin RESET Wake-up + Next instruction X X
PORT70~73 X Wake-up
+ Interrupt
+ Next instruction
Interrupt
Interrupt
*P70 ~ P73 's wakeup function is controlled by IOCF(1,2,3) and ENI instruction.
*P70 's wakeup signal is a rising or falling signal defined by CONT REGISTER bit7.
*/RINGTIME pin , Port9 ,Port71,Port72 and Port73 's wakeup signal is a falling edge signal.
8. RB(DTMF tone row and column register) (read/write)
7 6 5 4 3 2 1 0
c7 c6 c5 c4 r3 r2 r1 r0
* Bit 0 - Bit 3 are row-frequency tone.
* Bit 4 - Bit 7 are column-frequency tone.
* Initial RB is equal to high. Bit 7 ~ 0 are all "1" , turn off DTMF power .
bit 3~0 Row freq
1110 699.2Hz 1 2 3 A
1101 771.6Hz 4 5 6 B
1011 854Hz 7 8 9 C
0111 940.1Hz * 0 # D
Column freq 1203Hz 1331.8Hz 1472Hz 1645.2Hz
bit 7~4 1110 1101 1011 0111
9. RC(CALLER ID address)(read/write)
7 6 5 4 3 2 1 0
CIDA7 CIDA6 CIDA5 CIDA4 CIDA3 CIDA2 CIDA1 CIDA0
* Bit 0 ~ Bit 7 select CALLER ID RAM address up to 256.
10. RD(CALLER ID RAM data)(read/write)
* Bit 0 ~ Bit 8 are CALLER ID RAM data transfer register.
User can see IOCA register how to select CID RAM banks.
11. RE(LCD Driver,WDT Control)(read/write)
7 6 5 4 3 2 1 0
CWPWR /WDTE /WUP9H /WUP9L /WURING LCD_C2 LCD_C1 LCD_M
* Bit0 (LCD_M):LCD_M decides the methods, including duty, bias, and frame frequency.
* Bit1~Bit2 (LCD_C#):LCD_C# decides the LCD display enable or blanking. change the display duty must set the
"LCD_C2,LCD_C1" to "00".

EM78P911A
8-bit Micro-controller
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to change without notice.
~ ~
12 12/19/2005 (V2.1)
LCD_C2,LCD_C1 LCD Display Control LCD_M duty bias
0 0 change duty
Disable(turn off LCD) 0 1 1/16 1/4 1/8 1/4
0 1 Blanking : :
1 1 LCD display enable : :
* Bit3 (/WURING, RING Wake Up Enable): used to enable the wake-up function of /RINGTIME input pin.
(1/0=enable/disable)
* Bit4 (/WUP9L, PORT9 low nibble Wake Up Enable): used to enable the wake-up function of low nibble in
PORT9.(1/0=enable/disable)
* Bit5 (/WUP9H, PORT9 high nibble Wake Up Enable): used to enable the wake-up function of high nibble in
PORT9.(1/0=enable/disable)
* Bit6 (/WDTE,Watch Dog Timer Enable)
Control bit used to enable Watchdog timer.(1/0=enable/disable)
The relation between Bit3 to Bit6 can see the diagram 9.
* Bit7(Power control of Call Waiting circuit)
(1/0=enable circuit /disable circuit)
When Call waiting circuit is powered on, PLL is also enabled regardless of RA bit6(/358E). When Call
waiting circuit is powered off, PLL status is depended on RA bit6(/358E) setting.
/WURING
/RINGTIME
/WUP9L
PORT9(3:0)
/WUP9H
PORT9(7:4)
/WDTE
/WDTEN 0/1=enable/disable
Fig.9 Wake up function and control signal
12. RF (Interrupt Status Register)
7 6 5 4 3 2 1 0
INT3 FSK/CW C8_2 C8_1 INT2 INT1 INT0 TCIF
* "1" means interrupt request, "0" means non-interrupt
* Bit 0 (TCIF) TCC timer overflow interrupt flag. Set when TCC timer overflows .
* Bit 1 (INT0) external INT0 pin interrupt flag .
* Bit 2 (INT1) external INT1 pin interrupt flag .
* Bit 3 (INT2) external INT2pin interrupt flag .
* Bit 4 (C8_1) internal 8 bit counter interrupt flag .
* Bit 5 (C8_2) internal 8 bit counter interrupt flag .
* Bit 6 ( FSK/CW ) FSK data or Call waiting data interrupt flag
* Bit 7 (INT3) external INT3 pin interrupt flag.
* High to low edge trigger , Refer to the Interrupt subsection.
* IOCF is the interrupt mask register. User can read and clear.
13. R10~R3F (General Purpose Register)
* R10~R3F (Banks 0~3) all are general purpose registers.
VII.2 Special Purpose Registers
1. A (Accumulator)
* Internal data transfer, or instruction operand holding
* It's not an addressable register.

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2. CONT (Control Register)
7 6 5 4 3 2 1 0
INT_EDGE INT TS TE PAB PSR2 PSR1 PSR0
* Bit 0 (PSR0) ~ Bit 2 (PSR2) TCC/WDT prescaler bits.
PSR2 PSR1 PSR0 TCC Rate WDT Rate
0 0 0 1:2 1:1
0 0 1 1:4 1:2
0 1 0 1:8 1:4
0 1 1 1:16 1:8
1 0 0 1:32 1:16
1 0 1 1:64 1:32
1 1 0 1:128 1:64
1 1 1 1:256 1:128
* Bit 3 (PAB) Prescaler assignment bit.
0/1 : TCC/WDT
* Bit 4 (TE) TCC signal edge
0: increment from low to high transition on TCC
1: increment from high to low transition on TCC
* Bit 5 (TS) TCC signal source
0: internal instruction cycle clock
1: 16.384KHz
* Bit 6 : (INT)INT enable flag
0: interrupt masked by DISI or hardware interrupt
1: interrupt enabled by ENI/RETI instructions
* Bit 7 : INT_EDGE
0:P70 's interruption source is a rising edge signal.
1:P70 's interruption source is a falling edge signal.
* CONT register is readable and writable.
3. IOC5 (I/O Port Control Register)
7 6 5 4 3 2 1 0
IOC57 IOC56 IOC55 IOC54 MEIO RTFO RTFPWR P5S
* Bit0: P5S is switch register for I/O port or LCD signal switching.
0/1= normal I/O port/SEGMENT output .
* Bit1(RTFPWR) : power control of RTF circuit, 1/0 => power on/power off
* Bit2(RTFO) : (Read Only) RTF line DC voltage change detect output.
When line DC voltage is not changed, RTFO is low.
* Bit3(MEIO) : MEI line high or line in-use detect output
When input voltage of MEI pin is below 1.2V, MEIO is low; when input voltage of MEI pin is over 1.3V,
MEIO is high.
* Bit 4 to Bit7 are PORT5 I/O direction control registers.
* "1" put the relative I/O pin into high impedance, while "0" put the relative I/O pin as output.
4. IOC6 ~ IOC9 (I/O Port Control Register)
* four I/O direction control registers.
* "1" put the relative I/O pin into high impedance, while "0" put the relative I/O pin as output.
* User can see IOCB register how to switch to normal I/O port.

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8-bit Micro-controller
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5. IOCA (CALLER ID RAM,IO ,PAGE Control Register)(read/write,initial "00000000")
7 6 5 4 3 2 1 0
P8SH P8SL SDTPW/0 CALL_4 CALL_3 CALL_2 CALL_1 MEIPWR
* Bit 0(MEIPWR) : power control of MEI circuit, 1/0 => power on/power off
* Bit4~Bit1:"000" to "1001" are ten blocks of CALLER ID RAM area. User can use 2.5K RAM with RD ram
address.
* Bit 5 (SDTPW/0) : (Power control of Stuttered dial tone circuit/disable SDT)
ps. When code option bit2(/SDTEN) is “1”, SDT is disabled and IOCA bit5 is always “0”.
User cannot use SDT function. When code option bit2(/SDTEN) is “0”, SDT is enabled
and IOCA bit5 is SDTPW. At this time, setting SDTPW 1/0 = power on circuit /power
down circuit.
* Bit6: port8 low nibble switch, 0/1= normal I/O port/SEGMENT output .
* Bit7: port8 high nibble switch , 0/1= normal I/O port/SEGMENT output
6. IOCB (LCD ADDRESS)
PAGE0 : Bit6 ~ Bit0 = LCDA6 ~ LCDA0
The LCD display data is stored in the data RAM . The relation of data area and COM/SEG pin is as below:
COM15 ~ COM8 COM7 ~ COM0
40H (Bit15 ~ Bit8) 00H (Bit7 ~ Bit0) SEG0
41H 01H SEG1
: : :
: : :
: : :
: : :
7AH 4AH SEG58
7BH 3BH SEG59
7CH 3CH Empty
: : :
7FH 3FH Empty
PAGE1 : 8 bit up-counter (COUNTER1) preset and read out register . ( write = preset ) . After a interruption , it
will count from “00”.
7. IOCC (LCD DATA)
PAGE0 : Bit7 ~ Bit0 = LCD RAM data register
PAGE1 : 8 bit up-counter (COUNTER2) preset and read out register . ( write = preset) After a interruption , it will
count from “00”.
8. IOCD (Pull-high Control Register)
PAGE0:
7 6 5 4 3 2 1 0
PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0
* Bit 0 ~ 7 (/PH#) Control bit used to enable the pull-high of PORT7(#) pin.
1: Enable internal pull-high
0: Disable internal pull-high
PAGE1:
7 6 5 4 3 2 1 0
RO7 RO6 RO5 RO4 RO3 RO2 RO1 RO0

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8-bit Micro-controller
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* This specification is subject to change without notice.
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* Bit 7 ~ 0 (RO7~0) Control bit used to enable the R-OPTION of PORT97~PORT90 pin.
1: Enable
0: Disable
RO is used for R-OPTION . Setting RO to ‘1’ will enable the status of R-option pin (P90 ~ P97) to read by controller.
Clearing RO will disable R-option function. If the R-option function is used, user must connect PORT9 pins to GND
by 560K external register . If the register is connected/disconnected , the R9 will read as “ 0/1” when RO is set to ‘1’.
9. IOCE (Bias,PLL Control Register)
PAGE0:
7 6 5 4 3 2 1 0
P9SH P9SL P6S Bias3 Bias2 Bias1 LBD/P77 SC
* Bit 0 :SC (SCAN KEY signal ) 0/1 = disable/enable. Once you enable this bit , all of the LCD signal will have a
low pulse during a common period. This pulse has 30us width. Please use the procedure to implement the key
scan function.
a. set port7 as input port
b. set IOCD page0 port7 pull high
c. enable scan key signal
d. Once push a key . Set RA(6)=1 and switch to normal mode.
e. Blank LCD. Disable scan key signal.
f.Set P6S =0. Port6 sent probe signal to port7 and read port7. Get the key.
g. Note!! A probe signal should be delay a instruction at least to another probe signal.
h. Set P6S =1. Port6 as LCD signal. Enable LCD.
Fig.10 Key scan circuit
P70P71P72P73
P60
P61
P62
P63 KEY1
KEY2
KEY5
KEY3
KEY4

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8-bit Micro-controller
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Fig.11 key scan signal
*Bit 1 (LBD/P77) : (Port7’s P77 switch), 0/1 => low battery detect input/ normal IO port P77
ps. Default value is ‘1’.
* Bit 2~4 (Bias1~Bias3) Control bits used to choose LCD operation voltage .
LCD operate voltage Vop (VDD 5V) VDD=5V
000
001
010
011
100
101
110
111
0.60VDD
0.66VDD
0.74VDD
0.82VDD
0.87VDD
0.93VDD
0.96VDD
1.00VDD
3.0V
3.3V
3.7V
4.0V
4.4V
4.7V
4.8V
5.0V
* Bit5:port6 switch , 0/1= normal I/O port/COMMON output
* Bit6:port9 low nibble switch , 0/1= normal I/O port/SEGMENT output . Bit7:port9 high nibble switch
PAGE1:
7 6 5 4 3 2 1 0
OP77 OP76 C2S C1S PSC1 PSC0 CDRD 0
* Bit0: unused
* Bit1: cooked data or raw data select bit , 0/1 ==> cooked data/raw data
* Bit3~Bit2: counter1 prescaler , reset=(0,0)
(PSC1,PSC0) = (0,0)=>1:1 , (0,1)=>1:4 , (1,0)=>1:8 , (1,1)=>reserved
* Bit4:counter1 source , (0/1)=(32768Hz/3.579MHz if enable) scale=1:1
* Bit5:counter2 source , (0/1)=(32768Hz/3.579MHz if enable) scale=1:1
* Bit6:P76 opendrain control (0/1)=(disable/enable)
* Bit7:P77 opendrain control (0/1)=(disable/enable)
com2
seg
vdd
v1
v2
v3
vlcd
Gnd
vdd
v1
v2
v3
vlcd
Gnd
30us

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8-bit Micro-controller
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* This specification is subject to change without notice.
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10.IOCF (Interrupt Mask Register)
7 6 5 4 3 2 1 0
INT3 FSK/CW C8_2 C8_1 INT2 INT1 INT0 TCIF
* Bit 0 ~ 7 interrupt enable bit.
0: disable interrupt
1: enable interrupt
* IOCF Register is readable and writable.
VII.3 TCC/WDT Prescaler
There is an 8-bit counter available as prescaler for the TCC or WDT. The prescaler is available for the TCC only or WDT
only at the same time.
•An 8 bit counter is available for TCC or WDT determined by the status of the bit 3 (PAB) of the CONT register.
•See the prescaler ratio in CONT register.
•Fig. 10 depicts the circuit diagram of TCC/WDT.
•Both TCC and prescaler will be cleared by instructions which write to TCC each time.
•The prescaler will be cleared by the WDTC and SLEP instructions, when assigned to WDT mode.
•The prescaler will not be cleared by SLEP instructions, when assigned to TCC mode.
Fig.10 Block diagram of TCC WDT
VII.4 I/O Ports
The I/O registers, Port 6 ~ Port 9, are bi-directional tri-state I/O ports. Port 7 can be pulled-high internally by
software control. The I/O ports can be defined as "input" or "output" pins by the I/O control registers (IOC6 ~ IOC9 ) under
program control. The I/O registers and I/O control registers are both readable and writable. The I/O interface circuit is shown
in Fig.11.
16.38KHz

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8-bit Micro-controller
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* This specification is subject to change without notice.
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Fig.11 The circuit of I/O port and I/O control register
VII . 5 RESET and Wake-up
The RESET can be caused by
(1) Power on reset, or Voltage detector
(2) WDT timeout. (if enabled and in GREEN or NORMAL mode)
Note that only Power on reset, or only Voltage detector in Case(1) is enabled in the system by CODE Option bit. If Voltage
detector is disabled, Power on reset is selected in Case (1). Refer to Fig. 12.
Fig.12 Block diagram of Reset of controller
Once the RESET occurs, the following functions are performed.
•The oscillator is running, or will be started.
•The Program Counter (R2) is set to all "0".
•When power on, the upper 3 bits of R3 and the upper 2 bits of R4 are cleared.
•The Watchdog timer and prescaler are cleared.
•The Watchdog timer is disabled.
•The CONT register is set to all "1"
•The other register (bit7..bit0)

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8-bit Micro-controller
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R5 = “xxxx0000” IOC5 = "1111xx00"
R6 = PORT IOC6 = "11111111"
R7 = PORT IOC7 = "11111111"
R8 = PORT IOC8 = "11111111"
R9 = PORT IOC9 = "11111111"
RA = "000x0xxx IOCA = "00000000"
RB = "11111111" Page0 IOCB = "00000000" Page1 IOCB = "00000000"
RC = "00000000" Page0 IOCC = "0xxxxxxx" Page1 IOCC = "00000000"
RD = "xxxxxxxx" Page0 IOCD = "00000000" Page1 IOCD = “00000000”
RE = "00000000" Page0 IOCE = "00000010" Page1 IOCE = "00000000"
RF = "00000000" IOCF = "00000000"
The controller can be awakened from SLEEP mode or IDLE mode (execution of "SLEP" instruction, named as
SLEEP MODE or IDLE mode) by (1)TCC time out (2) WDT time-out (if enabled) or, (3) external input at PORT9. The
three cases will cause the controller wake up and run from next instruction. After wake-up , user should control WATCH
DOG in case of reset in GREEN mode or NORMAL mode. The last two should be open RE register before into sleep
mode or IDLE mode . The first one case will set a flag in RF bit0 .But it will not go to address 0x08.
VII.6 Interrupt
The CALLER ID IC has internal interrupts which are falling edge triggered, as followed : TCC timer overflow
interrupt (internal) , two 8-bit counters overflow interrupt .
If these interrupt sources change signal from high to low , then RF register will generate '1' flag to corresponding
register if you enable IOCF register.
RF is the interrupt status register which records the interrupt request in flag bit. IOCF is the interrupt mask register.
Global interrupt is enabled by ENI instruction and is disabled by DISI instruction. When one of the interrupts (when enabled)
generated, will cause the next instruction to be fetched from address 008H. Once in the interrupt service routine the source
of the interrupt can be determined by polling the flag bits in the RF register. The interrupt flag bit must be cleared in
software before leaving the interrupt service routine and enabling interrupts to avoid recursive interrupts.
There are four external interrupt pins including INT0 , INT1 , INT2 , INT3 . And four internal interrupt available.
Internal signals include TCC,CNT1,CNT2,FSK and CALL WAITING data. The last two will generate a interrupt
when the data trasient from high to low.
External interrupt INT0 , INT1 , INT2 , INT3 signals are from PORT7 bit0 to bit3 . If IOCF is enable then these
signal will cause interrupt , or these signals will be treated as general input data .
After reset, the next instruction will be fetched from address 000H and the instruction inturrept is 001H and the
hardware inturrept is 008H.
TCC will go to address 0x08 in GREEN mode or NORMAL mode after time out. And it will run next instruction
from “SLEP” instruction. These two cases will set a RF flag.
It is very important to save ACC,R3 and R5 when processing a interruption.
Address Instruction Note
0x08 DISI ;Disable interrupt
0x09 MOV A_BUFFER,A ;Save ACC
0x0A SWAP A_BUFFER
0x0B SWAPA 0x03 ;Save R3 status
0x0C MOV R3_BUFFER,A
0x0D MOV A,0x05 ;Save ROM page register
0x0E MOV R5_BUFFER,A
: :
: :
: MOV A,R5_BUFFER ;Return R5
: MOV 0X05,A
: SWAPA R3_BUFFER ;Return R3