Freescale Semiconductor MK22FN256VDC12 User manual

K22F Sub-Family Reference Manual
Supports: MK22FN256VDC12, MK22FN256VLL12,
MK22FN256VMP12, MK22FN256VLH12
Document Number: K22P121M120SF8RM
Rev. 3, 7/2014

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Contents
Section number Title Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................47
1.1.1 Purpose.........................................................................................................................................................47
1.1.2 Audience......................................................................................................................................................47
1.2 Conventions..................................................................................................................................................................47
1.2.1 Numbering systems......................................................................................................................................47
1.2.2 Typographic notation...................................................................................................................................48
1.2.3 Special terms................................................................................................................................................48
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................49
2.2 Module Functional Categories......................................................................................................................................49
2.2.1 ARM® Cortex®-M4 Core Modules............................................................................................................50
2.2.2 System Modules...........................................................................................................................................51
2.2.3 Memories and Memory Interfaces...............................................................................................................52
2.2.4 Clocks...........................................................................................................................................................52
2.2.5 Security and Integrity modules....................................................................................................................52
2.2.6 Analog modules...........................................................................................................................................53
2.2.7 Timer modules.............................................................................................................................................53
2.2.8 Communication interfaces...........................................................................................................................54
2.2.9 Human-machine interfaces..........................................................................................................................55
2.3 Orderable part numbers.................................................................................................................................................55
Chapter 3
Chip Configuration
3.1 Introduction...................................................................................................................................................................57
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Section number Title Page
3.2 Core modules................................................................................................................................................................57
3.2.1 ARM Cortex-M4 Core Configuration..........................................................................................................57
3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................59
3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration.........................................................65
3.2.4 FPU Configuration.......................................................................................................................................66
3.2.5 JTAG Controller Configuration...................................................................................................................66
3.3 System modules............................................................................................................................................................67
3.3.1 SIM Configuration.......................................................................................................................................67
3.3.2 System Mode Controller (SMC) Configuration...........................................................................................68
3.3.3 PMC Configuration......................................................................................................................................68
3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................69
3.3.5 MCM Configuration....................................................................................................................................71
3.3.6 Crossbar-Light Switch Configuration..........................................................................................................71
3.3.7 Peripheral Bridge Configuration..................................................................................................................73
3.3.8 DMA request multiplexer configuration......................................................................................................74
3.3.9 DMA Controller Configuration...................................................................................................................77
3.3.10 External Watchdog Monitor (EWM) Configuration....................................................................................78
3.3.11 Watchdog Configuration..............................................................................................................................80
3.4 Clock modules..............................................................................................................................................................81
3.4.1 MCG Configuration.....................................................................................................................................81
3.4.2 OSC Configuration......................................................................................................................................82
3.4.3 RTC OSC configuration...............................................................................................................................83
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Section number Title Page
3.5 Memories and memory interfaces.................................................................................................................................84
3.5.1 Flash Memory Configuration.......................................................................................................................84
3.5.2 Flash Memory Controller Configuration.....................................................................................................87
3.5.3 SRAM Configuration...................................................................................................................................87
3.5.4 System Register File Configuration.............................................................................................................89
3.5.5 VBAT Register File Configuration..............................................................................................................90
3.5.6 EzPort Configuration...................................................................................................................................90
3.6 Security.........................................................................................................................................................................91
3.6.1 CRC Configuration......................................................................................................................................92
3.6.2 RNG Configuration......................................................................................................................................92
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Section number Title Page
3.7 Analog...........................................................................................................................................................................93
3.7.1 16-bit SAR ADC Configuration..................................................................................................................93
3.7.2 CMP Configuration......................................................................................................................................101
3.7.3 12-bit DAC Configuration...........................................................................................................................103
3.7.4 VREF Configuration....................................................................................................................................104
3.8 Timers...........................................................................................................................................................................105
3.8.1 PDB Configuration......................................................................................................................................105
3.8.2 FlexTimer Configuration.............................................................................................................................108
3.8.3 PIT Configuration........................................................................................................................................114
3.8.4 Low-power timer configuration...................................................................................................................115
3.8.5 RTC configuration.......................................................................................................................................117
3.9 Communication interfaces............................................................................................................................................118
3.9.1 Universal Serial Bus (USB) FS Subsystem.................................................................................................118
3.9.2 SPI configuration.........................................................................................................................................123
3.9.3 I2C Configuration........................................................................................................................................127
3.9.4 UART Configuration...................................................................................................................................128
3.9.5 LPUART configuration................................................................................................................................130
3.9.6 I2S configuration..........................................................................................................................................131
3.10 Human-machine interfaces...........................................................................................................................................134
3.10.1 GPIO configuration......................................................................................................................................134
Chapter 4
Memory Map
4.1 Introduction...................................................................................................................................................................137
4.2 System memory map.....................................................................................................................................................137
4.2.1 Aliased bit-band regions..............................................................................................................................138
4.2.2 Flash Access Control Introduction...............................................................................................................140
4.3 Flash Memory Map.......................................................................................................................................................140
4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................141
4.4 SRAM memory map.....................................................................................................................................................141
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Section number Title Page
4.5 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................141
4.5.1 Read-after-write sequence and required serialization of memory operations..............................................142
4.5.2 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................142
4.6 Private Peripheral Bus (PPB) memory map..................................................................................................................146
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................147
5.2 Programming model......................................................................................................................................................147
5.3 High-Level device clocking diagram............................................................................................................................147
5.4 Clock definitions...........................................................................................................................................................148
5.4.1 Device clock summary.................................................................................................................................149
5.5 Internal clocking requirements.....................................................................................................................................152
5.5.1 Clock divider values after reset....................................................................................................................153
5.5.2 VLPR mode clocking...................................................................................................................................153
5.6 Clock Gating.................................................................................................................................................................154
5.7 Module clocks...............................................................................................................................................................154
5.7.1 PMC 1-kHz LPO clock................................................................................................................................156
5.7.2 IRC 48MHz clock........................................................................................................................................156
5.7.3 WDOG clocking..........................................................................................................................................157
5.7.4 Debug trace clock.........................................................................................................................................157
5.7.5 PORT digital filter clocking.........................................................................................................................158
5.7.6 LPTMR clocking..........................................................................................................................................158
5.7.7 RTC_CLKOUT and CLKOUT32K clocking..............................................................................................159
5.7.8 USB FS OTG Controller clocking...............................................................................................................160
5.7.9 UART clocking............................................................................................................................................161
5.7.10 LPUART0 clocking.....................................................................................................................................161
5.7.11 I2S/SAI clocking..........................................................................................................................................162
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Section number Title Page
Chapter 6
Reset and Boot
6.1 Introduction...................................................................................................................................................................165
6.2 Reset..............................................................................................................................................................................166
6.2.1 Power-on reset (POR)..................................................................................................................................166
6.2.2 System reset sources....................................................................................................................................166
6.2.3 MCU Resets.................................................................................................................................................170
6.2.4 Reset Pin .....................................................................................................................................................171
6.2.5 Debug resets.................................................................................................................................................172
6.3 Boot...............................................................................................................................................................................173
6.3.1 Boot sources.................................................................................................................................................173
6.3.2 Boot options.................................................................................................................................................173
6.3.3 FOPT boot options.......................................................................................................................................174
6.3.4 Boot sequence..............................................................................................................................................175
Chapter 7
Power Management
7.1 Introduction...................................................................................................................................................................177
7.2 Clocking modes............................................................................................................................................................177
7.2.1 Partial Stop...................................................................................................................................................177
7.2.2 DMA Wakeup..............................................................................................................................................178
7.2.3 Compute Operation......................................................................................................................................179
7.2.4 Peripheral Doze............................................................................................................................................180
7.2.5 Clock Gating................................................................................................................................................181
7.3 Power Modes Description.............................................................................................................................................181
7.4 Entering and exiting power modes...............................................................................................................................183
7.5 Power mode transitions.................................................................................................................................................184
7.6 Power modes shutdown sequencing.............................................................................................................................185
7.7 Flash Program Restrictions...........................................................................................................................................186
7.8 Module Operation in Low Power Modes......................................................................................................................186
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Section number Title Page
Chapter 8
Security
8.1 Introduction...................................................................................................................................................................191
8.2 Flash Security...............................................................................................................................................................191
8.3 Security Interactions with other Modules.....................................................................................................................192
8.3.1 Security Interactions with EzPort................................................................................................................192
8.3.2 Security Interactions with Debug.................................................................................................................192
Chapter 9
Debug
9.1 Introduction...................................................................................................................................................................193
9.1.1 References....................................................................................................................................................195
9.2 The Debug Port.............................................................................................................................................................195
9.2.1 JTAG-to-SWD change sequence.................................................................................................................196
9.2.2 JTAG-to-cJTAG change sequence...............................................................................................................196
9.3 Debug Port Pin Descriptions.........................................................................................................................................197
9.4 System TAP connection................................................................................................................................................197
9.4.1 IR Codes.......................................................................................................................................................197
9.5 JTAG status and control registers.................................................................................................................................198
9.5.1 MDM-AP Control Register..........................................................................................................................199
9.5.2 MDM-AP Status Register............................................................................................................................201
9.6 Debug Resets................................................................................................................................................................202
9.7 AHB-AP........................................................................................................................................................................203
9.8 ITM...............................................................................................................................................................................203
9.9 Core Trace Connectivity...............................................................................................................................................204
9.10 TPIU..............................................................................................................................................................................204
9.11 DWT.............................................................................................................................................................................204
9.12 Debug in Low Power Modes........................................................................................................................................205
9.12.1 Debug Module State in Low Power Modes.................................................................................................205
9.13 Debug & Security.........................................................................................................................................................206
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Section number Title Page
Chapter 10
Signal Multiplexing and Signal Descriptions
10.1 Introduction...................................................................................................................................................................207
10.2 Signal Multiplexing Integration....................................................................................................................................207
10.2.1 Port control and interrupt module features..................................................................................................208
10.2.2 Clock gating.................................................................................................................................................209
10.2.3 Signal multiplexing constraints....................................................................................................................209
10.3 Pinout............................................................................................................................................................................209
10.3.1 K22F Signal Multiplexing and Pin Assignments.........................................................................................209
10.3.2 K22F Pinouts................................................................................................................................................214
10.4 Module Signal Description Tables................................................................................................................................218
10.4.1 Core Modules...............................................................................................................................................218
10.4.2 System Modules...........................................................................................................................................219
10.4.3 Clock Modules.............................................................................................................................................219
10.4.4 Memories and Memory Interfaces...............................................................................................................220
10.4.5 Analog..........................................................................................................................................................220
10.4.6 Timer Modules.............................................................................................................................................221
10.4.7 Communication Interfaces...........................................................................................................................223
10.4.8 Human-Machine Interfaces (HMI)..............................................................................................................225
Chapter 11
Port Control and Interrupts (PORT)
11.1 Introduction...................................................................................................................................................................227
11.2 Overview.......................................................................................................................................................................227
11.2.1 Features........................................................................................................................................................227
11.2.2 Modes of operation......................................................................................................................................228
11.3 External signal description............................................................................................................................................229
11.4 Detailed signal description............................................................................................................................................229
11.5 Memory map and register definition.............................................................................................................................229
11.5.1 Pin Control Register n (PORTx_PCRn).......................................................................................................236
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