GigaDevice Semiconductor GD32F3 0 Series User manual

GigaDevice Semiconductor Inc.
GD32F3x0
Arm®Cortex®-M4 32-bit MCU
(Applicable to GD32F310, GD32GD32F330,
GD32GD32F350 series)
User Manual
Revision 2.8
(Jun. 2023)

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Table of Contents
Table of Contents...........................................................................................................3
List of Figures ..............................................................................................................16
List of Table..................................................................................................................22
1. System and memory architecture ........................................................................24
1.1. Arm®Cortex®-M4 processor ..................................................................................... 24
1.2. System architecture .................................................................................................. 25
1.3. Memory map .............................................................................................................. 26
1.3.1. Bit-banding............................................................................................................................ 29
1.3.2. On-chip SRAM memory........................................................................................................ 29
1.3.3. On-chip Flash memory ......................................................................................................... 30
1.4. Boot configuration..................................................................................................... 30
1.5. I / O compensation cell.............................................................................................. 31
1.6. System configuration registers (SYSCFG) .............................................................. 32
1.6.1. System configuration register 0 (SYSCFG_CFG0) .............................................................. 32
1.6.2. EXTI sources selection register 0 (SYSCFG_EXTISS0)...................................................... 33
1.6.3. EXTI sources selection register 1 (SYSCFG_EXTISS1)...................................................... 34
1.6.4. EXTI sources selection register 2 (SYSCFG_EXTISS2)...................................................... 35
1.6.5. EXTI sources selection register 3 (SYSCFG_EXTISS3)...................................................... 37
1.6.6. System configuration register 2 (SYSCFG_CFG2) .............................................................. 38
1.6.7. I / O compensation control register (SYSCFG_CPSCTL).................................................... 39
1.7. Device electronic signature...................................................................................... 40
1.7.1. Memory density information.................................................................................................. 40
1.7.2. Unique device ID (96 bits) .................................................................................................... 40
2. Flash memory controller (FMC)............................................................................42
2.1. Overview .................................................................................................................... 42
2.2. Characteristics........................................................................................................... 42
2.3. Function overview..................................................................................................... 42
2.3.1. Flash memory architecture ................................................................................................... 42
2.3.2. Read operations ................................................................................................................... 43
2.3.3. Unlock the FMC_CTL register .............................................................................................. 43
2.3.4. Page erase............................................................................................................................ 43
2.3.5. Mass erase ........................................................................................................................... 44
2.3.6. Main flash programming ....................................................................................................... 46
2.3.7. Option byte erase ................................................................................................................. 47
2.3.8. Option byte programming ..................................................................................................... 48

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2.3.9. Option byte description......................................................................................................... 48
2.3.10. Page erase/Program protection............................................................................................ 49
2.3.11. Security protection................................................................................................................ 50
2.4. Register definition..................................................................................................... 51
2.4.1. Wait state register (FMC_WS).............................................................................................. 51
2.4.2. Unlock key register (FMC_KEY)........................................................................................... 51
2.4.3. Option byte unlock key register (FMC_OBKEY)................................................................... 52
2.4.4. Status register (FMC_STAT)................................................................................................. 52
2.4.5. Control register (FMC_CTL)................................................................................................. 53
2.4.6. Address register (FMC_ADDR) ............................................................................................ 54
2.4.7. Option byte status register (FMC_OBSTAT)......................................................................... 55
2.4.8. Write protection register (FMC_WP)..................................................................................... 55
2.4.9. Wait state enable register (FMC_WSEN)............................................................................. 56
2.4.10. Product ID register (FMC_PID)............................................................................................. 56
3. Power management unit (PMU)............................................................................58
3.1. Overview .................................................................................................................... 58
3.2. Characteristics........................................................................................................... 58
3.3. Function overview ..................................................................................................... 58
3.3.1. Backup domain..................................................................................................................... 59
3.3.2. VDD / VDDA power domain...................................................................................................... 60
3.3.3. 1.2V power domain............................................................................................................... 62
3.3.4. Power saving modes ............................................................................................................ 62
3.4. Register definition..................................................................................................... 66
3.4.1. Control register (PMU_CTL)................................................................................................. 66
3.4.2. Control and status register (PMU_CS)................................................................................. 68
4. Reset and clock unit (RCU)...................................................................................71
4.1. Reset control unit (RCTL) ......................................................................................... 71
4.1.1. Overview............................................................................................................................... 71
4.1.2. Function overview................................................................................................................. 71
4.2. Clock control unit (CCTL) ......................................................................................... 72
4.2.1. Overview............................................................................................................................... 72
4.2.2. Characteristics...................................................................................................................... 74
4.2.3. Function overview................................................................................................................. 74
4.3. Register definition..................................................................................................... 79
4.3.1. Control register0 (RCU_CTL0)............................................................................................. 79
4.3.2. Configuration register 0 (RCU_CFG0) ................................................................................. 80
4.3.3. Interrupt register (RCU_INT) ................................................................................................ 84
4.3.4. APB2 reset register (RCU_APB2RST)................................................................................. 87
4.3.5. APB1 reset register (RCU_APB1RST)................................................................................. 88
4.3.6. AHB enable register (RCU_AHBEN).................................................................................... 90

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4.3.7. APB2 enable register (RCU_APB2EN) ................................................................................ 92
4.3.8. APB1 enable register (RCU_APB1EN) ................................................................................ 93
4.3.9. Backup domain control register (RCU_BDCTL)................................................................... 95
4.3.10. Reset source /clock register (RCU_RSTSCK) ..................................................................... 97
4.3.11. AHB reset register (RCU_AHBRST)..................................................................................... 98
4.3.12. Configuration register 1 (RCU_CFG1) ............................................................................... 100
4.3.13. Configuration register 2 (RCU_CFG2) ............................................................................... 101
4.3.14. Control register 1 (RCU_CTL1).......................................................................................... 102
4.3.15. Additional clock control register (RCU_ADDCTL) .............................................................. 102
4.3.16. Additional clock interrupt register (RCU_ADDINT)............................................................. 103
4.3.17. APB1 additional enable register (RCU_ADDAPB1EN)...................................................... 104
4.3.18. APB1 additional reset register (RCU_ADDAPB1RST)....................................................... 105
4.3.19. Voltage key register (RCU_VKEY) ..................................................................................... 105
4.3.20. Deep-sleep mode voltage register (RCU_DSV)................................................................. 106
5. Clock trim controller (CTC).................................................................................107
5.1. Overview .................................................................................................................. 107
5.2. Characteristics......................................................................................................... 107
5.3. Function overview................................................................................................... 107
5.3.1. REF sync pulse generator .................................................................................................. 108
5.3.2. CTC trim counter................................................................................................................. 108
5.3.3. Frequency evaluation and automatically trim process........................................................ 109
5.3.4. Software program guide ......................................................................................................110
5.4. Register definition....................................................................................................111
5.4.1. Control register 0 (CTC_CTL0)............................................................................................111
5.4.2. Control register 1 (CTC_CTL1)............................................................................................112
5.4.3. Status register (CTC_STAT)................................................................................................113
5.4.4. Interrupt clear register (CTC_INTC) ....................................................................................115
6. Interrupt/event controller (EXTI)......................................................................... 117
6.1. Overview ...................................................................................................................117
6.2. Characteristics..........................................................................................................117
6.3. Interrupts function overview....................................................................................117
6.4. External interrupt and event block diagram .......................................................... 120
6.5. External interrupt and event function overview .................................................... 120
6.6. Register definition................................................................................................... 123
6.6.1. Interrupt enable register (EXTI_INTEN) ............................................................................. 123
6.6.2. Event enable register (EXTI_EVEN) .................................................................................. 123
6.6.3. Rising edge trigger enable register (EXTI_RTEN) ............................................................. 124
6.6.4. Falling edge trigger enable register (EXTI_FTEN)............................................................. 124
6.6.5. Software interrupt event register (EXTI_SWIEV) ............................................................... 125

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6.6.6. Pending register (EXTI_PD)............................................................................................... 125
7. General-purpose and alternate-function I/Os (GPIO)........................................127
7.1. Overview .................................................................................................................. 127
7.2. Characteristics......................................................................................................... 127
7.3. Function overview................................................................................................... 127
7.3.1. GPIO pin configuration ....................................................................................................... 128
7.3.2. Alternate functions (AF)...................................................................................................... 129
7.3.3. Additional functions............................................................................................................. 129
7.3.4. Input configuration .............................................................................................................. 129
7.3.5. Output configuration ........................................................................................................... 130
7.3.6. Analog configuration........................................................................................................... 130
7.3.7. Alternate function (AF) configuration.................................................................................. 131
7.3.8. GPIO locking function......................................................................................................... 132
7.3.9. GPIO single cycle toggle function....................................................................................... 132
7.3.10. GPIO very high speed drive capability ............................................................................... 132
7.4. Register definition................................................................................................... 133
7.4.1. Port control register (GPIOx_CTL, x=A..D,F)..................................................................... 133
7.4.2. Port output mode register (GPIOx_OMODE, x=A..D,F)..................................................... 134
7.4.3. Port output speed register 0 (GPIOx_OSPD0, x=A..D,F)................................................... 136
7.4.4. Port pull-up/down register (GPIOx_PUD, x=A..D,F)........................................................... 138
7.4.5. Port input status register (GPIOx_ISTAT, x=A..D,F)........................................................... 139
7.4.6. Port output control register (GPIOx_OCTL, x=A..D,F) ....................................................... 140
7.4.7. Port bit operate register (GPIOx_BOP, x=A..D,F)............................................................... 140
7.4.8. Port configuration lock register (GPIOx_LOCK, x=A,B) ..................................................... 141
7.4.9. Alternate function selected register 0 (GPIOx_AFSEL0, x=A,B,C).................................... 142
7.4.10. Alternate function selected register 1 (GPIOx_AFSEL1, x=A,B,C).................................... 143
7.4.11. Bit clear register (GPIOx_BC, x=A..D,F) ............................................................................ 144
7.4.12. Port bit toggle register (GPIOx_TG, x=A..D,F)................................................................... 144
7.4.13. Port output speed register 1 (GPIOx_OSPD1, x=A..D,F)................................................... 145
8. Cyclic redundancy checks management unit (CRC) ........................................146
8.1. Overview .................................................................................................................. 146
8.2. Characteristics......................................................................................................... 146
8.3. Function overview................................................................................................... 147
8.4. Register definition................................................................................................... 148
8.4.1. Data register (CRC_DATA)................................................................................................. 148
8.4.2. Free data register (CRC_FDATA)....................................................................................... 148
8.4.3. Control register (CRC_CTL)............................................................................................... 149
8.4.4. Initialization data register (CRC_IDATA)............................................................................. 149
8.4.5. Polynomial register (CRC_POLY)....................................................................................... 150

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9. Direct memory access controller (DMA)............................................................151
9.1. Overview .................................................................................................................. 151
9.2. Characteristics......................................................................................................... 151
9.3. Block diagram.......................................................................................................... 152
9.4. Function overview................................................................................................... 152
9.4.1. DMA operation.................................................................................................................... 152
9.4.2. Peripheral handshake......................................................................................................... 154
9.4.3. Arbitration............................................................................................................................ 154
9.4.4. Address generation............................................................................................................. 155
9.4.5. Circular mode...................................................................................................................... 155
9.4.6. Memory to memory mode................................................................................................... 155
9.4.7. Channel configuration......................................................................................................... 155
9.4.8. Interrupt............................................................................................................................... 156
9.4.9. DMA request mapping ........................................................................................................ 157
9.5. Register definition................................................................................................... 160
9.5.1. Interrupt flag register (DMA_INTF)..................................................................................... 160
9.5.2. Interrupt flag clear register (DMA_INTC)............................................................................ 160
9.5.3. Channel x control register (DMA_CHxCTL) ....................................................................... 161
9.5.4. Channel x counter register (DMA_CHxCNT)...................................................................... 163
9.5.5. Channel x peripheral base address register (DMA_CHxPADDR)...................................... 164
9.5.6. Channel x memory base address register (DMA_CHxMADDR)........................................ 164
10. Debug (DBG).....................................................................................................166
10.1. Overview............................................................................................................... 166
10.2. Serial Wire Debug port overview......................................................................... 166
10.2.1. Pin assignment ................................................................................................................... 166
10.2.2. JEDEC-106 ID code ........................................................................................................... 166
10.3. Debug hold function overview ............................................................................ 167
10.3.1. Debug support for power saving mode............................................................................... 167
10.3.2. Debug support for TIMER, I2C, RTC, WWDGT and FWDGT............................................ 167
10.4. Register definition................................................................................................ 168
10.4.1. ID code register (DBG_ID).................................................................................................. 168
10.4.2. Control register 0 (DBG_CTL0).......................................................................................... 168
10.4.3. Control register 1 (DBG_CTL1).......................................................................................... 170
11. Analog to digital converter (ADC) ...................................................................172
11.1. Overview............................................................................................................... 172
11.2. Characteristics..................................................................................................... 172
11.3. Pins and internal signals..................................................................................... 173
11.4. Function overview................................................................................................ 174

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11.4.1. Foreground calibration function.......................................................................................... 174
11.4.2. Dual clock domain architecture........................................................................................... 175
11.4.3. ADCON enable................................................................................................................... 175
11.4.4. Routine sequence............................................................................................................... 175
11.4.5. Operation modes ................................................................................................................ 175
11.4.6. Conversion result threshold monitor function ..................................................................... 178
11.4.7. Data storage mode ............................................................................................................. 178
11.4.8. Sample time configuration.................................................................................................. 179
11.4.9. External trigger configuration.............................................................................................. 179
11.4.10. DMA request ....................................................................................................................... 180
11.4.11. ADC internal channels........................................................................................................ 180
11.4.12. ADC interrupts .................................................................................................................... 181
11.4.13. Programmable resolution (DRES)...................................................................................... 181
11.4.14. On-chip hardware oversampling......................................................................................... 181
11.5. Register definition................................................................................................ 184
11.5.1. Status register (ADC_STAT)............................................................................................... 184
11.5.2. Control register 0 (ADC_CTL0) .......................................................................................... 184
11.5.3. Control register 1 (ADC_CTL1) .......................................................................................... 186
11.5.4. Sampling time register 0 (ADC_SAMPT0) ......................................................................... 188
11.5.5. Sampling time register 1 (ADC_SAMPT1) ......................................................................... 188
11.5.6. Watchdog high threshold register (ADC_WDHT)............................................................... 189
11.5.7. Watchdog low threshold register (ADC_WDLT) ................................................................. 190
11.5.8. Routine sequence register0(ADC_RSQ0).......................................................................... 190
11.5.9. Routine sequence register1(ADC_RSQ1).......................................................................... 191
11.5.10. Routine sequence register 2 (ADC_RSQ2)........................................................................ 191
11.5.11. Routine data register (ADC_RDATA).................................................................................. 192
11.5.12. Oversampling control register (ADC_OVSAMPCTL) ......................................................... 192
12. Digital-to-analog converter (DAC)...................................................................195
12.1. Overview............................................................................................................... 195
12.2. Characteristic....................................................................................................... 195
12.3. Function overview................................................................................................ 196
12.3.1. DAC enable......................................................................................................................... 196
12.3.2. DAC output buffer............................................................................................................... 196
12.3.3. DAC data configuration....................................................................................................... 196
12.3.4. DAC trigger......................................................................................................................... 196
12.3.5. DAC workflow ..................................................................................................................... 197
12.3.6. DAC noise wave ................................................................................................................. 197
12.3.7. DAC output calculate.......................................................................................................... 198
12.3.8. DMA function....................................................................................................................... 198
12.4. Registers definition.............................................................................................. 199
12.4.1. Control register (DAC_CTL) ............................................................................................... 199

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12.4.2. Software trigger register (DAC_SWT) ................................................................................ 200
12.4.3. DAC 12-bit right-aligned data holding register(DAC_R12DH)............................................ 201
12.4.4. DAC 12-bit left-aligned data holding register(DAC_L12DH) .............................................. 201
12.4.5. DAC 8-bit right-aligned data holding register (DAC_R8DH)............................................... 202
12.4.6. DAC data output register (DAC_DO).................................................................................. 202
12.4.7. DAC Status register (DAC_STAT)...................................................................................... 202
13. Comparator (CMP)............................................................................................204
13.1. Overview............................................................................................................... 204
13.2. Characteristic....................................................................................................... 204
13.3. Function overview................................................................................................ 204
13.3.1. CMP clock and reset........................................................................................................... 205
13.3.2. CMP I/O configure .............................................................................................................. 205
13.3.3. CMP operating mode.......................................................................................................... 206
13.3.4. CMP hysteresis................................................................................................................... 206
13.3.5. CMP register write protection ............................................................................................. 206
13.4. CMP registers....................................................................................................... 207
13.4.1. Control/status register (CMP_CS)...................................................................................... 207
14. Watchdog timer (WDGT) .................................................................................. 211
14.1. Free watchdog timer (FWDGT).............................................................................211
14.1.1. Overview..............................................................................................................................211
14.1.2. Characteristics.....................................................................................................................211
14.1.3. Function overview................................................................................................................211
14.1.4. Register definition............................................................................................................... 214
14.2. Window watchdog timer (WWDGT)..................................................................... 218
14.2.1. Overview............................................................................................................................. 218
14.2.2. Characteristics.................................................................................................................... 218
14.2.3. Function overview............................................................................................................... 218
14.2.4. Register definition............................................................................................................... 221
15. Real-time clock (RTC).......................................................................................223
15.1. Overview............................................................................................................... 223
15.2. Characteristics..................................................................................................... 223
15.3. Function overview................................................................................................ 224
15.3.1. Block diagram..................................................................................................................... 224
15.3.2. Clock source and prescalers .............................................................................................. 224
15.3.3. Shadow registers introduction ............................................................................................ 225
15.3.4. Configurable and field maskable alarm .............................................................................. 225
15.3.5. RTC initialization and configuration .................................................................................... 226
15.3.6. Calendar reading ................................................................................................................ 227
15.3.7. Resetting the RTC .............................................................................................................. 228

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15.3.8. RTC shift function ............................................................................................................... 228
15.3.9. RTC reference clock detection ........................................................................................... 229
15.3.10. RTC smooth digital calibration............................................................................................ 230
15.3.11. Time-stamp function ........................................................................................................... 232
15.3.12. Tamper detection ................................................................................................................ 232
15.3.13. Calibration clock output ...................................................................................................... 233
15.3.14. Alarm output........................................................................................................................ 233
15.3.15. RTC power saving mode management.............................................................................. 234
15.3.16. RTC interrupts..................................................................................................................... 234
15.4. Register definition................................................................................................ 235
15.4.1. Time register (RTC_TIME).................................................................................................. 235
15.4.2. Date register (RTC_DATE)................................................................................................. 235
15.4.3. Control register (RTC_CTL)................................................................................................ 236
15.4.4. Status register (RTC_STAT) ............................................................................................... 238
15.4.5. Prescaler register (RTC_PSC) ........................................................................................... 240
15.4.6. Alarm 0 time and date register (RTC_ALRM0TD).............................................................. 240
15.4.7. Write protection key register (RTC_WPK).......................................................................... 242
15.4.8. Sub second register (RTC_SS) .......................................................................................... 242
15.4.9. Shift function control register (RTC_SHIFTCTL)................................................................ 242
15.4.10. Time of time stamp register (RTC_TTS)............................................................................. 243
15.4.11. Date of time stamp register (RTC_DTS)............................................................................. 244
15.4.12. Sub second of time stamp register (RTC_SSTS)............................................................... 244
15.4.13. High resolution frequency compensation register (RTC_HRFC) ....................................... 245
15.4.14. Tamper register (RTC_TAMP) ............................................................................................ 246
15.4.15. Alarm 0 sub second register (RTC_ALRM0SS) ................................................................. 248
15.4.16. Backup registers (RTC_BKPx) (x = 0..4)............................................................................ 249
16. Timer (TIMERx) .................................................................................................251
16.1. Advanced timer (TIMERx ,x=0)............................................................................ 252
16.1.1. Overview............................................................................................................................. 252
16.1.2. Characteristics.................................................................................................................... 252
16.1.3. Block diagram..................................................................................................................... 253
16.1.4. Function overview............................................................................................................... 254
16.1.5. Register definition............................................................................................................... 280
16.2. General level0 timer (TIMERx, x=1, 2)................................................................. 307
16.2.1. Overview............................................................................................................................. 307
16.2.2. Characteristics.................................................................................................................... 307
16.2.3. Block diagram..................................................................................................................... 308
16.2.4. Function overview............................................................................................................... 309
16.2.5. Register definition............................................................................................................... 324
16.3. General level2 timer (TIMERx, x=13)................................................................... 349
16.3.1. Overview............................................................................................................................. 349
16.3.2. Characteristics.................................................................................................................... 349