SONIX SN8P2714_2715 User manual

SN8P2714X_2715
8-bit micro-controller build-in 12-bit ADC
SONiX TECHNOLOGY CO., LTD Page1 V1.4
SN8P2714X_2715
USER’S MANUAL
V1.4
SN8P2714
SN8P27142
SN8P27143
SN8P2715
S
SO ON Ni iX X 8 8- -B Bi it t M Mi ic cr ro o- -C Co on nt tr ro ol ll le er r
SONIX reserves the right to make change without further notice to any products herein to improve reliability, function or design. SONIX does not
assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent
rights nor the rights of others. SONIX products are not designed, intended, or authorized for us as components in systems intended, for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SONIX product
could create a situation where personal injury or death may occur. Should Buyer purchase or use SONIX products for any such unintended or
unauthorized application. Buyer shall indemnify and hold SONIX and its officers, employees, subsidiaries, affiliates and distributors harmless against
all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of
the part.

SN8P2714X_2715
8-bit micro-controller build-in 12-bit ADC
SONiX TECHNOLOGY CO., LTD Page2 V1.4
AMENDMENT HISTORY
Version Date Description
VER 0.1 Aug. 2004 Preliminary Version first issue
VER 0.2 Jan. 2005 1. Add SN8P27142/ SN8P27143 relative data.
2. Fix ADC clock and Timer clock description.
3. Add LVD36 relative information.
4. Correct the LVD24 bit location from bit 3 to bit 4 in PFLAG register description.
5. Modify LVD code option related description
6. Modify TC0RATE and TC1RATE table.
7. Add TC0X8 and TC1X8 notice.
8. Release the ROM address 0x04 ~ 0x07 as general-purpose area.
9. Remove the instruction limitation at interrupt vector address (0x08)
10. Change IDE support version to M2IDE V1.04
11. Modify pin circuit diagram.
12. There is no Schmitt trigger input in port 4.
13. Add description of P0.3 without wakeup function
VER 0.3 Mar. 2005 1. Modify Zero flag description.
2. In instruction set table, change “S = 0”, otherwise “S = 1” to “S = 1”, otherwise “S =
0”
3. Fix ADC conversion time formula.
4. Remove “Note:For 12-bit resolution the conversion time is 16 steps”.
5. Remove “Note: Please use "@RST_WDT" macro to clear the watchdog timer
successfully both in S8KD-2 ICE emulation and real chip.”
6. Modify watchdog reset section
7. Fixed the slow mode current of electrical characteristic table.
Sept 2005 1. Modify Programming Pin Mapping.
2. Modify PROGRAM CHECK LIST.
3. Modify P13 AVREF pin description
4. Modify 27142/143 pin assignment.
5. Modify P57,P66 TC0RATE、TC1RATE.
6. Modify P57,P66:TC0X8=1 Fosc/2~Fosc/256 to Fosc/1~Fosc/128
7. Modify P107 SLOW Mode Current.
8. ADD P97 “Note”.
VER 1.0
Nov.2005 1. ADD Brown-Out reset circuit.
2. Working Voltage vs. Frequency graphs.
VER 1.1 Nov.2005 1. ADD ADC current.
2. Modify Topr value.
VER 1.2 Dec.2005 1. Remove 32k mode.
2. Modify P108 SN8P271XAXD to SN8P271XXD.
3. Modify P52 wakeup trigger signal.
4. Remove CHARACTERISTIC GRAPHS.
5. Modify reset section.
6. Limit Fcpu=Fosc/4~./8 when Noise Filter enable
7. Remove Pc
VER 1.3 Sep.2006 1. Modify 15.2 STANDARD ELECTRICAL CHARACTERISTIC.
2. Add 15.3 CHARACTERISTIC GRAPHS.
3. Add chapter17 Marking Definition.
VER 1.4 Feb 2007 1. Modify ELECTRICAL CHARACTERISTIC.
2. Modify RST/P0.3/VPP PIN DISCRIPTION.

SN8P2714X_2715
8-bit micro-controller build-in 12-bit ADC
SONiX TECHNOLOGY CO., LTD Page3 V1.4
Table of Contents
AMENDMENT HISTORY .............................................................................................................. 2
1 PRODUCT OVERVIEW................................................................................................................. 8
1.1 FEATURES OF SN8P2710 SERIES........................................................................................... 8
1.2 SYSTEM BLOCK DIAGRAM ................................................................................................. 10
1.3 PIN ASSIGNMENT................................................................................................................ 11
1.3.1 SN8P27142 Pin Assignment .......................................................................................... 11
1.3.2 SN8P27143 Pin Assignment .......................................................................................... 11
1.3.3 SN8P2714K Pin Assignment.......................................................................................... 12
1.3.4 SN8P2715P Pin Assignment.......................................................................................... 12
1.4 PIN DESCRIPTIONS............................................................................................................. 13
1.5 PIN CIRCUIT DIAGRAMS ..................................................................................................... 14
2 CODE OPTION TABLE............................................................................................................... 15
3 ADDRESS SPACES ................................................................................................................... 16
3.1 PROGRAM MEMORY (ROM) ............................................................................................... 16
3.1.1 OVERVIEW.................................................................................................................... 16
3.1.2 USER RESET VECTOR ADDRESS (0000H)................................................................. 17
3.1.3 INTERRUPT VECTOR ADDRESS (0008H)................................................................... 17
3.1.4 GENERAL PURPOSE PROGRAM MEMORY AREA..................................................... 19
3.1.5 LOOKUP TABLE DESCRIPTION................................................................................... 19
3.1.6 JUMP TABLE DESCRIPTION........................................................................................ 21
3.2 DATA MEMORY (RAM)......................................................................................................... 23
3.2.1 OVERVIEW.................................................................................................................... 23
3.3 WORKING REGISTERS ....................................................................................................... 24
3.3.1 Y, Z REGISTERS........................................................................................................... 24
3.3.2 R REGISTERS...............................................................................................................25
3.4 PROGRAM FLAG.................................................................................................................. 25
3.4.1 RESET FLAG................................................................................................................. 25
3.4.2 LVD 2.4V FLAG.............................................................................................................. 25
3.4.3 LVD 3.6V FLAG.............................................................................................................. 25
3.4.4 CARRY FLAG................................................................................................................. 26
3.4.5 DECIMAL CARRY FLAG................................................................................................ 26
3.4.6 ZERO FLAG................................................................................................................... 26
3.5 ACCUMULATOR................................................................................................................... 27
3.6 STACK OPERATIONS .......................................................................................................... 28
3.6.1 OVERVIEW.................................................................................................................... 28

SN8P2714X_2715
8-bit micro-controller build-in 12-bit ADC
SONiX TECHNOLOGY CO., LTD Page4 V1.4
3.6.2 STACK REGISTERS...................................................................................................... 29
3.6.3 STACK OPERATION EXAMPLE.................................................................................... 30
3.7 PROGRAM COUNTER ......................................................................................................... 31
3.7.1 ONE ADDRESS SKIPPING ........................................................................................... 32
3.7.2 MULTI-ADDRESS JUMPING......................................................................................... 33
4 ADDRESSING MODE................................................................................................................. 34
4.1 OVERVIEW........................................................................................................................... 34
4.1.1 IMMEDIATE ADDRESSING MODE............................................................................... 34
4.1.2 DIRECTLY ADDRESSING MODE ................................................................................. 34
4.1.3 INDIRECTLY ADDRESSING MODE.............................................................................. 34
4.1.4 TO ACCESS DATA in RAM BANK 0.............................................................................. 35
5 SYSTEM REGISTER................................................................................................................... 36
5.1 OVERVIEW........................................................................................................................... 36
5.2 SYSTEM REGISTER ARRANGEMENT (BANK 0) ................................................................ 36
5.2.1 BYTES of SYSTEM REGISTER..................................................................................... 36
5.2.2 BITS of SYSTEM REGISTER ........................................................................................ 37
6 RESET......................................................................................................................................... 39
6.1 OVERVIEW........................................................................................................................... 39
6.2 POWER ON RESET.............................................................................................................. 40
6.3 WATCHDOG RESET ............................................................................................................ 40
6.4 BROWN OUT RESET ........................................................................................................... 41
6.4.1 BROWN OUT DESCRIPTION........................................................................................ 41
6.4.2 THE SYSTEM OPERATING VOLTAGE DECSRIPTION............................................... 42
6.4.3 BROWN OUT RESET IMPROVEMENT......................................................................... 42
6.5 EXTERNAL RESET............................................................................................................... 44
6.6 EXTERNAL RESET CIRCUIT ............................................................................................... 44
6.6.1 Simply RC Reset Circuit................................................................................................. 44
6.6.2 Diode & RC Reset Circuit............................................................................................... 45
6.6.3 Zener Diode Reset Circuit.............................................................................................. 45
6.6.4 Voltage Bias Reset Circuit.............................................................................................. 46
6.6.5 External Reset IC ........................................................................................................... 47
7 OSCILLATORS........................................................................................................................... 48
7.1 OVERVIEW........................................................................................................................... 48
7.1.1 OSCM REGISTER DESCRIPTION................................................................................ 49
7.1.2 EXTERNAL HIGH-SPEED OSCILLATOR...................................................................... 49
7.1.3 HIGH CLOCK OSCILLATOR CODE OPTION ............................................................... 49
7.1.4 SYSTEM OSCILLATOR CIRCUITS............................................................................... 50

SN8P2714X_2715
8-bit micro-controller build-in 12-bit ADC
SONiX TECHNOLOGY CO., LTD Page5 V1.4
7.1.5 External RC Oscillator Frequency Measurement............................................................ 51
7.2 INTERNAL LOW-SPEED OSCILLATOR............................................................................... 52
7.3 SYSTEM MODE DESCRIPTION........................................................................................... 53
7.3.1 OVERVIEW.................................................................................................................... 53
7.3.2 NORMAL MODE ............................................................................................................ 53
7.3.3 SLOW MODE.................................................................................................................53
7.3.4 POWER DOWN (SLEEP) MODE................................................................................... 53
7.4 SYSTEM MODE CONTROL.................................................................................................. 54
7.4.1 SN8P2710 SYSTEM MODE BLOCK DIAGRAM............................................................ 54
7.4.2 SYSTEM MODE SWITCHING ....................................................................................... 55
7.5 WAKEUP TIME ..................................................................................................................... 56
7.5.1 OVERVIEW.................................................................................................................... 56
7.5.2 HARDWARE WAKEUP.................................................................................................. 56
8 TIMERS COUNTERS.................................................................................................................. 57
8.1 WATCHDOG TIMER (WDT).................................................................................................. 57
8.2 TIMER COUNTER 0(TC0).................................................................................................... 58
8.2.1 OVERVIEW.................................................................................................................... 58
8.2.2 TC0M MODE REGISTER............................................................................................... 59
8.2.3 TC0C COUNTING REGISTER....................................................................................... 61
8.2.4 TC0R AUTO-LOAD REGISTER..................................................................................... 63
8.2.5 TC0 TIMER COUNTER OPERATION SEQUENCE....................................................... 64
8.2.6 TC0 CLOCK FREQUENCY OUTPUT (BUZZER)........................................................... 66
8.3 TIMER COUNTER 1(TC1).................................................................................................... 67
8.3.1 OVERVIEW.................................................................................................................... 67
8.3.2 TC1M MODE REGISTER............................................................................................... 68
8.3.3 TC1C COUNTING REGISTER....................................................................................... 70
8.3.4 TC1R AUTO-LOAD REGISTER..................................................................................... 72
8.3.5 TC1 TIMER COUNTER OPERATION SEQUENCE....................................................... 73
8.3.6 TC1 CLOCK FREQUENCY OUTPUT (BUZZER)........................................................... 75
8.4 PWM FUNCTION DESCRIPTION......................................................................................... 76
8.4.1 OVERVIEW.................................................................................................................... 76
8.4.2 PWM PROGRAM DESCRIPTION.................................................................................. 77
8.4.3 PWM Duty with TCxR changing ..................................................................................... 78
8.4.4 TCxIRQ and PWM Duty ................................................................................................. 79
9 INTERRUPT ................................................................................................................................ 80
9.1 OVERVIEW........................................................................................................................... 80
9.2 INTEN INTERRUPT ENABLE REGISTER ............................................................................ 80
9.3 INTRQ INTERRUPT REQUEST REGISTER......................................................................... 81

SN8P2714X_2715
8-bit micro-controller build-in 12-bit ADC
SONiX TECHNOLOGY CO., LTD Page6 V1.4
9.4 P0.0 INTERRUPT TRIGGER EDGE CONTROL REGISTER ................................................ 81
9.5 INTERRUPT OPERATION DESCRIPTION........................................................................... 82
9.5.1 GIE GLOBAL INTERRUPT OPERATION ...................................................................... 82
9.5.2 INT0 (P0.0) INTERRUPT OPERATION ......................................................................... 83
9.5.3 INT1 (P0.1) INTERRUPT OPERATION ......................................................................... 83
9.5.4 TC0 INTERRUPT OPERATION..................................................................................... 85
9.5.5 TC1 INTERRUPT OPERATION..................................................................................... 86
9.5.6 MULTI-INTERRUPT OPERATION................................................................................. 87
10 I/O PORT................................................................................................................................... 89
10.1 OVERVIEW......................................................................................................................... 89
10.2 I/O PORT FUNCTION TABLE ............................................................................................. 90
10.3 PULL-UP RESISTERS ........................................................................................................ 91
10.4 I/O PORT DATA REGISTER ............................................................................................... 94
11 8-CHANNEL ANALOG TO DIGITAL CONVERTER................................................................. 96
11.1 OVERVIEW......................................................................................................................... 96
11.2 ADM REGISTER ................................................................................................................. 97
11.3 ADR REGISTERS ............................................................................................................... 97
11.4 ADB REGISTERS ............................................................................................................... 97
11.5 P4CON REGISTERS .......................................................................................................... 98
11.6 ADC CONVERTING TIME................................................................................................... 99
11.7 ADC CIRCUIT ................................................................................................................... 100
12 7-BIT DIGITAL TO ANALOG CONVERTER .......................................................................... 101
12.1 OVERVIEW....................................................................................................................... 101
12.2 DAM REGISTER ............................................................................................................... 102
12.3 D/A CONVERTER OPERATION ....................................................................................... 102
13 CODING ISSUE ...................................................................................................................... 103
13.1 TEMPLATE CODE ............................................................................................................ 103
13.2 PROGRAM CHECK LIST .................................................................................................. 107
14 INSTRUCTION SET TABLE ................................................................................................... 108
15 ELECTRICAL CHARACTERISTIC ......................................................................................... 109
15.1 ABSOLUTE MAXIMUM RATING....................................................................................... 109
15.2 STANDARD ELECTRICAL CHARACTERISTIC................................................................ 109
15.3 CHARACTERISTIC GRAPHS........................................................................................... 110
16 DEVELOPMENT TOOLS ........................................................................................................ 114
16.1 DEVELOPMENT TOOL VERSION ............................................................................................. 114

SN8P2714X_2715
8-bit micro-controller build-in 12-bit ADC
SONiX TECHNOLOGY CO., LTD Page7 V1.4
16.1.1 ICE (In circuit emulation)............................................................................................ 114
16.1.2 OTP Writer ................................................................................................................. 114
16.1.3 IDE (Integrated Development Environment)............................................................... 114
16.2 SN8P2715/SN8P2714 EV-KIT .......................................................................................... 115
16.2.1 PCB DESCRIPTION................................................................................................... 115
16.3 SN8P2715/14 EV-KIT CONNNECT TO SN8ICE 2K .......................................................... 116
16.4 TRANSITION BOARD FOR OTP PROGTRAMMING........................................................ 117
16.4.1 SN8P2715/2715 Rev. B TRANSITION BOARD......................................................... 117
16.4.2 CONNNECT Rev. B TRANSITION BOARD TO EASY WRITER................................ 117
16.5 OTP PROGRAMMING PIN TO TRANSITION BOARD MAPPING..................................................... 118
16.5.1 The pin assignment of Easy and MP EZ Writer transition board socket:.................... 118
16.5.2 The pin assignment of Writer V3.0 transition board socket: ....................................... 118
16.5.3 SN8P2710 Series Programming Pin Mapping:........................................................... 119
17 MARKING DEFINITION .......................................................................................................... 120
17.1 INTRODUCTION............................................................................................................... 120
17.2 MARKING INDETIFICATION SYSTEM............................................................................. 120
17.3 MARKING EXAMPLE........................................................................................................ 121
17.4 DATECODE SYSTEM....................................................................................................... 121
18 PACKAGE INFORMATION .................................................................................................... 122
18.1 P-DIP18 PIN...................................................................................................................... 122
18.2 SOP18 PIN........................................................................................................................ 123
18.3 P-DIP 20 PIN ..................................................................................................................... 124
18.4 SOP 20 PIN ....................................................................................................................... 125
18.5 SSOP20 PIN ..................................................................................................................... 126
18.6 SK-DIP28 PIN ................................................................................................................... 127
18.7 SOP28 PIN........................................................................................................................ 128
18.8 P-DIP 32 PIN ..................................................................................................................... 129
18.9 SOP 32 PIN ....................................................................................................................... 129

SN8P2714X_2715
8-bit micro-controller build-in 12-bit ADC
SONiX TECHNOLOGY CO., LTD Page8 V1.4
1 PRODUCT OVERVIEW
1.1 FEATURES of SN8P2710 Series
♦Memory configuration ♦Four interrupt sources
OTP ROM size: 2K * 16 bits. Two internal interrupts: TC0, TC1
RAM size: 128 * 8 bits Two external interrupts: INT0, INT1
Eight levels stack buffer
♦Two 8-bit Timer/Counter
♦I/O pin configuration TC0: Auto-reload timer/Counter/PWM0/Buzzer output
Input only pin: P0 TC1: Auto-reload timer/Counter/PWM1/Buzzer output
Bi-directional: P2, P4, P5 ♦On chip watchdog timer.
Wakeup: P0.0, P0.1, P0.2
External interrupt: P0.0, P0.1 ♦System clocks and Operating modes
Pull-up resisters: P0, P2, P4, P5 External high clock: RC type up to 10 MHz
P4 pins shared with ADC inputs. External high clock: Crystal type up to 16 MHz
♦Max 8-channel 12-bit ADC. Internal low clock: RC type 16KHz(3V), 32KHz(5V)
Normal mode: Both high and low clock active
♦One channel 7-bit DAC. Slow mode: Low clock only
Sleep mode: Both high and low clock stop
♦Powerful instructions
One clocks per instruction cycle (1T)
Most of instructions are one cycle only ♦Package (Chip form support)
All ROM area lookup table function (MOVC) SN8P27142: P-DIP 18 pins, SOP 18pins
SN8P27143:P-DIP 20 pins, SOP 20 pins, SSOP 20 pins
SN8P2714: SK-DIP 28 pins, SOP 28pins
SN8P2715: P-DIP 32 pins, SOP 32 pins
FEATURES SELECTION TABLE
Timer PWM
CHIP ROM RAM Stack
T0 TC0 TC1
I/O ADC DAC
Buzzer
SIO Wakeup
Pin no.
Package
SN8P27142 2K*16 128 8 - V V 15 5ch - 2 - 2 DIP18/SOP18
SN8P27143 2K*16 128 8 - V V 16 6ch - 2 - 2 DIP20/SOP20/SSOP20
SN8P2714 2K*16 128 8 - V V 23 8ch 1ch 2 - 3 SKDIP28/SOP28
SN8P2715 2K*16 128 8 - V V 27 8ch 1ch 2 - 3 DIP32/SOP32
SN8P2704A 4K*16 256 8 V V V 18 5ch 1ch 2 18 SKDIP28/SOP28
SN8P2705A 4K*16 256 8 V V V 23 8ch 1ch 2 19 DIP32/SOP32
Note: For SN8P27143 and SN8P27142 must configure P02R (bit 2 of P0UR) as “1” to avoid sleep mode fail.

SN8P2714X_2715
8-bit micro-controller build-in 12-bit ADC
SONiX TECHNOLOGY CO., LTD Page9 V1.4
Compare SN8P2714/15 to SN8P2704A/05A
Item SN8P2714/15 SN8P2704A/05A
AC Noise Immunity Capability
Excellent
(Add an 47uF bypass Capacitor
between VDD and GND)
Excellent
(Add an 47uF bypass Capacitor
between VDD and GND)
Memory ROM: 2K x 16
RAM: 128 x 8
ROM: 4K x 16
RAM: 256 x 8
Maximum I/O pins 23 I/O in 28 pins package
27 I/O in 32 pins package
18 I/O in 28 pins package
23 I/O in 32 pins package
High Speed PWM
PWM Resolution: 8bit/6bit/5bit/4bit
8bit PWM up to 62.5K at 16Mhz
4bit PWM up to 1000K at 16Mhz
PWM Resolution: 8bit/6bit/5bit/4bit
8bit PWM up to 7.8125K at 16Mhz
4bit PWM up to 125K at 16Mhz
Programmable Open-Drain Output N/A P1.0 / P1.1 / P5.2 (SO)
B0MOV M, I No Limitation “I” can’t be 0E6h or 0E7h
B0XCH A, M No Limitation The address of M
can’t be 80h ~ FFh
Valid instruction in ROM address 8 No Limitation JMP or NOP
ADC Interrupt No Yes
ADC Clock Frequency Four kinds of setting
(Configuration by ADCKS [1:0])
Seven kinds of setting
(Configuration by ADCKS [2:0])
Valid Range of
TC0C/TC1C/TC0R/TC1R 0x00 ~ 0xFF 0x00 ~ 0xFE
Green mode No Yes
SIO Function No Yes
LVD Level: 2.0V always ON 1.8V always ON
Port 0 Input only port Bi-direction port
Interrupt Vector Instruction No Limitation NOP/JMP only
PUSH/POP Instruction No Yes

SN8P2714X_2715
8-bit micro-controller build-in 12-bit ADC
SONiX TECHNOLOGY CO., LTD Page10 V1.4
1.2 SYSTEM BLOCK DIAGRAM
Figure 1-1.Simplified System Block Diagram
PC
IR OTP
ROM
H-OSC
TIMING GENERATOR
RAM
SYSTEM REGISTER
ALU
ACC
INTERRUPT
CONTROL TIMER & COUNTER
PORT0
PORT2 PORT4 PORT5
FLAGS
DAC
ADC
DAO
AIN0~AIN7
Internal
CLK
PWM1
PWM0 PWM0/Buzzer0
PWM1/Buzzer1
Low Vo lt
Detector
Watch-Dog
Timer
PC
IR OTP
ROM
H-OSC
TIMING GENERATOR
RAM
SYSTEM REGISTER
ALU
ACC
INTERRUPT
CONTROL TIMER & COUNTER
PORT0
PORT2 PORT4 PORT5
FLAGS
DAC
ADC
DAO
AIN0~AIN7
Internal
CLK
PWM1
PWM0 PWM0/Buzzer0
PWM1/Buzzer1
Low Vo lt
Detector
Watch-Dog
Timer

SN8P2714X_2715
8-bit micro-controller build-in 12-bit ADC
SONiX TECHNOLOGY CO., LTD Page11 V1.4
1.3 PIN ASSIGNMENT
Format Description：SN8P271xY Y = K > SK-DIP，P > P-DIP，S> SOP
1.3.1 SN8P27142 Pin Assignment
P0.1 1 U 18 P0.0
P2.0 2 17 P5.0
P2.1 3 16 P5.1
P5.6/XOUT 4 15 P5.3/BZ1/PWM1
XIN 5 14 P5.4/BZ0/PWM0
VSS 6 13 P0.3/RST/VPP
P4.4/AIN4 7 12 VDD
P4.3/AIN3 8 11 P4.0/AIN0
P4.2/AIN2 9 10 P4.1/AIN1
SN8P27142P
SN8P27142S
1.3.2 SN8P27143 Pin Assignment
P2.0 1 U 20 P0.1
P2.1 2 19 P0.0
P5.6/XOUT 3 18 P5.0
XIN 4 17 P5.1
VSS 5 16 P5.3/BZ1/PWM1
P4.5/AIN5 6 15 P5.4/BZ0/PWM0
P4.4/AIN4 7 14 P0.3/RST/VPP
P4.3/AIN3 8 13 VDD
P4.2/AIN2 9 12 AVREFH
P4.1/AIN1 10 11 P4.0/AIN0
SN8P27143P
SN8P27143S
SN8P27143X
¾Note: For SN8P27143 and SN8P27142 must configure P02R (bit 2 of P0UR) as “1” to avoid sleep mode
fail.
¾Note: The ADC reference voltage (AVREFH) of SN8P27142/SN8P27143 is VDD.

SN8P2714X_2715
8-bit micro-controller build-in 12-bit ADC
SONiX TECHNOLOGY CO., LTD Page12 V1.4
1.3.3 SN8P2714K Pin Assignment
P5.3/BZ1/PWM1 1 U 28 P5.4/BZ0/PWM0
P5.2 2 27 DAC
P5.1 3 26 P0.3/RST/VPP
P5.0 4 25 VDD
P0.0/INT0 5 24 AVREFH
P0.1/INT1 6 23 P4.0/AIN0
P0.2 7 22 P4.1/AIN1
P2.0 8 21 P4.2/AIN2
P2.1 9 20 P4.3/AIN3
P2.2 10 19 P4.4/AIN4
P2.3 11 18 P4.5/AIN5
P2.4 12 17 P4.6/AIN6
P5.6/XOUT 13 16 P4.7/AIN7
XIN 14 15 VSS
SN8P2714K
SN8P2714S
1.3.4 SN8P2715P Pin Assignment
P5.5 1 U 32 DAO
P5.4/BZ0/PWM0 2 31 P0.3/RST/VPP
P5.3/BZ1/PWM1 3 30 VDD
P5.2 4 29 AVREFH
P5.1 5 28 P4.0/AIN0
P5.0 6 27 P4.1/AIN1
P0.0/INT0 7 26 P4.2/AIN2
P0.1/INT1 8 25 P4.3/AIN3
P0.2 9 24 P4.4/AIN4
P2.0 10 23 P4.5/AIN5
P2.1 11 22 P4.6/AIN6
P2.2 12 21 P4.7/AIN7
P2.3 13 20 VSS
P2.4 14 19 XIN
P2.5 15 18 P5.6/XOUT
P2.6 16 17 P2.7
SN8P2715P
SN8P2715S

SN8P2714X_2715
8-bit micro-controller build-in 12-bit ADC
SONiX TECHNOLOGY CO., LTD Page13 V1.4
1.4 PIN DESCRIPTIONS
PIN NAME TYPE DESCRIPTION
P0 [1:0] / INT [1:0] I P0 [1:0]: Input only pin/ wakeup/pull-up/Schmitt trigger input
INT [1:0]: External interrupt
P0 .2 I P0.2: Input only pin/wake up/pull-up/Schmitt trigger input
P2 [7:0] I/O P2 [7:0] bi-direction pins/pull-up/Schmitt trigger input
P4 [7:0] / AIN [7:0] I/O Bi-direction pins/pull-up /ADC input/ without Schmitt trigger input
P5 [5:0] I/O Bi-direction pins/pull-up/Schmitt trigger input
P5.4: PWM0/BZ0, P5.3: PWM1/BZ1
AVREFH I ADC highest reference voltage input
(NOTE :The ADC reference voltage (AVREFH) of SN8P27142 and SN8P27143 are
VDD.)
DAO O Current type DAC output
P0.3/RST/VPP I/P P0.3: Schmitt trigger input pin / NO pull-up, NO wakeup/ in RC mode
P0.3 is input only pin without pull-up resistor under P0.3 mode. Add the 100 ohm
external resistor on P0.3, when it is set to be input pin.
RST: External reset, active “low”
VPP: OTP programming pin
XIN I External oscillator input pin. / External RC oscillator input
XOUT/P5.6 I/O XOUT: External oscillator output pin.
P5.6: Bi-direction pin/pull-up/Schmitt trigger input in RC mode
VDD, VSS P Power supply pins.
Table 1-1. SN8P2714/15 Pin Description

SN8P2714X_2715
8-bit micro-controller build-in 12-bit ADC
SONiX TECHNOLOGY CO., LTD Page14 V1.4
1.5 PIN CIRCUIT DIAGRAMS
Port 0.1 and P0.2 structure:
Pin
Int. Bus
Int. Rst
Pull-Up
PnUR
Port 0.3 structure:
Pin
Ext. Reset
Code Option
Int. Bus
Int. Rst
Port 2, 5 structure:
Pull-Up
Pin
Output
Latch
PnM, PnUR
Input Bus
PnM
Output Bus
Port 4 structure:
GCHS
Int. ADC
P4CON
Pull-Up
Output
Latch
PnM, PnUR
Input Bus
PnM
Output Bus
Pin
Figure 1-2. Pin Circuit Diagram

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2 CODE OPTION TABLE
Code Option Content Function Description
Ext_RC Low cost external RC oscillator for high clock oscillator.
Output the Fcpu clock from Xout pin.
12M_X’tal High speed crystal /resonator (e.g. 12MHz ~ 16MHz) for high clock oscillator.
High_Clk
4M_X’tal Middle speed crystal /resonator (e.g. 4MHz ~ 10Mhz) for high clock oscillator.
Enable Enable Noise Filter and the Fcpu is Fosc/4~Fosc/8.
Noise_Filter Disable Disable Noise Filter and the Fcpu is Fosc/1~Fosc/8.
Always_On Watchdog timer always on even in sleep (power down) mode.
Enable Normal mode: Enable Watchdog timer
Sleep mode: Stop Watchdog timer Stop
Watch_Dog
Disable Disable Watchdog function.
Fosc/1 Instruction cycle is oscillator clock.
Notice: In Fosc/1, Noise Filter must be disabled.
Fosc/2 Instruction cycle is 2 oscillator clocks.
Notice: In Fosc/2, Noise Filter must be disabled.
Fosc/4 Instruction cycle is 4 oscillator clocks.
Fcpu
Fosc/8 Instruction cycle is 8 oscillator clocks.
Enable Enable ROM code Security function.
Security Disable Disable ROM code Security function.
Reset Enable external reset pin
RST_P0.3 P0.3 Enable P0.3 input only pin without pull-up register
LVD_L LVD will reset chip if VDD is below 2.0V
LVD_M LVD will reset chip if VDD is below 2.0V
Enable LVD24 bit of PFLAG register for 2.4V low voltage indicator.
LVD
LVD_H LVD will reset chip if VDD is below 2.4V
Enable LVD36 bit of PFLAG register for 3.6V low voltage indicator.
Table 2-1. Code Option Table of SN8P2714x/2715
Notice:
¾In high noisy environment, enable “Noise Filter” and set Watch_Dog as “Always_On” is
strongly recommended.
¾Enable “Noise Filter” will limit the Fcpu = Fosc/4 or Fosc/8
¾Fcpu code option is only available for High Clock
¾Fosc = Fhosc (External high clock) in normal mode.
¾Fosc = Flosc (Internal low RC clock) in slow mode.
¾In slow mode, Fcpu = Fosc / 4.

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3 ADDRESS SPACES
3.1 PROGRAM MEMORY (ROM)
3.1.1 OVERVIEW
ROM Maps for SN8P2710 devices provide 2K X 16-bit OTP programmable memory. The SN8P2710 program memory
is able to fetch instructions through 12-bit wide PC (Program Counter) and can look up ROM data by using ROM code
registers (R, X, Y, Z). In standard configuration, the device’s 2,048 x 16-bit program memory has four areas:
¾1-word reset vector addresses
¾1-word Interrupt vector addresses
¾4-words reserved area
¾2K words
All of the program memory is partitioned into three coding areas. The 1st area is located from 00H to 07H(The Reset
vector area), the 2nd area is for the interrupt vector (0008H) and the 3ed area is user code area from 0009H to 07FBH.
ROM
0000H Reset vector User reset vector
0001H Jump to user start address
0002H Jump to user start address
0003H Jump to user start address
0004H Jump to user start address
0005H Jump to user start address
0006H Jump to user start address
0007H
General purpose area
Jump to user start address
0008H Interrupt vector User interrupt vector
0009H User program
.
.
000FH
0010H
0011H
.
.
07FBH
General purpose area
End of user program
07FCH
.
07FFH
Code Option
Figure 3-1 ROM Address Structure

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3.1.2 USER RESET VECTOR ADDRESS (0000H)
A 1-word vector address area is used to execute system reset. After power on reset or watchdog timer overflow reset,
then the chip will restart the program from address 0000h and all system registers will be set as default values. The
following example shows the way to define the reset vector in the program memory.
ÂExample: After power on reset, external reset active or reset by watchdog timer overflow.
ORG 0 ; 0000H
JMP START ; Jump to user program address.
. ;
ORG 10H
START: ; 0010H, The head of user program.
. ; User program
.
.
.
ENDP ; End of program
3.1.3 INTERRUPT VECTOR ADDRESS (0008H)
A 1-word vector address area is used to execute interrupt request. If any interrupt service is executed, the program
counter (PC) value is stored in stack buffer and points to 0008h of program memory to execute the vectored interrupt.
Users have to define the interrupt vector and the following example shows the way to define the interrupt vector in the
program memory.
ÂExample 1: This demo program includes interrupt service routine and the user program is behind the
interrupt service routine.
ORG 0 ; 0000H
JMP START ; Jump to user program address.
.
ORG 8 ; Interrupt service routine
B0XCH A, ACCBUF ; B0XCH doesn’t change C, Z flag
B0MOV A, PFLAG
B0MOV PFLAGBUF, A ; Save PFLAG register in a buffer
. ; User code
. ; User code
B0MOV A, PFLAGBUF
B0MOV PFLAG, A ; Restore PFLAG register from buffer
B0XCH A, ACCBUF
RETI ; End of interrupt service routine
START: ; The head of user program.
. ; User program
.
.
JMP START ; End of user program
ENDP ; End of program

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ÂExample 2: The demo program includes interrupt service routine and the address of interrupt service
routine is in a special address of general-purpose area.
ORG 0 ; 0000H
JMP START ; Jump to user program address.
. ; 0001H ~ 0007H are reserved
ORG 08
JMP MY_IRQ ; 0008H, Jump to interrupt service routine address
ORG 10H
START: ; 0010H, The head of user program.
. ; User program
.
.
.
JMP START ; End of user program
MY_IRQ: ;The head of interrupt service routine
B0XCH A, ACCBUF ; B0XCH doesn’t change C, Z flag
B0MOV A, PFLAG
B0MOV PFLAGBUF, A ; Save PFLAG register in a buffer
. ; User code
. ; User code
B0MOV A, PFLAGBUF
B0MOV PFLAG, A ; Restore PFLAG register from buffer
RETI ; End of interrupt service routine
ENDP ; End of program
¾Note: It is easy to get the rules of SONIX program from demo programs given above. These points are as
following.
1.The address 0000H is a “JMP” instruction to make the program go to general-purpose ROM area.
2. The interrupt service starts from 0008H. Users can put the whole interrupt service routine from 0008H
(Example1) or to put a “JMP” instruction in 0008H then place the interrupt service routine in other
general-purpose ROM area (Example2) to get more modularized coding style.

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3.1.4 GENERAL PURPOSE PROGRAM MEMORY AREA
The ROM locations 0001H~0007H and 0009H~07FBH are used as general-purpose memory. The area is stored
instruction’s op-code and look-up table data. The SN8P2710 includes jump table function by using program counter
(PC) and look-up table function by using ROM code registers (R, Y, Z).
The boundary of program memory is separated by the high-byte program counter (PCH) every 100H. In jump table
function and look-up table function, the program counter can’t leap over the boundary by program counter
automatically. Users need to modify the PCH value to “PCH+1” as the PCL overflow (from 0FFH to 000H).
3.1.5 LOOKUP TABLE DESCRIPTION
In the ROM’s data lookup function, Y register to the highest 8-bit and Z register to the lowest 8-bit data of ROM
address. After MOVC instruction is executed, the low-byte data of ROM then will be stored in ACC and high-byte data
stored in R register.
ÂExample: To look up the ROM data located “TABLE1”.
B0MOV Y, #TABLE1$M ; To set lookup table1’s middle address
B0MOV Z, #TABLE1$L ; To set lookup table1’s low address.
MOVC ; To lookup data, R = 00H, ACC = 35H
;
; Increment the index address for next address
INCMS Z ; Z+1
JMP @F ; Not overflow
INCMS Y ; Z overflow (FFH Æ00), ÆY=Y+1
NOP ; Not overflow
;
@@: MOVC ; To lookup data, R = 51H, ACC = 05H.
. . ;
TABLE1: DW 0035H ; To define a word (16 bits) data.
DW 5105H ; “
DW 2012H ; “
¾CAUSION: The Y register can’t increase automatically if Z register cross boundary from 0xFF to 0x00.
Therefore, user must take care such situation to avoid loop-up table errors. If Z register overflow, Y
register must be added one. The following INC_YZ macro shows a simple method to process Y and Z
registers automatically.
¾Note: Because the program counter (PC) is only 12-bit, the X register is useless in the application. Users
can omit “B0MOV X, #TABLE1$H”. SONiX ICE support more larger program memory addressing
capability. So make sure X register is “0” to avoid unpredicted error in loop-up table operation.
ÂExample: INC_YZ Macro
INC_YZ MACRO
INCMS Z ; Z+1
JMP @F ; Not overflow
INCMS Y ; Y+1
NOP ; Not overflow
@@:
ENDM

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The other coding style of loop-up table is to add Y or Z index register by accumulator. Be careful if carry happen. Refer
following example for detailed information:
ÂExample: Increase Y and Z register by B0ADD/ADD instruction
B0MOV Y, #TABLE1$M ; To set lookup table’s middle address.
B0MOV Z, #TABLE1$L ; To set lookup table’s low address.
B0MOV A, BUF ; Z = Z + BUF.
B0ADD Z, A
B0BTS1 FC ; Check the carry flag.
JMP GETDATA ; FC = 0
INCMS Y ; FC = 1. Y+1.
NOP
GETDATA: ;
MOVC ; To lookup data. If BUF = 0, data is 0x0035
; If BUF = 1, data is 0x5105
; If BUF = 2, data is 0x2012
.
.
. . ;
TABLE1: DW 0035H ; To define a word (16 bits) data.
DW 5105H ; “
DW 2012H ; “