Infineon XC800 Series User manual

User’s Manual, V 1.3, Feb. 2007
Microcontrollers
XC866
8-Bit Single Chip Microcontroller

Edition 2007-02
Published by Infineon Technologies AG,
81726 München, Germany
©Infineon Technologies AG 2007.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.

User’s Manual, V 1.3, Feb. 2007
Microcontrollers
XC866
8-Bit Single Chip Microcontroller

3-1
XC866
Revision History: V 1.3, 2007-02
Previous Version: V1.0, 2005-10
V1.1, 2005-12
V1.2, 2006-06
Page Subjects (major changes since last revision)
1-2 Device temperature range is updated, see Table 1-1.
1-2 Device variants are updated, see Table 1-3.
1-13 The hint for using MBC pin is added.
7-12 When the external oscillator is used, the on-chip oscillator can be powered
down.
10-13 Table 10-3 is updated for the generation of 115.2 KHz baud rate.
14-6 NMI mode priority is over debug mode, see Section 14.2.1.4.
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
[email protected]

XC866
Table of Contents Page
User’s Manual I-1 V 1.3, 2007-02
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1 Feature Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.3 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.4 Textual Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
1.5 Reserved, Undefined and Unimplemented Terminology . . . . . . . . . . . . 1-15
1.6 Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
2 Processor Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 CPU Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.2.1 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.2.2 Data Pointer (DPTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.2.3 Accumulator (ACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.2.4 B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.2.5 Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2.2.6 Extended Operation Register (EO) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
2.2.7 Power Control Register (PCON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
2.3 Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
3 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.2 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.2.1 Internal Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.2.2 External Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.3 Memory Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.3.1 Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.3.2 Flash Protection Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.4 Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.4.1 Address Extension by Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.4.2 Address Extension by Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.4.3 Bit-Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
3.4.4 System Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
3.4.4.1 Bit Protection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
3.4.5 XC866 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
3.4.5.1 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
3.4.5.2 System Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
3.4.5.3 WDT Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
3.4.5.4 Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
3.4.5.5 ADC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23
3.4.5.6 Timer 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
3.4.5.7 CCU6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
3.4.5.8 SSC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30

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3.4.5.9 OCDS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31
3.5 Boot ROM Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32
3.5.1 User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32
3.5.2 BootStrap Loader Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32
3.5.3 OCDS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32
3.5.4 User JTAG Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32
4 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1 Flash Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2 Flash Bank Sectorization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.3 Wordline Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.4 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
4.5 Error Detection and Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
4.6 In-System Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
4.7 In-Application Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
4.7.1 Flash Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
4.7.2 Flash Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
4.7.3 Aborting Flash Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
4.7.4 Flash Bank Read Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
5 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.1 Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.1.1 Interrupt Structure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.1.2 Interrupt Structure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.2 Interrupt Source and Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5.3 Interrupt Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
5.3.1 Interrupt Node Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
5.3.2 External Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
5.3.3 Interrupt Flag Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
5.3.4 Interrupt Priority Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24
5.3.5 Interrupt Flag Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27
5.4 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28
5.5 Interrupt Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
6 Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.1 General Port Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
6.1.1 General Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
6.1.1.1 Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
6.1.1.2 Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
6.1.1.3 Open Drain Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
6.1.1.4 Pull-Up/Pull-Down Device Register . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
6.1.1.5 Alternate Input Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11
6.1.1.6 Alternate Output Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11

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6.2 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
6.3 Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
6.3.1 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
6.3.2 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
6.4 Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
6.4.1 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
6.4.2 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
6.5 Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26
6.5.1 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26
6.5.2 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29
6.6 Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31
6.6.1 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31
6.6.2 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34
7 Power Supply, Reset and Clock Management . . . . . . . . . . . . . . . . . . 7-1
7.1 Power Supply System with Embedded Voltage Regulator . . . . . . . . . . . 7-1
7.2 Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7.2.1 Types of Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7.2.1.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3
7.2.1.2 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
7.2.1.3 Watchdog Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
7.2.1.4 Power-Down Wake-Up Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
7.2.1.5 Brownout Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
7.2.2 Module Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
7.2.3 Booting Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
7.2.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
7.3 Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7.3.1 Clock Generation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7.3.1.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
7.3.2 Clock Source Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
7.3.3 Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
7.3.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
8 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
8.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.1.1 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.1.2 Slow-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
8.1.3 Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
8.1.4 Peripheral Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
8.2 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
9 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
9.2 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5

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9.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5
10 Serial Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
10.1 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.1.1 UART Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
10.1.1.1 Mode 0, 8-Bit Shift Register, Fixed Baud Rate . . . . . . . . . . . . . . . 10-2
10.1.1.2 Mode 1, 8-Bit UART, Variable Baud Rate . . . . . . . . . . . . . . . . . . . 10-3
10.1.1.3 Mode 2, 9-Bit UART, Fixed Baud Rate . . . . . . . . . . . . . . . . . . . . . 10-5
10.1.1.4 Mode 3, 9-Bit UART, Variable Baud Rate . . . . . . . . . . . . . . . . . . . 10-5
10.1.2 Multiprocessor Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
10.1.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
10.1.4 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
10.1.4.1 Fixed Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
10.1.4.2 Dedicated Baud-rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
10.1.4.3 Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21
10.1.5 Interfaces of UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-22
10.2 LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23
10.2.1 LIN Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-23
10.2.2 LIN Header Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25
10.2.2.1 Automatic Synchronization to the Host . . . . . . . . . . . . . . . . . . . . 10-25
10.2.2.2 Baud Rate Detection of LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-25
10.3 High-Speed Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . 10-28
10.3.1 General Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-29
10.3.1.1 Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-29
10.3.1.2 Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30
10.3.1.3 Half-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-33
10.3.1.4 Continuous Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-34
10.3.1.5 Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-34
10.3.1.6 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-35
10.3.1.7 Error Detection Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-36
10.3.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-39
10.3.3 Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-39
10.3.4 Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-41
10.3.5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-42
10.3.5.1 Port Input Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-42
10.3.5.2 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-43
10.3.5.3 Baud Rate Timer Reload Register . . . . . . . . . . . . . . . . . . . . . . . . 10-47
10.3.5.4 Transmit and Receive Buffer Register . . . . . . . . . . . . . . . . . . . . . 10-48
11 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.1 Timer 0 and Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.1.1 Basic Timer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11.1.2 Timer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2

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11.1.2.1 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
11.1.2.2 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
11.1.2.3 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
11.1.2.4 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
11.1.3 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7
11.1.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
11.2 Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
11.2.1 Auto-Reload Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
11.2.1.1 Up/Down Count Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13
11.2.1.2 Up/Down Count Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14
11.2.2 Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-16
11.2.3 External Interrupt Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18
11.2.4 Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18
11.2.5 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19
11.2.6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19
12 Capture/Compare Unit 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1
12.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.1.1 Timer T12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
12.1.1.1 Timer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
12.1.1.2 Counting Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
12.1.1.3 Switching Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4
12.1.1.4 Compare Mode of T12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6
12.1.1.5 Duty Cycle of 0% and 100% . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
12.1.1.6 Dead-time Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
12.1.1.7 Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9
12.1.1.8 Single-Shot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
12.1.1.9 Hysteresis-Like Control Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
12.1.2 Timer T13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12
12.1.2.1 Timer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12
12.1.2.2 Compare Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13
12.1.2.3 Single-Shot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13
12.1.2.4 Synchronization of T13 to T12 . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14
12.1.3 Modulation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14
12.1.4 Trap Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-17
12.1.5 Multi-Channel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-18
12.1.6 Hall Sensor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20
12.1.6.1 Sampling of the Hall Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-20
12.1.6.2 Brushless-DC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21
12.1.7 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-24
12.1.8 Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-24
12.1.9 Port Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-25
12.2 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-28

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12.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-31
12.3.1 System Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-33
12.3.1.1 Port Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-33
12.3.2 Timer T12 – Related Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-37
12.3.3 Timer T13 – Related Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-43
12.3.4 Capture/Compare Control Registers . . . . . . . . . . . . . . . . . . . . . . . 12-47
12.3.5 Modulation Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-59
12.3.5.1 Global Module Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-59
12.3.5.2 Multi-Channel Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-67
12.3.6 Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-79
13 Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
13.1 Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
13.2 Clocking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
13.2.1 Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
13.3 Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7
13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
13.4.1 Request Source Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
13.4.2 Conversion Start Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
13.4.3 Channel Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10
13.4.4 Sequential Request Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
13.4.4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
13.4.4.2 Request Source Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12
13.4.5 Parallel Request Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13
13.4.5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13
13.4.5.2 Request Source Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13
13.4.5.3 External Trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14
13.4.5.4 Software Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14
13.4.5.5 Autoscan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15
13.4.6 Wait-for-Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15
13.4.7 Result Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16
13.4.7.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-16
13.4.7.2 Limit Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17
13.4.7.3 Data Reduction Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18
13.4.7.4 Result Register View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19
13.4.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-21
13.4.8.1 Event Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-22
13.4.8.2 Channel Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-23
13.4.9 External Trigger Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-25
13.5 ADC Module Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 13-26
13.6 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-28
13.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-31
13.7.1 General Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-31

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13.7.2 Priority and Arbitration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-33
13.7.3 External Trigger Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . 13-35
13.7.4 Channel Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-36
13.7.5 Input Class Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-37
13.7.6 Sequential Source Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-38
13.7.7 Parallel Source Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-44
13.7.8 Result Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-48
13.7.9 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-52
14 On-Chip Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
14.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
14.2 Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
14.2.1 Debug Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3
14.2.1.1 Hardware Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
14.2.1.2 Software Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5
14.2.1.3 External Breaks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
14.2.1.4 NMI-mode priority over Debug-mode . . . . . . . . . . . . . . . . . . . . . . 14-6
14.2.2 Debug Actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
14.2.2.1 Call the Monitor Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
14.2.2.2 Activate the MBC pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7
14.3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7
14.3.1 JTAG ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
14.3.2 Input Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10
15 Bootstrap Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1
15.1 Communication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2
15.1.1 UART Transfer Block Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2
15.1.2 LIN Transfer Block Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
15.1.3 Response Code to the Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
15.2 Bootstrap Loader via UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
15.2.1 Communication Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
15.2.2 The Selection of Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6
15.2.2.1 The Activation of Modes 0 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7
15.2.2.2 The Activation of Modes 1, 3 and F . . . . . . . . . . . . . . . . . . . . . . . . 15-8
15.2.2.3 The Activation of Mode 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9
15.2.2.4 The Activation of Mode 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10
15.3 Bootstrap Loader via LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12
15.3.1 Communication Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13
15.3.2 The Selection of Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16
15.3.2.1 The Activation of Modes 0, 2 and 8 . . . . . . . . . . . . . . . . . . . . . . . 15-16
15.3.2.2 The Activation of Modes 1, 3 and 9 . . . . . . . . . . . . . . . . . . . . . . . 15-18
15.3.2.3 The Activation of Mode 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-19
15.3.2.4 The Activation of Mode 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-19

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15.3.3 LIN Response Protocol to the Host . . . . . . . . . . . . . . . . . . . . . . . . . 15-19
15.3.4 Fast LIN BSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-20
15.3.5 After-Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-21
15.3.6 User Defined Parameters for LIN BSL . . . . . . . . . . . . . . . . . . . . . . . 15-23
16 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
16.1 Keyword Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1
16.2 Register Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6

XC866
Introduction
User’s Manual 1-1 V 1.3, 2007-02
Intro, V 1.3
1 Introduction
The XC866 is a member of the high-performance XC800 family of 8-bit microcontrollers.
It is based on the XC800 Core that is compatible with the industry standard 8051
processor. The XC866 features a great number of enhancements to enable new
application technologies through its highly integrated on-chip components, such as
on-chip oscillator or an integrated voltage regulator, allowing a single voltage supply of
3.3 or 5.0 V. In addition, the XC866 is equipped with either embedded Flash memory to
offer high flexibility in development and ramp-up, or compatible ROM versions to provide
cost-saving potential in high-volume production. The XC866 memory protection strategy
features read-out protection of user intellectual property (IP), along with Flash program
and erase protection to prevent data corruption.
The multi-bank Flash architecture supports In-Application Programming (IAP), allowing
user program to run from one bank, while programming or erasing another bank.
In-System Programming (ISP) is available through the Boot ROM-based BootStrap
Loader (BSL), enabling convenient programming and erasing of the embedded Flash via
an external host (e.g., personal computer).
Other key features of the XC866 include a Capture/Compare Unit 6 (CCU6) for the
generation of pulse width modulated signal with special modes for motor control, and a
10-bit Analog-to-Digital Converter (ADC) with extended functionalities like autoscan and
result accumulation for anti-aliasing filtering or for averaging. Local Interconnect Network
(LIN) applications are also supported through extended UART features and the provision
of LIN low level drivers for most devices. For low power applications, various power
saving modes are available for selection by the user. Control of the numerous on-chip
peripheral functionalities is achieved by extending the Special Function Register (SFR)
address range with an intelligent paging mechanism optimized for interrupt handling.
Figure 1-1 shows the functional units of the XC866.
Figure 1-1 XC866 Functional Units
Port 0
Port 1
Port 2
Port 3
XC800 Core
UART
ADC
10-bit
8-channel
Boot ROM
8K Bytes
XRAM
512 Bytes
RAM
256 Bytes
On-Chip Debug Support
Timer 0
16-bit
Timer 1
16-bit
Timer 2
16-bit
Watchdog
Timer
SSC
4K/ 8K/16K Bytes Flash
or 8K/16K Bytes ROM
1)
Capture/Compare Unit
16-bit
Compare Unit
16-bit
6-bit Digital I/O
5-bit Digital I/O
8-bit Digital I/O
8-bit Digital/Analog Input
1) All ROM devices include 4K bytes Flash

XC866
Introduction
User’s Manual 1-2 V 1.3, 2007-02
Intro, V 1.3
The XC866 product family features devices with different configurations and program
memory sizes, temperature and quality profiles (Automotive or Industrial), offering cost-
effective solution for different application requirements.
The configuration of temperature range (TA)for XC866 devices are summarized in
Table 1-1 and the configuration of LIN BSL for XC866 devices are summarized in
Table 1-2.
The list of XC866 devices and their differences are summarized in Table 1-3.
Table 1-1 Device Configuration for Temperature Range
Device Name Temperature Range TA
SAF -40 to 85 °C
SAK -40 to 125 °C
SAA -40 to 140 °C
Table 1-2 Device Configuration for LIN BSL
Device Name LIN BSL Support
XC866 No
XC866L Yes
Table 1-3 Device Summary
Device
Type
Device Name Power
Supply
(V)
P-Flash
Size
(Kbytes)
D-Flash
Size
(Kbytes)
ROM
Size
(Kbytes)
Quality
Profile1)
Flash2) SAA-XC866*-4FRA 5.0 12 4 – Automotive
SAA-XC866*-2FRA 5.0 4 4 – Automotive
SAA-XC866*-1FRA 5.0/3.3 – 4 – Automotive
SAK-XC866*-4FRA 5.0 12 4 – Automotive
SAK-XC866*-4FRI 5.0 12 4 – Industrial
SAK-XC866*-2FRA 5.0 4 4 – Automotive
SAK-XC866*-2FRI 5.0 4 4 – Industrial
SAK-XC866*-1FRA 5.0/3.3 – 4 – Automotive
SAK-XC866*-1FRI 5.0/3.3 – 4 – Industrial
SAF-XC866*-4FRA 5.0 12 4 – Automotive
SAF-XC866*-4FRI 5.0 12 4 – Industrial
SAF-XC866*-2FRA 5.0 4 4 – Automotive

XC866
Introduction
User’s Manual 1-3 V 1.3, 2007-02
Intro, V 1.3
Note: The asterisk (*) above denotes the device configuration letters from Table 1-2.
For XC866-4RR ROM device, different configurations of memory can be used which
must meet the following conditions:
• ROM size is (12 + X) KBytes and D-Flash size is (4 - X ) KBytes.
SAF-XC866*-2FRI 5.0 4 4 – Industrial
SAF-XC866*-1FRA 5.0/3.3 – 4 – Automotive
SAF-XC866*-1FRI 5.0/3.3 – 4 – Industrial
SAA-XC866*-4FRA 3V 3.3 12 4 – Automotive
SAA-XC866*-2FRA 3V 3.3 4 4 – Automotive
SAK-XC866*-4FRA 3V 3.3 12 4 – Automotive
SAK-XC866*-4FRI 3V 3.3 12 4 – Industrial
SAK-XC866*-2FRA 3V 3.3 4 4 – Automotive
SAK-XC866*-2FRI 3V 3.3 4 4 – Industrial
SAF-XC866*-4FRA 3V 3.3 12 4 – Automotive
SAF-XC866*-4FRI 3V 3.3 12 4 – Industrial
SAF-XC866*-2FRA 3V 3.3 4 4 – Automotive
SAF-XC866*-2FRI 3V 3.3 4 4 – Industrial
ROM SAA-XC866*-4RRA 5.0/3.3 – 4 16 Automotive
SAA-XC866*-2RRA 5.0/3.3 – 4 8 Automotive
SAK-XC866*-4RRA 5.0/3.3 – 4 16 Automotive
SAK-XC866*-4RRI 5.0/3.3 – 4 16 Industrial
SAK-XC866*-2RRA 5.0/3.3 – 4 8 Automotive
SAK-XC866*-2RRI 5.0/3.3 – 4 8 Industrial
SAF-XC866*-4RRA 5.0/3.3 – 4 16 Automotive
SAF-XC866*-4RRI 5.0/3.3 – 4 16 Industrial
SAF-XC866*-2RRA 5.0/3.3 – 4 8 Automotive
SAF-XC866*-2RRI 5.0/3.3 – 4 8 Industrial
1) Industrial is not for Automotive usage
2) The flash memory (P-Flash and D-Flash) can be used for code or data.
Table 1-3 Device Summary
Device
Type
Device Name Power
Supply
(V)
P-Flash
Size
(Kbytes)
D-Flash
Size
(Kbytes)
ROM
Size
(Kbytes)
Quality
Profile1)

XC866
Introduction
User’s Manual 1-4 V 1.3, 2007-02
Intro, V 1.3
• X is aligned based on D-Flash sectors arrangement.
• ROM size must be linearly overmapping D-Flash range bottom up.
The memory configurations of XC866-4RR ROM device are summarized in Table 1-4.
The term “XC866” in this document refers to all devices of the XC866 family unless
otherwise stated.
Table 1-4 Memory Configurations of XC866-4RR ROM device
Configuration Type ROM Size D-Flash Size
1 16 Kbytes 0 Kbyte
2 15.875 Kbytes 0.125 Kbytes
3 15.75 Kbytes 0.25 Kbytes
4 15.625 Kbytes 0.375 Kbytes
5 15.5 Kbytes 0.5 Kbytes
6 15.25 Kbytes 0.75 Kbytes
7 15 Kbytes 1 Kbytes
8 14.5 Kbytes 1.5 Kbytes
914Kbytes2Kbytes
10 13 Kbytes 3 Kbytes
11 12 Kbytes 4 Kbytes

XC866
Introduction
User’s Manual 1-5 V 1.3, 2007-02
Intro, V 1.3
1.1 Feature Summary
The following list summarizes the main features of the XC866:
• High-performance XC800 Core
– compatible with standard 8051 processor
– two clocks per machine cycle architecture (for memory access without wait state)
– two data pointers
• On-chip memory
– 8 Kbytes of Boot ROM
– 256 bytes of RAM
– 512 bytes of XRAM
– 4/8/16 Kbytes of Flash; or
8/16 Kbytes of ROM, with additional 4 Kbytes of Flash
(includes memory protection strategy)
• I/O port supply at 3.3 or 5.0 V and core logic supply at 2.5 V (generated by embedded
voltage regulator)
• Reset generation
– Power-On reset
– Hardware reset
– Brownout reset for core logic supply
– Watchdog timer reset
– Power-Down Wake-up reset
• On-chip OSC and PLL for clock generation
– PLL loss-of-lock detection
• Power saving modes
– slow-down mode
– idle mode
– power-down mode with wake-up capability via RXD or EXINT0
– clock gating control to each peripheral
• Programmable 16-bit Watchdog Timer (WDT)
• Four ports
– 19 pins as digital I/O
– 8 pins as digital/analog input
• 8-channel, 10-bit ADC
• Three 16-bit timers
– Timer 0 and Timer 1 (T0 and T1)
–Timer2
• Capture/compare unit for PWM signal generation (CCU6)
• Full-duplex serial interface (UART)
• Synchronous serial channel (SSC)
• On-chip debug support
– 1 Kbyte of monitor ROM (part of the 8-Kbyte Boot ROM)
– 64 bytes of monitor RAM

XC866
Introduction
User’s Manual 1-6 V 1.3, 2007-02
Intro, V 1.3
• PG-TSSOP-38 pin package
• Temperature range TA:
– SAF (-40 to 85 °C)
– SAK (-40 to 125 °C)
– SAA (-40 to 140 °C)
The block diagram of the XC866 is shown in Figure 1-2.
Figure 1-2 XC866 Block Diagram
ADC
Port 0Port 1Port 2Port 3
CCU6
Timer 2
SSC
WDT
OCDS
8-Kbyte
Boot ROM
1)
256-byte RAM
+
64-byte monitor
RAM
512-byte XRAM
4/8/16-Kbyte Flash
or
8/16-Kbyte ROM
2)
XC800 Core
T0 & T1 UART
1) Includes 1-Kbyte monitor ROM
2) Includes additional 4-Kbyte Flash
P0.0 - P0.5
P1.0 - P1.1
P1.5-P1.7
P3.0 - P3.7
P2.0 - P2.7
V
AREF
V
AGND
Clock Generator
10 MHz
On-chip OSC
PLL
XTAL1
XTAL2
Internal Bus
V
DDP
V
SSP
V
DDC
V
SSC
RESET
TMS
MBC
XC866

XC866
Introduction
User’s Manual 1-7 V 1.3, 2007-02
Intro, V 1.3
1.2 Pin Configuration
The pin configuration of the XC866, based on the PG-TSSOP-38 package, is shown in
Figure 1-3.
Figure 1-3 XC866 Pin Configuration, PG-TSSOP-38 Package (top view)
P0.0/TCK_0/T12HR_1/CC61_1/CLKOUT/RXDO_1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
28
27
26
25
24
23
22
21
20
37
36
35
34
33
32
31
30
29
38
XC866
P2.0/CCPOS0_0/EXINT1/T12HR_2/TCK_1/CC61_3/AN0
P0.2/CTRAP_2/TDO_0/TXD_1
P0.3/SCLK_1/COUT63_1
P0.4/MTSR_1/CC62_1
P0.5/MRST_1/EXINT0_0/COUT62_1
P1.0/RXD_0/T2EX
P1.1/EXINT3/TDO_1/TXD_0
P1.5/CCPOS0_1/EXINT5/EXF2_0/RXDO_0
P1.6/CCPOS1_1/T12HR_0/EXINT6
P1.7/CCPOS2_1/T13HR_0
P2.4/AN4
P2.1/CCPOS1_0/EXINT2/T13HR_2/TDI_1/CC62_3/AN1
P2.2/CCPOS2_0/CTRAP_1/CC60_3/AN2
P2.3/AN3
P2.7/AN7
P2.5/AN5
P2.6/AN6
P3.0/CCPOS1_2/CC60_0
P3.1/CCPOS0_2/CC61_2/COUT60_0
P3.2/CCPOS2_2/CC61_0
P3.3/COUT61_0
P3.4/CC62_0
P3.5/COUT62_0
P3.6/CTRAP_0
P3.7/EXINT4/COUT63_0
VDDP
VSSP
VDDC
VSSC
VAREF
VAGND
XTAL1
XTAL2
TMS
RESET
MBC
P0.1/TDI_0/T13HR_1/RXD_1/EXF2_1/COUT61_1

XC866
Introduction
User’s Manual 1-8 V 1.3, 2007-02
Intro, V 1.3
1.3 Pin Definitions and Functions
After reset, all pins are configured as input with one of the following:
• Pull-up device enabled only (PU)
• Pull-down device enabled only (PD)
• High impedance with both pull-up and pull-down devices disabled (Hi-Z)
The functions and default states of the XC866 external pins are provided in Table 1-5.
Table 1-5 Pin Definitions and Functions
Symbol Pin
Number
Type Reset
State
Function
P0 I/O Port 0
Port 0 is a 6-bit bidirectional general purpose I/O
port. It can be used as alternate functions for the
JTAG, CCU6, UART, and the SSC.
P0.0 12 Hi-Z TCK_0 JTAG Clock Input
T12HR_1 CCU6 Timer 12 Hardware Run
Input
CC61_1 Input/Output of Capture/Compare
channel 1
CLKOUT Clock Output
RXDO_1 UART Transmit Data Output
P0.1 14 Hi-Z TDI_0 JTAG Serial Data Input
T13HR_1 CCU6 Timer 13 Hardware Run
Input
RXD_1 UART Receive Data Input
COUT61_1 Output of Capture/Compare
channel 1
EXF2_1 Timer 2 External Flag Output
P0.2 13 PU CTRAP_2 CCU6 Trap Input
TDO_0 JTAG Serial Data Output
TXD_1 UART Transmit Data Output/
Clock Output
P0.3 2 Hi-Z SCK_1 SSC Clock Input/Output
COUT63_1 Output of Capture/Compare
channel 3
P0.4 3 Hi-Z MTSR_1 SSC Master Transmit Output/
Slave Receive Input
CC62_1 Input/Output of Capture/Compare
channel 2