Epson S1C63003 User manual

Rev. 1.1
CMOS 4-BIT SINGLE CHIP MICROCONTROLLER
S1C63003/004/008/016
Technical Manual

©
SEIKO EPSON CORPORATION 2013, All rights reserved.
Notice
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko
Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability
of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and,
further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical prod-
ucts. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation
or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third
party. When exporting the products or technology described in this material, you should comply with the applicable export control
laws and regulations and follow the procedures required by such laws and regulations. You are requested not to use, to resell, to
export and/or to otherwise dispose of the products (and any technical information furnished, if any) for the development and/or
manufacture of weapon of mass destruction or for other military purposes.
All brands or product names mentioned herein are trademarks and/or registered trademarks of their respective companies.
Evaluation board/kit and Development tool important notice
1. This evaluation board/kit or development tool is designed for use for engineering evaluation, demonstration, or development
purposes only. Do not use it for other purpose. It is not intended to meet the requirement of design for finished product.
2. This evaluation board/kit or development tool is intended for use by an electronics engineer, and it is not the product for con-
sumer. The user should use this goods properly and safely. Seiko Epson dose not assume any responsibility and liability of any
kind of damage and/or fire coursed by usage of it. User should cease to use it when any abnormal issue occurs even during
proper and safe use.
3. The part used for this evaluation board/kit or development tool is changed without any notice.

Devices
S1 C 63158 F 0A01
Packing specifications
00 : Besides tape & reel
0A : TCP BL 2 directions
0B : Tape & reel BACK
0C : TCP BR 2 directions
0D : TCP BT 2 directions
0E : TCP BD 2 directions
0F : Tape & reel FRONT
0G : TCP BT 4 directions
0H : TCP BD 4 directions
0J : TCP SL 2 directions
0K : TCP SR 2 directions
0L : Tape & reel LEFT
0M: TCP ST 2 directions
0N : TCP SD 2 directions
0P : TCP ST 4 directions
0Q : TCP SD 4 directions
0R : Tape & reel RIGHT
99 : Specs not fixed
Specification
Package
D: die form; F: QFP, B: BGA
Model number
Model name
C: microcomputer, digital products
Product classification
S1: semiconductor
Development tools
S5U1 C 63000 A1 1
Packing specifications
00: standard packing
Version
1: Version 1
Tool type
Hx : ICE
Ex : EVA board
Px : Peripheral board
Wx: Flash ROM writer for the microcomputer
Xx : ROM writer peripheral board
Cx : C compiler package
Ax : Assembler package
Dx : Utility tool by the model
Qx : Soft simulator
Yx : Writer software
Corresponding model number
63000: common to S1C63 Family
Tool classification
C: microcomputer use
Product classification
S5U1: development tool for semiconductor products
00
00
Configuration of product number
CONFIGURATION OF PRODUCT NUMBER
S1C63003/004/008/016 TECHNICAL MANUAL Seiko Epson Corporation i
(Rev. 1.1)
Configuration of product number

CONTENTS
S1C63003/004/008/016 TECHNICAL MANUAL Seiko Epson Corporation i
(Rev. 1.1)
- Contents -
1 Outline ...........................................................................................................................1-1
1.1 Features ...........................................................................................................................1-1
1.2 Block Diagram..................................................................................................................1-2
1.3 Mask Option .....................................................................................................................1-6
2 Pins and Packages .......................................................................................................2-1
2.1 S1C63016 Pins ................................................................................................................2-1
2.1.1 S1C63016 Pin/Pad Layout Diagrams ................................................................2-1
2.1.2 S1C63016 Pin Description.................................................................................2-4
2.2 S1C63008 Pins ................................................................................................................2-6
2.2.1 S1C63008 Pin/Pad Layout Diagrams ................................................................2-6
2.2.2 S1C63008 Pin Description.................................................................................2-9
2.3 S1C63004 Pins ...............................................................................................................2-11
2.3.1 S1C63004 Pin/Pad Layout Diagrams ...............................................................2-11
2.3.2 S1C63004 Pin Description................................................................................2-15
2.4 S1C63003 Pins ...............................................................................................................2-17
2.4.1 S1C63003 Pin/Pad Layout Diagrams ...............................................................2-17
2.4.2 S1C63003 Pin Description................................................................................2-19
2.5 Package ..........................................................................................................................2-20
2.5.1 Plastic Package.................................................................................................2-20
2.5.2 Ceramic Package for Test Samples ..................................................................2-22
3 CPU and Memory..........................................................................................................3-1
3.1 CPU..................................................................................................................................3-1
3.2 Code Memory Area..........................................................................................................3-1
3.2.1 Code ROM.........................................................................................................3-1
3.3 Data Memory Area...........................................................................................................3-2
3.3.1 RAM...................................................................................................................3-2
3.3.2 Data ROM..........................................................................................................3-3
3.3.3 Display Memory .................................................................................................3-3
3.3.4 I/O Memory........................................................................................................3-4
4 Initial Reset ...................................................................................................................4-1
4.1 Initial Reset Circuit ...........................................................................................................4-1
4.2 Reset Terminal (RESET)..................................................................................................4-1
4.3 Simultaneous High Input to P0x Ports (P00–P03) ...........................................................4-2
4.4 Internal Register at Initial Resetting .................................................................................4-2
4.5 Terminal Settings at Initial Resetting ................................................................................4-3
5 Power Supply ................................................................................................................5-1
5.1 Operating Voltage.............................................................................................................5-1
5.2 Internal Power Supply Circuit...........................................................................................5-1
5.3 Controlling LCD Power Supply.........................................................................................5-3
5.4 Heavy Load Protection Function ......................................................................................5-3
5.5 I/O Memory for Power Supply Circuit ...............................................................................5-4
5.6 Precautions ......................................................................................................................5-5
6 Interrupt Controller.......................................................................................................6-1
6.1 Configuration of Interrupt Controller.................................................................................6-1
6.2 Interrupt Factors...............................................................................................................6-3
6.3 Interrupt Mask ..................................................................................................................6-3

CONTENTS
ii Seiko Epson Corporation S1C63003/004/008/016 TECHNICAL MANUAL
(Rev. 1.1)
6.4 Interrupt Vector.................................................................................................................6-4
6.5 I/O Memory of Interrupt Controller ...................................................................................6-5
6.6 Precautions ......................................................................................................................6-8
7 Oscillation Circuit and Clock Control.........................................................................7-1
7.1 Oscillation Circuit .............................................................................................................7-1
7.1.1 Configuration of Oscillation Circuit.....................................................................7-1
7.1.2 Mask Option.......................................................................................................7-1
7.1.3 OSC1 Oscillation Circuit ....................................................................................7-1
7.1.4 OSC3 Oscillation Circuit ....................................................................................7-2
7.2 Switching the CPU Clock .................................................................................................7-2
7.3 HALT and SLEEP.............................................................................................................7-3
7.4 Control of Peripheral Circuit Clocks .................................................................................7-4
7.5 Clock Output (FOUT) .......................................................................................................7-4
7.6 I/O Memory for Oscillation Circuit/Clock Output Control ..................................................7-5
7.7 Precautions ......................................................................................................................7-6
8 Watchdog Timer ............................................................................................................8-1
8.1 Configuration of Watchdog Timer.....................................................................................8-1
8.2 Interrupt Function .............................................................................................................8-1
8.3 I/O Memory of Watchdog Timer .......................................................................................8-1
8.4 Precautions ......................................................................................................................8-2
9 Clock Timer ..................................................................................................................9-1
9.1 Configuration of Clock Timer............................................................................................9-1
9.2 Controlling Operating Clock .............................................................................................9-1
9.3 Data Read and Hold Function..........................................................................................9-1
9.4 Interrupt Function .............................................................................................................9-2
9.5 I/O Memory of Clock Timer ..............................................................................................9-2
9.6 Precautions ......................................................................................................................9-4
10 Stopwatch Timer........................................................................................................10-1
10.1 Configuration of Stopwatch Timer .................................................................................10-1
10.2 Controlling Operating Clock ..........................................................................................10-1
10.3 Counter and Prescaler ..................................................................................................10-2
10.4 Capture Buffer and Hold Function.................................................................................10-2
10.5 Stopwatch Timer RUN/STOP and Reset.......................................................................10-3
10.6 Direct Input Function and Key Mask [S1C63004/008/016] ...........................................10-3
10.7 Interrupt Function ..........................................................................................................10-6
10.8 I/O Memory of Stopwatch Timer....................................................................................10-7
10.9 Precautions ..................................................................................................................10-10
11 Programmable Timer .................................................................................................11-1
11.1 Configuration of Programmable Timer ..........................................................................11-1
11.2 Controlling Operating Clock ..........................................................................................11-3
11.3 Basic Counter Operation...............................................................................................11-4
11.4 Event Counter Mode (Timers 0 and 2)..........................................................................11-4
11.5 PWM mode (Timers 0–3) [S1C63004/008/016] ............................................................11-5
11.6 16-bit timer mode (Timer 0 + 1, Timer 2 + 3) [S1C63004/008/016] ..............................11-6
11.7 Interrupt Function ..........................................................................................................11-7
11.8 TOUT Output Control ....................................................................................................11-7

CONTENTS
S1C63003/004/008/016 TECHNICAL MANUAL Seiko Epson Corporation iii
(Rev. 1.1)
11.9 Clock Output to Serial Interface and R/F Converter [S1C63004/008/016]....................11-8
11.10 I/O Memory of Programmable Timer...........................................................................11-8
11.11 Precautions ................................................................................................................11-14
12 I/O Ports .....................................................................................................................12-1
12.1 Configuration of I/O Ports..............................................................................................12-1
12.2 Mask Option ..................................................................................................................12-2
12.3 I/O Control Registers and Input/Output Mode...............................................................12-3
12.4 Input Interface Level......................................................................................................12-3
12.5 Pull-down During Input Mode........................................................................................12-3
12.6 Key Input Interrupt Function ..........................................................................................12-3
12.7 I/O memory of I/O ports ................................................................................................12-5
12.8 Precautions ...................................................................................................................12-9
13 Serial Interface [S1C63004/008/016] .....................................................13-1
13.1 Configuration of Serial Interface....................................................................................13-1
13.2 Serial Interface Terminals..............................................................................................13-1
13.3 Mask Option ..................................................................................................................13-2
13.4 Operating Mode of Serial Interface ...............................................................................13-2
13.5 Setting Synchronous Clock ...........................................................................................13-4
13.5.1 Selecting Source Clock...................................................................................13-4
13.5.2 Selecting Synchronous Clock Format.............................................................13-4
13.6 Data Input/Output and Interrupt Function......................................................................13-5
13.6.1 Serial Data Output Procedure and Interrupt ...................................................13-5
13.6.2 Serial Data Input Procedure and Interrupt......................................................13-5
13.6.3 Serial Data Input/Output Permutation .............................................................13-6
13.6.4 SRDY Signal ...................................................................................................13-6
13.6.5 Timing Chart ...................................................................................................13-6
13.7 Data Transfer in SPI Mode ............................................................................................13-8
13.8 I/O Memory of Serial Interface ......................................................................................13-9
13.9 Precautions ..................................................................................................................13-12
14 LCD Driver..................................................................................................................14-1
14.1 Configuration of LCD Driver ..........................................................................................14-1
14.2 Mask Option ..................................................................................................................14-1
14.2.1 SEG/GPIO/RFC Terminal Configuration ........................................................14-1
14.2.2 Power Source for LCD Driving ........................................................................14-2
14.2.3 Segment Option..............................................................................................14-2
14.3 LCD Display Control......................................................................................................14-7
14.3.1 Selecting Display Mode ..................................................................................14-7
14.3.2 Switching Drive Duty.......................................................................................14-7
14.3.3 Switching Frame Frequency ...........................................................................14-7
14.3.4 Drive Waveform...............................................................................................14-8
14.3.5 Static Drive.....................................................................................................14-14
14.3.6 LCD Contrast Adjustment [S1C63004/008/016] ............................................14-14
14.4 Display Memory ...........................................................................................................14-15
14.5 I/O Memory of LCD Driver............................................................................................14-15
14.6 Precautions ..................................................................................................................14-17
15 Sound Generator .......................................................................................................15-1
15.1 Configuration of Sound Generator ................................................................................15-1
15.2 Controlling Operating Clock ..........................................................................................15-1

CONTENTS
iv Seiko Epson Corporation S1C63003/004/008/016 TECHNICAL MANUAL
(Rev. 1.1)
15.3 Buzzer Output Control...................................................................................................15-1
15.4 Buzzer Frequency and Sound Level Settings ...............................................................15-2
15.5 Digital Envelope ...........................................................................................................15-3
15.6 One-shot output ...........................................................................................................15-3
15.7 I/O Memory of Sound Generator...................................................................................15-4
15.8 Precautions ...................................................................................................................15-6
16 R/F Converter.............................................................................................................16-1
16.1 Configuration of R/F Converter .....................................................................................16-1
16.2 Controlling Operating Clock ..........................................................................................16-1
16.3 Connection Terminals and CR Oscillation Circuit..........................................................16-2
16.4 Operation of R/F Conversion.........................................................................................16-4
16.5 Interrupt Function ..........................................................................................................16-6
16.6 Continuous Oscillation Function....................................................................................16-8
16.7 I/O Memory of R/F Converter........................................................................................16-8
16.8 Precautions ..................................................................................................................16-11
17 SVD (Supply Voltage Detection) Circuit [S1C63004/008/016] ........................17-1
17.1 Configuration of SVD Circuit .........................................................................................17-1
17.2 SVD Operation ..............................................................................................................17-1
17.3 I/O Memory of SVD Circuit............................................................................................17-2
17.4 Precautions ...................................................................................................................17-2
18 Integer Multiplier [S1C63008/016] .........................................................18-1
18.1 Configuration of Integer Multiplier .................................................................................18-1
18.2 Controlling Clock Manager............................................................................................18-1
18.3 Multiplication Mode .......................................................................................................18-1
18.4 Division Mode................................................................................................................18-2
18.5 Execution Cycle.............................................................................................................18-2
18.6 I/O Memory of Integer Multiplier....................................................................................18-3
18.7 Precautions ...................................................................................................................18-5
19 Electrical Characteristics..........................................................................................19-1
19.1 Absolute Maximum Rating ............................................................................................19-1
19.2 Recommended Operating Conditions ...........................................................................19-1
19.3 DC Characteristics ........................................................................................................19-2
19.4 Analog Circuit Characteristics and Current Consumption.............................................19-3
19.4.1 LCD Driver ......................................................................................................19-3
19.4.2 SVD circuit [S1C63004/008/016] ....................................................................19-4
19.4.3 R/F converter circuit........................................................................................19-5
19.4.4 Current consumption ......................................................................................19-5
19.5 Oscillation Characteristics.............................................................................................19-7
19.6 Serial Interface AC Characteristics [S1C63004/008/016] .............................................19-8
19.7 Timing Chart..................................................................................................................19-8
19.8 Characteristics Curves (reference value) ......................................................................19-9
20 Basic External Wiring Diagram ................................................................................20-1
Appendix A List of I/O Registers................................................................................ AP-A-1
FF00H Oscillation Circuit ........................................................................ AP-A-1
FF01H Watchdog Timer ......................................................................... AP-A-1
FF02H–FF03H Power Supply Circuit .................................................................. AP-A-1

CONTENTS
S1C63003/004/008/016 TECHNICAL MANUAL Seiko Epson Corporation v
(Rev. 1.1)
FF04H–FF05H SVD Circuit ................................................................................. AP-A-1
FF10H–FF1BH Clock Manager ........................................................................... AP-A-1
FF20H–FF3FH I/O Ports ..................................................................................... AP-A-2
FF40H–FF42H Clock Timer ................................................................................. AP-A-4
FF44H–FF47H Sound Generator ........................................................................ AP-A-4
FF48H–FF4DH Stopwatch Timer ......................................................................... AP-A-4
FF50H–FF52H LCD Driver .................................................................................. AP-A-5
FF58H–FF5CH Serial Interface ........................................................................... AP-A-5
FF60H–FF6BH R/F Converter .............................................................................. AP-A-5
FF70H–FF76H Integer Multiplier ......................................................................... AP-A-6
FF80H–FF9FH Programmable Timer .................................................................. AP-A-7
FFE1H–FFFFH Interrupt Controller ...................................................................... AP-A-9
Appendix B Peripheral Circuit Boards for S1C6F016............................................... AP-B-1
B.1 Names and Functions of Each Part ............................................................................. AP-B-1
B.1.1 S5U1C63000P6............................................................................................. AP-B-1
B.1.2 S5U1C6F016P2 ............................................................................................ AP-B-3
B.2 Connecting to the Target System................................................................................. AP-B-5
B.3 Downloading to S5U1C63000P6 ................................................................................. AP-B-8
B.4 Usage Precautions ...................................................................................................... AP-B-9
B.4.1 Operational precautions ............................................................................... AP-B-9
B.4.2 Differences with the actual IC........................................................................ AP-B-9
B.5 Product Specifications ................................................................................................ AP-B-12
B.5.1 Specifications of S5U1C63000P6 ................................................................ AP-B-12
B.5.2 Specifications of S5U1C6F016P2 ................................................................ AP-B-12
Appendix C Power Saving .......................................................................................... AP-C-1
C.1 Power Saving by Clock Control.................................................................................... AP-C-1
C.2 Power Saving by Power Supply Control....................................................................... AP-C-3
Appendix D Mask Data Creation Procedure ............................................................. AP-D-1
D.1 Mask Data Creation Flowchart .................................................................................... AP-D-1
D.2 Function Option File Creation Procedure .................................................................... AP-D-1
D.3 Segment Option File Creation Procedure.................................................................... AP-D-1
D.4 Mask Data File Creation Procedure............................................................................. AP-D-2
Appendix E Summary of Notes .................................................................................. AP-E-1
E.1 Summary of Notes by Function ................................................................................... AP-E-1
E.2 Precautions on Mounting ............................................................................................. AP-E-5
Revision History

1 OUTLINE
S1C63003/004/008/016 TECHNICAL MANUAL Seiko Epson Corporation 1-1
(Rev. 1.1)
Outline1
The S1C630 Series of 4-bit microcontrollers (S1C63003/004/008/016) features low voltage operations and low cur-
rent consumption. It consists of a 4-bit core CPU S1C63000 as the core CPU, ROM (maximum 16K words ×13 bits),
RAM (maximum 2K words ×4 bits), timers, and sound generator. It also incorporates a segment LCD controller/
driver that can drive a maximum 56-segment ×8-common LCD panel, and an R/F converter that can measure tem-
perature and humidity using sensors such as a thermistor.
The S1C630 Series is suitable for battery driven clocks and watches with temperature and humidity measurement
functions.
*This manual describes the functions of four mask ROM models in S1C630 Series, S1C63016, S1C63008,
S1C63004, and S1C63003. The descriptions are applied to all these four models unless otherwise specified.
Features1.1
1.1 Features of modelsTable 1.
Function S1C63016 S1C63008 S1C63004 S1C63003
Core 4-bit core CPU S1C63000
OSC1 oscillation circuit 32.768 kHz (Typ.) crystal oscillation circuit
OSC3 oscillation circuit 4.0 MHz (Typ., 3 V model)/1.0 MHz (Typ., 1.5 V model) ceramic oscillation
circuit, 1.8 MHz (Typ., 3 V model)/500 kHz (Typ., 1.5 V model) CR oscilla-
tion circuit (external R), or 500 kHz (Typ., 3 V model)/500 kHz (Typ., 1.5 V
model) CR oscillation circuit (built-in R) (*1)
550 kHz (Typ., 3 V
model)/550 kHz (Typ.,
1.5 V model) CR oscilla-
tion circuit (built-in R)
Instruction set 47 types of basic instructions (411 instructions with all), 8 types of addressing modes
Instruction execution time During operation at 32.768 kHz: 61 µsec 122 µsec 183 µsec
During operation at 4 MHz: 0.5 µsec 1 µsec 1.5 µsec
ROM
capacity
Code ROM 16,384 words ×13 bits 8,192 words ×13 bits 4,096 words ×13 bits
Data ROM 4,096 words ×4 bits 2,048 words ×4 bits 1,024 words ×4 bits Not available
RAM
capacity
Data memory 2,048 words ×4 bits 1,024 words ×4 bits 512 words ×4 bits 256 words ×4 bits
Display memory 448 bits 400 bits 288 bits 110 bits
I/O ports 24 bits 24 bits 20 bits 16 bits
Pull-down resistors can be included. (*1)
The pins can be switched for peripheral circuit inputs/outputs. (*2)
Serial interface 1 port (8-bit clock synchronous system with SPI supported) Not available
LCD driver 56 segments (Max., *1)
×3 to 8 commons (*2)
50 segments (Max., *1)
×3 to 8 commons (*2)
36 segments (Max., *1)
×3 to 8 commons (*2)
22 segments (Max., *1)
×3 to 5 commons (*2)
Time base counters Clock timer
1/1000-second stopwatch timer (with direct key input function)
Clock timer
1/1000-second stop-
watch timer (without
direct key input function)
Programmable timer 8-bit timer ×4 channels
(Can be used as 16-bit
timer ×2 or 16-bit timer
×1 + 8-bit timer ×2) (*2)
8-bit timer ×3 channels
(Can be used as 16-bit timer ×1 + 8-bit timer ×
1) (*2)
8-bit timer ×1 channel
Watchdog timer Built-in
Sound generator With envelope and 1-shot output functions
R/F converter 2 channels, CR oscillation type R/F converter with 20-bit counters, supports resistive humidity sen-
sors.
Integer multiplier 8-bit accumulator ×1 channel
Multiplication: 8 bits ×8 bits →16-bit product
Division: 16 bits ÷8 bits →8-bit quotient and
8-bit remainder
Not available
Supply voltage detection
(SVD) circuit
Programmable 29 detection voltage levels (*2) Not available
External interrupt
Key input 8 systems 4 systems
Internal interrupt
Watchdog timer
Clock timer
Stopwatch timer
Programmable timer
Serial interface
R/F converter
1 system (NMI)
8 systems
4 systems
8 systems
1 system
3 systems
1 system (NMI)
8 systems
4 systems
6 systems
1 system
3 systems
1 system (NMI)
4 systems
2 systems
1 system
–
3 systems

1 OUTLINE
1-2 Seiko Epson Corporation S1C63003/004/008/016 TECHNICAL MANUAL
(Rev. 1.1)
Function S1C63016 S1C63008 S1C63004 S1C63003
Power supply voltage 1.8 to 5.5 V (3 V normal type) or 1.1 to 1.7 V (1.5 V low-voltage type) (*1)
Operating temperature range -40 to 85°C
Current
consump-
tion (Typ.)
SLEEP (32 kHz) 0.1 µA (3 V model)/0.1 µA (1.5 V model)
HALT (32 kHz) 0.5 µA (3 V model)/0.5 µA (1.5 V model)
RUN (32 kHz) 2.3 µA (3 V model)/2.0 µA (1.5 V model)
RUN (4 M/1 MHz) 220 µA (4 MHz, 3 V model)/
60 µA (1 MHz, 1.5 V model)
40 µA (550 kHz, 3 V
model)/30 µA (550 kHz,
1.5 V model)
Shipment form QFP15-100pin,
TQFP14-100pin,
or die form
QFP14-80pin,
TQFP14-100pin,
or die form
QFP12-48pin
or die form
*1: Can be selected with mask option. *2: Can be selected with software.
Block Diagram1.2
S1C63016
OSC1
OSC2
OSC3
OSC4
TEST
RESET
KEY00–03
KEY10–13
FOUT
KRST00–03
RUN_STP
LAP
EVIN_A, B
TOUT_A, B
BZ
SCLK
SOUT
SIN
SRDY_SS
RFOUT
RFIN0
SEN0, REF0
RFIN1
SEN1, REF1
HUD
P00 / KEY00 / RUN_STP / KRST00
P01 / KEY01 / LAP / KRST01
P02 / KEY02 / KRST02
P03 / KEY03 / KRST03
P10 / KEY10 / EVIN_A
P11 / KEY11/ TOUT_A
P12 / KEY12 / BZ
P13 / KEY13 / FOUT
P20
P21
P22 / EVIN_B
P23 / TOUT_B
P30 / SCLK
P31 / SOUT
P32 / SIN
P33 / SRDY_SS
P40
P41
P42
P43
P50 / RFOUT
P51 / SEN0
P52 / REF0
P53 / RFIN0
HUD
SEN1
REF1
RFIN1
SEG44
SEG45
SEG46
SEG47
SEG40
SEG41
SEG42
SEG43
SEG36
SEG37
SEG38
SEG39
SEG48
SEG49
SEG50
SEG51
SEG55
SEG54
SEG53
SEG52
SEG0–35
COM0–7
SEG36–55 Mask option
VDD
VD1
VOSC
VC1–3
CA, CB
VSS
Core CPU S1C63000
Code ROM
16,384 words ×13 bits
System Reset
Control
Interrupt
Controller
OSC
RAM
2,048 words ×4 bits
Data ROM
4,096 words ×4 bits
LCD Controller
& Driver
Power
Controller
SVD
Integer Multiplier
Watchdog
Timer
Clock
Management
Unit
Clock
Timer
Stopwatch
Timer
Programmable
Timer
Sound
Generator
Test
R/F Converter
I/O Controller
& I/O Port
Serial
Interface
2.1 S1C63016 block diagramFigure 1.

1 OUTLINE
S1C63003/004/008/016 TECHNICAL MANUAL Seiko Epson Corporation 1-3
(Rev. 1.1)
S1C63008
OSC1
OSC2
OSC3
OSC4
TEST
RESET
SEG0–29
COM0–7
KEY00–03
KEY10–13
FOUT
SEG36–55
KRST00–03
RUN_STP
LAP
EVIN_A, B
TOUT_A, B
BZ
SCLK
SOUT
SIN
SRDY_SS
RFOUT
RFIN0
SEN0, REF0
RFIN1
SEN1, REF1
HUD
SEG44
SEG45
SEG46
SEG47
SEG40
SEG41
SEG42
SEG43
SEG36
SEG37
SEG38
SEG39
SEG48
SEG49
SEG50
SEG51
SEG55
SEG54
SEG53
SEG52
Mask option
P00 / KEY00 / RUN_STP / KRST00
P01 / KEY01 / LAP / KRST01
P02 / KEY02 / KRST02
P03 / KEY03 / KRST03
P10 / KEY10 / EVIN_A
P11 / KEY11/ TOUT_A
P12 / KEY12 / BZ
P13 / KEY13 / FOUT
P20
P21
P22 / EVIN_B
P23 / TOUT_B
P30 / SCLK
P31 / SOUT
P32 / SIN
P33 / SRDY_SS
P40
P41
P42
P43
P50 / RFOUT
P51 / SEN0
P52 / REF0
P53 / RFIN0
HUD
SEN1
REF1
RFIN1
VDD
VD1
VOSC
VC1–3
CA, CB
VSS
Core CPU S1C63000
Code ROM
8,192 words ×13 bits
System Reset
Control
Interrupt
Controller
OSC
RAM
1,024 words ×4 bits
Data ROM
2,048 words ×4 bits
LCD Controller
& Driver
Power
Controller
SVD
Integer Multiplier
Watchdog
Timer
Clock
Management
Unit
Clock
Timer
Stopwatch
Timer
Programmable
Timer
Sound
Generator
Test
R/F Converter
I/O Controller
& I/O Port
Serial
Interface
2.2 S1C63008 block diagramFigure 1.

1 OUTLINE
1-4 Seiko Epson Corporation S1C63003/004/008/016 TECHNICAL MANUAL
(Rev. 1.1)
S1C63004
OSC1
OSC2
OSC3
OSC4
TEST
VDD
VD1
VOSC
VC1–3
CA, CB
VSS
RESET
P00 / KEY00 / RUN_STP / KRST00
P01 / KEY01 / LAP / KRST01
P02 / KEY02 / KRST02
P03 / KEY03 / KRST03
P10 / KEY10 / EVIN_A
P11 / KEY11/ TOUT_A
P12 / KEY12 / BZ
P13 / KEY13 / FOUT
P20
P21
P22 / EVIN_B
P23 / TOUT_B
P30 / SCLK
P31 / SOUT
P32 / SIN
P33 / SRDY_SS
P50 / RFOUT
P51 / SEN0
P52 / REF0
P53 / RFIN0
HUD
SEN1
REF1
RFIN1
SEG44
SEG45
SEG46
SEG47
SEG40
SEG41
SEG42
SEG43
SEG48
SEG49
SEG50
SEG51
SEG55
SEG54
SEG53
SEG52
SEG0–19
COM0–7
KEY00–03
KEY10–13
FOUT
SEG40–55
KRST00–03
RUN_STP
LAP
EVIN_A, B
TOUT_A, B
BZ
SCLK
SOUT
SIN
SRDY_SS
RFOUT
RFIN0
SEN0, REF0
RFIN1
SEN1, REF1
HUD
Mask option
Core CPU S1C63000
Code ROM
4,096 words ×13 bits
System Reset
Control
Interrupt
Controller
OSC
RAM
512 words ×4 bits
Data ROM
1,024 words ×4 bits
LCD Controller
& Driver
Power
Controller
SVD
Watchdog
Timer
Clock
Management
Unit
Clock
Timer
Stopwatch
Timer
Programmable
Timer
Sound
Generator
Test
R/F Converter
I/O Controller
& I/O Port
Serial
Interface
2.3 S1C63004 block diagramFigure 1.

1 OUTLINE
S1C63003/004/008/016 TECHNICAL MANUAL Seiko Epson Corporation 1-5
(Rev. 1.1)
S1C63003
OSC1
OSC2
TEST
VDD
VD1
VOSC
VC1–3
CA, CB
VSS
RESET
P00 / KEY00 / KRST00
P01 / KEY01 / KRST01
P02 / KEY02 / KRST02
P03 / KEY03 / KRST03
P10 / EVIN_A
P11 / TOUT_A
P12 / BZ
P13 / FOUT
P20
P21
P22
P23
P50 / RFOUT
P51 / SEN0
P52 / REF0
P53 / RFIN0
HUD
SEN1
REF1
RFIN1
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG55
SEG54
SEG53
SEG52
SEG0–9
COM0–4
KEY00–03
FOUT
SEG44–55
KRST00–03
EVIN_A
TOUT_A
BZ
RFOUT
RFIN0
SEN0, REF0
RFIN1
SEN1, REF1
HUD
Mask option
Core CPU S1C63000
Code ROM
4,096 words ×13 bits
System Reset
Control
Interrupt
Controller
OSC
RAM
256 words ×4 bits
LCD Controller
& Driver
Power
Controller
Watchdog
Timer
Clock
Management
Unit
Clock
Timer
Stopwatch
Timer
Programmable
Timer
Sound
Generator
Test
R/F Converter
I/O Controller
& I/O Port
2.4 S1C63003 block diagramFigure 1.

1 OUTLINE
1-6 Seiko Epson Corporation S1C63003/004/008/016 TECHNICAL MANUAL
(Rev. 1.1)
Mask Option1.3
S1C63003/004/008/016 provides the mask options shown below. Several hardware specifications are prepared in
each optional item, and one of them can be selected according to the application. Use the function option generator
"winfog" and segment option generator "winsog" provided as development tools for this selection. Mask pattern of
the IC is finally generated based on the data created by winfog and winsog. Refer to the "S5U1C63000A Manual"
for these tools.
<Outline of the mask option>
(1) Operating power voltage type
Either 3 V normal type (1.8 to 5.5 V) or 1.5 V low-voltage type (1.1 to 1.7 V) can be selected as the operating
power voltage type.
(2) OSC3 oscillation circuit
In the S1C63004/008/016, the OSC3 oscillator type can be selected from ceramic oscillation, CR oscillation (ex-
ternal R) and CR oscillation (built-in R). The S1C63003 OSC3 oscillator type is fixed at CR oscillation (built-in
R). Refer to "OSC3 Oscillation Circuit" in the "Oscillation Circuit and Clock Control" chapter for details.
(3) RESET terminal pull-down resistor
An internal pull-down resistor can be incorporated into the RESET port. Refer to "Reset Terminal (RESET)" in
the "Initial Reset" chapter for details.
(4) SEG/GPIO/RFC selector
The I/O port (P20–P53) and R/F converter input/output pins are shared with the SEG terminals. This mask op-
tion allows selection of whether each of these pins are used for the I/O port or R/F converter or used for the SEG
output. Refer to "Mask Option" in the "LCD Driver" chapter for details.
(5) I/O port pull-down resistor
An internal pull-down resistor that will be enabled in input mode can be incorporated into each I/O port (P00–
P53). Refer to "Mask Option" in the "I/O Ports" chapter for details.
(6) Output specification of the I/O port
Either complementary output or P-channel open drain output can be selected as the output cell type of each I/O
port (P00–P53). Refer to "Mask Option" in the "I/O Ports" chapter for details. Do not configure the P50–P53 ports
to P-channel open drain output if the R/F converter (channel 0) is used.
(7) Multiple key entry reset function (by simultaneous high input to the P0x ports)
This option allows selection of whether the function to reset the IC by pressing multiple keys simultaneously is
implemented or not. A combination of the P0x ports (P00–P03) to be used for this function can also be selected.
Refer to "Simultaneous High Input to P0x Ports (P00–P03)" in the "Initial Reset" chapter for details.
(8) Time authorize circuit for the multiple key entry reset function
When the multiple key entry reset option (option (7)) is selected, the time authorize circuit can also be incorpo-
rated. The time authorize circuit measures the high pulse width of the simultaneous input signals and asserts the
reset signal if it is longer than the predetermined time. This option is not available when the multiple key entry
reset option is not selected. Refer to "Simultaneous High Input to P0x Ports (P00–P03)" in the "Initial Reset"
chapter for details.
(9) LCD drive power supply
In the S1C63004/008/016, either the internal power supply or an external power supply can be selected as the
LCD drive power source. When the internal power supply is selected, the reference voltage for boosting (VC1 or
VC2) can be set using a register. The S1C63003 LCD drive power source can also be selected from the internal
power supply and an external power supply by mask option. When using the internal power supply, the reference
voltage for boosting (VC1 or VC2) should be selected by mask option. Refer to "Mask Option" in the "LCD Driver"
chapter for details.
(10) LCD segment specification
The display memory bits can be allocated to a desired SEG terminal. It is also possible to set SEG terminals for
DC output. Refer to "Mask Option" in the "LCD Driver" chapter for details.

1 OUTLINE
S1C63003/004/008/016 TECHNICAL MANUAL Seiko Epson Corporation 1-7
(Rev. 1.1)
3.1 Option list (S1C63008/016)Table 1.
Optional item Option
Operating power voltage 1. Normal Type (1.8–5.5 V) 2. Low Voltage Type (1.1–1.7 V)
OSC3 oscillation circuit 1. CR (built-in R)
2. CR (external R)
3. Ceramic (4.0 MHz)
RESET terminal pull-down resistor 1. Use 2. Not Use
SEG/GPIO/RFC selector P20 1. I/O 2. SEG
P21 1. I/O 2. SEG
P22 1. I/O 2. SEG
P23 1. I/O 2. SEG
P30 1. I/O 2. SEG
P31 1. I/O 2. SEG
P32 1. I/O 2. SEG
P33 1. I/O 2. SEG
P40 1. I/O 2. SEG
P41 1. I/O 2. SEG
P42 1. I/O 2. SEG
P43 1. I/O 2. SEG
P50 1. I/O 2. SEG
P51 1. I/O 2. SEG
P52 1. I/O 2. SEG
P53 1. I/O 2. SEG
RFIN1 1. RFC 2. SEG
REF1 1. RFC 2. SEG
SEN1 1. RFC 2. SEG
HUD 1. RFC 2. SEG
I/O port pull-down resistor P00 1. Use 2. Not Use
P01 1. Use 2. Not Use
P02 1. Use 2. Not Use
P03 1. Use 2. Not Use
P10 1. Use 2. Not Use
P11 1. Use 2. Not Use
P12 1. Use 2. Not Use
P13 1. Use 2. Not Use
P20 1. Use 2. Not Use
P21 1. Use 2. Not Use
P22 1. Use 2. Not Use
P23 1. Use 2. Not Use
P30 1. Use 2. Not Use
P31 1. Use 2. Not Use
P32 1. Use 2. Not Use
P33 1. Use 2. Not Use
P40 1. Use 2. Not Use
P41 1. Use 2. Not Use
P42 1. Use 2. Not Use
P43 1. Use 2. Not Use
P50 1. Use 2. Not Use
P51 1. Use 2. Not Use
P52 1. Use 2. Not Use
P53 1. Use 2. Not Use
I/O port output
specification
P00 1. Complementary 2. Pch Open Drain
P01 1. Complementary 2. Pch Open Drain
P02 1. Complementary 2. Pch Open Drain
P03 1. Complementary 2. Pch Open Drain
P10 1. Complementary 2. Pch Open Drain
P11 1. Complementary 2. Pch Open Drain
P12 1. Complementary 2. Pch Open Drain
P13 1. Complementary 2. Pch Open Drain
P20 1. Complementary 2. Pch Open Drain
P21 1. Complementary 2. Pch Open Drain
P22 1. Complementary 2. Pch Open Drain
P23 1. Complementary 2. Pch Open Drain
P30 1. Complementary 2. Pch Open Drain
P31 1. Complementary 2. Pch Open Drain
P32 1. Complementary 2. Pch Open Drain
P33 1. Complementary 2. Pch Open Drain
P40 1. Complementary 2. Pch Open Drain
P41 1. Complementary 2. Pch Open Drain
P42 1. Complementary 2. Pch Open Drain
P43 1. Complementary 2. Pch Open Drain

1 OUTLINE
1-8 Seiko Epson Corporation S1C63003/004/008/016 TECHNICAL MANUAL
(Rev. 1.1)
Optional item Option
I/O port output
specification
P50 1. Complementary 2. Pch Open Drain *
P51 1. Complementary 2. Pch Open Drain *
P52 1. Complementary 2. Pch Open Drain *
P53 1. Complementary 2. Pch Open Drain *
P0x port multiple key entry reset
combination
1. Not Use
2. Use <P00, P01>
3. Use <P00, P01, P02>
4. Use <P00, P01, P02, P03>
P0x port multiple key entry reset time
authorization
1. Not Use 2. Use
LCD drive power supply
1. Internal 1/3 bias
2. External 1/3 bias, VDD = VC2 (4.5 V panel)
3. External 1/3 bias, VDD = VC3 (3.0 V panel)
4. External 1/2 bias, VDD = VC3, VC1 = VC2 (3.0 V panel)
Selectable nFixed
*Do not select "Pch Open Drain" as the P50–P53 port output specification if the R/F converter (channel 0) is used.
3.2 Option list (S1C63004)Table 1.
Optional item Option
Operating power voltage 1. Normal Type (1.8–5.5 V) 2. Low Voltage Type (1.1–1.7 V)
OSC3 oscillation circuit 1. CR (built-in R)
2. CR (external R)
3. Ceramic (4.0 MHz)
RESET terminal pull-down resistor 1. Use 2. Not Use
SEG/GPIO/RFC selector P20 1. I/O 2. SEG
P21 1. I/O 2. SEG
P22 1. I/O 2. SEG
P23 1. I/O 2. SEG
P30 1. I/O 2. SEG
P31 1. I/O 2. SEG
P32 1. I/O 2. SEG
P33 1. I/O 2. SEG
P50 1. I/O 2. SEG
P51 1. I/O 2. SEG
P52 1. I/O 2. SEG
P53 1. I/O 2. SEG
RFIN1 1. RFC 2. SEG
REF1 1. RFC 2. SEG
SEN1 1. RFC 2. SEG
HUD 1. RFC 2. SEG
I/O port pull-down resistor P00 1. Use 2. Not Use
P01 1. Use 2. Not Use
P02 1. Use 2. Not Use
P03 1. Use 2. Not Use
P10 1. Use 2. Not Use
P11 1. Use 2. Not Use
P12 1. Use 2. Not Use
P13 1. Use 2. Not Use
P20 1. Use 2. Not Use
P21 1. Use 2. Not Use
P22 1. Use 2. Not Use
P23 1. Use 2. Not Use
P30 1. Use 2. Not Use
P31 1. Use 2. Not Use
P32 1. Use 2. Not Use
P33 1. Use 2. Not Use
P50 1. Use 2. Not Use
P51 1. Use 2. Not Use
P52 1. Use 2. Not Use
P53 1. Use 2. Not Use
I/O port output
specification
P00 1. Complementary 2. Pch Open Drain
P01 1. Complementary 2. Pch Open Drain
P02 1. Complementary 2. Pch Open Drain
P03 1. Complementary 2. Pch Open Drain
P10 1. Complementary 2. Pch Open Drain
P11 1. Complementary 2. Pch Open Drain
P12 1. Complementary 2. Pch Open Drain
P13 1. Complementary 2. Pch Open Drain

1 OUTLINE
S1C63003/004/008/016 TECHNICAL MANUAL Seiko Epson Corporation 1-9
(Rev. 1.1)
Optional item Option
I/O port output
specification
P20 1. Complementary 2. Pch Open Drain
P21 1. Complementary 2. Pch Open Drain
P22 1. Complementary 2. Pch Open Drain
P23 1. Complementary 2. Pch Open Drain
P30 1. Complementary 2. Pch Open Drain
P31 1. Complementary 2. Pch Open Drain
P32 1. Complementary 2. Pch Open Drain
P33 1. Complementary 2. Pch Open Drain
P50 1. Complementary 2. Pch Open Drain *
P51 1. Complementary 2. Pch Open Drain *
P52 1. Complementary 2. Pch Open Drain *
P53 1. Complementary 2. Pch Open Drain *
P0x port multiple key entry reset
combination
1. Not Use
2. Use <P00, P01>
3. Use <P00, P01, P02>
4. Use <P00, P01, P02, P03>
P0x port multiple key entry reset time
authorization
1. Not Use 2. Use
LCD drive power supply
1. Internal 1/3 bias
2. External 1/3 bias, VDD = VC2 (4.5 V panel)
3. External 1/3 bias, VDD = VC3 (3.0 V panel)
4. External 1/2 bias, VDD = VC3, VC1 = VC2 (3.0 V panel)
Selectable nFixed
*Do not select "Pch Open Drain" as the P50–P53 port output specification if the R/F converter (channel 0) is used.
3.3 Option list (S1C63003)Table 1.
Optional item Option
Operating power voltage 1. Normal Type (1.8–5.5 V) 2. Low Voltage Type (1.1–1.7 V)
OSC3 oscillation circuit n1. CR (built-in R)
2. CR (external R)
3. Ceramic (4.0 MHz)
RESET terminal pull-down resistor 1. Use 2. Not Use
SEG/GPIO/RFC selector P20 1. I/O 2. SEG
P21 1. I/O 2. SEG
P22 1. I/O 2. SEG
P23 1. I/O 2. SEG
P50 1. I/O 2. SEG
P51 1. I/O 2. SEG
P52 1. I/O 2. SEG
P53 1. I/O 2. SEG
RFIN1 1. RFC 2. SEG
REF1 1. RFC 2. SEG
SEN1 1. RFC 2. SEG
HUD 1. RFC 2. SEG
I/O port pull-down resistor P00 1. Use 2. Not Use
P01 1. Use 2. Not Use
P02 1. Use 2. Not Use
P03 1. Use 2. Not Use
P10 1. Use 2. Not Use
P11 1. Use 2. Not Use
P12 1. Use 2. Not Use
P13 1. Use 2. Not Use
P20 1. Use 2. Not Use
P21 1. Use 2. Not Use
P22 1. Use 2. Not Use
P23 1. Use 2. Not Use
P50 1. Use 2. Not Use
P51 1. Use 2. Not Use
P52 1. Use 2. Not Use
P53 1. Use 2. Not Use
I/O port output
specification
P00 1. Complementary 2. Pch Open Drain
P01 1. Complementary 2. Pch Open Drain
P02 1. Complementary 2. Pch Open Drain
P03 1. Complementary 2. Pch Open Drain
P10 1. Complementary 2. Pch Open Drain
P11 1. Complementary 2. Pch Open Drain
P12 1. Complementary 2. Pch Open Drain
P13 1. Complementary 2. Pch Open Drain

1 OUTLINE
1-10 Seiko Epson Corporation S1C63003/004/008/016 TECHNICAL MANUAL
(Rev. 1.1)
Optional item Option
I/O port output
specification
P20 1. Complementary 2. Pch Open Drain
P21 1. Complementary 2. Pch Open Drain
P22 1. Complementary 2. Pch Open Drain
P23 1. Complementary 2. Pch Open Drain
P50 1. Complementary 2. Pch Open Drain *
P51 1. Complementary 2. Pch Open Drain *
P52 1. Complementary 2. Pch Open Drain *
P53 1. Complementary 2. Pch Open Drain *
P0x port multiple key entry reset
combination
1. Not Use
2. Use <P00, P01>
3. Use <P00, P01, P02>
4. Use <P00, P01, P02, P03>
P0x port multiple key entry reset time
authorization
1. Not Use 2. Use
LCD drive power supply
1. Internal (VC2 reference) 1/3 bias (3.0 V panel)
2. Internal (VC1 reference) 1/3 bias (3.0 V panel)
3. External 1/3 bias, VDD = VC2 (4.5 V panel)
4. External 1/3 bias, VDD = VC3 (3.0 V panel)
5. External 1/2 bias, VDD = VC3, VC1 = VC2 (3.0 V panel)
Selectable nFixed
*Do not select "Pch Open Drain" as the P50–P53 port output specification if the R/F converter (channel 0) is used.

1 OUTLINE
S1C63003/004/008/016 TECHNICAL MANUAL Seiko Epson Corporation 1-11
(Rev. 1.1)
3.4 Segment option (S1C63016)Table 1.
Pin
name
Address (F0xxH)
Output specificationCOM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7
HLDHLDHLDHLDHLDHLDHLDHLD
SEG0 S C N
SEG1 S C N
SEG2 S C N
SEG3 S C N
SEG4 S C N
SEG5 S C N
SEG6 S C N
SEG7 S C N
SEG8 S C N
SEG9 S C N
SEG10 S C N
SEG11 S C N
SEG12 S C N
SEG13 S C N
SEG14 S C N
SEG15 S C N
SEG16 S C N
SEG17 S C N
SEG18 S C N
SEG19 S C N
SEG20 S C N
SEG21 S C N
SEG22 S C N
SEG23 S C N
SEG24 S C N
SEG25 S C N
SEG26 S C N
SEG27 S C N
SEG28 S C N
SEG29 S C N
SEG30 S C N
SEG31 S C N
SEG32 S C N
SEG33 S C N
SEG34 S C N
SEG35 S C N
SEG36 nS CN
SEG37 nS CN
SEG38 nS CN
SEG39 nS CN
SEG40 nS CN
SEG41 nS CN
SEG42 nS CN
SEG43 nS CN
SEG44 nS CN
SEG45 nS CN
SEG46 nS CN
SEG47 nS CN
SEG48 nS CN
SEG49 nS CN
SEG50 nS CN
SEG51 nS CN
SEG52 nS CN
SEG53 nS CN
SEG54 nS CN
SEG55 nS CN
<address> H: RAM data high-order address (0–7) <Output specification> S: Segment output
L: RAM data low-order address (0–F) C: Complementary output
D: Data bit (0–3) N: Nch open drain output
Notes for using the segment option generator "winsog" (S1C63016)
1. The output specification of SEG0 to SEG35 can be selected from "LCD segment output (S)," "DC complementary
output (C)" and "DC Nch open drain output (N)."
2. Configurations for SEG/GPIO pins (SEG36 to SEG55)
•Always select "LCD segment output (S)" as the output specification of SEG36 to SEG55.
•Leave the address cells of the pins for which "1. I/O" is selected with the "SEG/GPIO/RFC selector" option.
•Enter addresses and data bits to the address cells of the pins for which "2. SEG" is selected with the "SEG/
GPIO/RFC selector" option.

1 OUTLINE
1-12 Seiko Epson Corporation S1C63003/004/008/016 TECHNICAL MANUAL
(Rev. 1.1)
3.5 Segment option (S1C63008)Table 1.
Pin
name
Address (F0xxH)
Output specificationCOM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7
HLDHLDHLDHLDHLDHLDHLDHLD
SEG0 S C N
SEG1 S C N
SEG2 S C N
SEG3 S C N
SEG4 S C N
SEG5 S C N
SEG6 S C N
SEG7 S C N
SEG8 S C N
SEG9 S C N
SEG10 S C N
SEG11 S C N
SEG12 S C N
SEG13 S C N
SEG14 S C N
SEG15 S C N
SEG16 S C N
SEG17 S C N
SEG18 S C N
SEG19 S C N
SEG20 S C N
SEG21 S C N
SEG22 S C N
SEG23 S C N
SEG24 S C N
SEG25 S C N
SEG26 S C N
SEG27 S C N
SEG28 S C N
SEG29 S C N
SEG30 nSCN
SEG31 nSCN
SEG32 nSCN
SEG33 nSCN
SEG34 nSCN
SEG35 nSCN
SEG36 nS CN
SEG37 nS CN
SEG38 nS CN
SEG39 nS CN
SEG40 nS CN
SEG41 nS CN
SEG42 nS CN
SEG43 nS CN
SEG44 nS CN
SEG45 nS CN
SEG46 nS CN
SEG47 nS CN
SEG48 nS CN
SEG49 nS CN
SEG50 nS CN
SEG51 nS CN
SEG52 nS CN
SEG53 nS CN
SEG54 nS CN
SEG55 nS CN
<address> H: RAM data high-order address (0–7) <Output specification> S: Segment output
L: RAM data low-order address (0–F) C: Complementary output
D: Data bit (0–3) N: Nch open drain output
Notes for using the segment option generator "winsog" (S1C63008)
1. The output specification of SEG0 to SEG29 can be selected from "LCD segment output (S)," "DC complementary
output (C)" and "DC Nch open drain output (N)."
2. Configurations for SEG/GPIO pins (SEG36 to SEG55)
•Always select "LCD segment output (S)" as the output specification of SEG36 to SEG55.
•Leave the address cells of the pins for which "1. I/O" is selected with the "SEG/GPIO/RFC selector" option.
•Enter addresses and data bits to the address cells of the pins for which "2. SEG" is selected with the "SEG/
GPIO/RFC selector" option.
3. Configurations for nonexistent SEG pins (SEG30 to SEG35)
•Always select "LCD segment output (S)" as the output specification of SEG30 to SEG35.
•Leave the address cells for SEG30 to SEG35 blank. (Unused addresses will be allocated.)