Emerson Pm8560 User manual

Pm8560: Octal E1/T1/J1 Line Interface PTMC
User’s Manual
from Emerson Network Power™
Embedded Computing
October 2007

The information in this manual has been checked and is believed to be accurate and reli-
able. HOWEVER, NO RESPONSIBILITY IS ASSUMED BY EMERSON NETWORK POWER,
EMBEDDED COMPUTING FOR ITS USE OR FOR ANY INACCURACIES. Specifications are sub-
ject to change without notice. EMERSON DOES NOT ASSUME ANY LIABILITY ARISING OUT
OF USE OR OTHER APPLICATION OF ANY PRODUCT, CIRCUIT, OR PROGRAM DESCRIBED
HEREIN. This document does not convey any license under Emerson patents or the rights of
others.
Emerson. Consider It Solved is a trademark, and Business-Critical Continuity, Emerson Net-
work Power, and the Emerson Network Power logo are trademarks and service marks of
Emerson Electric Co. © 2007 Emerson Electric Co.
Copyright © 2007 Emerson Electric Co. All rights reserved.
Revision Level: Principal Changes: Date:
10006609-00 Original release March 2006
10006609-01 BDFM PLD changes, revise figure on 6-4, add
figure on 8-13
June 2006
10006609-02 Add RCSR bit 7, monitor version 1.3, new front
panel
December 2006
10006609-03 Add framer waveform, monitor version 1.4 October 2007

10006609-03 Pm8560 User’s Manual i
Regulatory Agency Warnings & Notices
The Emerson Pm8560 meets the requirements set forth by the Federal Communications
Commission (FCC) in Title 47 of the Code of Federal Regulations. The following information
is provided as required by this agency.
This device complies with part 15 of the FCC Rules. Operation is subject to the following two
conditions: (1) This device may not cause harmful interference, and (2) this device must
accept any interference received, including interference that may cause undesired opera-
tion.
FCC RULES AND REGULATIONS — PART 15
This equipment has been tested and found to comply with the limits for a Class A digital
device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reason-
able protection against harmful interference when the equipment is operated in a commer-
cial environment. This equipment generates, uses and can radiate radio frequency energy
and, if not installed and used in accordance with the instructions, may cause harmful inter-
ference to radio communications. Operation of this equipment in a residential area is likely
to cause harmful interference, in which case the user will be required to correct the interfer-
ence at his own expense.
Caution: Making changes or modifications to the Pm8560 hardware without the explicit consent of
Emerson Network Power could invalidate the user’s authority to operate this equipment.
EMC COMPLIANCE
The electromagnetic compatibility (EMC) tests used a Pm8560 model that includes a front
panel assembly from Emerson Network Power.
Caution: For applications where the Pm8560 is provided without a front panel, or where the front
panel has been removed, your system chassis/enclosure must provide the required
electromagnetic interference (EMI) shielding to maintain EMC compliance.
!
!

Regulatory Agency Warnings & Notices (continued)
Pm8560 User’s Manual 10006609-03
ii
EC Declaration of Conformity
According to EN 45014:1998
Manufacturer’s Name: Emerson Network Power
Embedded Computing
Manufacturer’s Address: 8310 Excelsior Drive
Madison, Wisconsin 53717
Declares that the following product, in accordance with the requirements of 89/336/EEC, EMC
Directive and 99/5/EC, RTTE Directive and their amending directives,
Product: AMC Module
Model Name/Number: Pm8560/10005277-xx
has been designed and manufactured to the following specifications:
EN55022:1998 Information Technology Equipment, Radio disturbance characteristics, Limits and
methods of measurement
EN55024:1998 Information Technology Equipment, Immunity characteristics, Limits and methods
of measurement
EN300386 V.1.3.1 Electromagnetic compatibility and radio spectrum matters (ERM);
Telecommunication network equipment; EMC requirements
As manufacturer we hereby declare that the product named above has been designed to comply
with the relevant sections of the above referenced specifications. This product complies with the
essential health and safety requirements of the EMC Directive and RTTE Directive. We have an inter-
nal production control system that ensures compliance between the manufactured products and
the technical documentation.
Issue date: October 10, 2007
Bill Fleury
Compliance Engineer

10006609-03 Pm8560 User’s Manual iii
Contents
1Overview
Components and Features . . . . . . . . . . . 1-1
Functional Overview . . . . . . . . . . . . . . . . 1-2
Additional Information . . . . . . . . . . . . . . 1-6
Product Certification . . . . . . . . . . . . . 1-6
RoHS Compliance. . . . . . . . . . . . . . . . 1-7
Terminology and Notation. . . . . . . . 1-7
Technical References. . . . . . . . . . . . . 1-8
2Setup
Electrostatic Discharge . . . . . . . . . . . . . . 2-1
Pm8560 Circuit Board . . . . . . . . . . . . . . . 2-1
Connectors . . . . . . . . . . . . . . . . . . . . . 2-5
Front Panel . . . . . . . . . . . . . . . . . . . . . 2-5
Pm8560 Setup . . . . . . . . . . . . . . . . . . . . . 2-5
Power Requirements . . . . . . . . . . . . . 2-6
Environmental Considerations . . . . 2-6
Reset Methods . . . . . . . . . . . . . . . . . . 2-6
System JTAG Chain. . . . . . . . . . . . . . . 2-7
Installation. . . . . . . . . . . . . . . . . . . . . . 2-8
Troubleshooting . . . . . . . . . . . . . . . . . . . . 2-9
Technical Support . . . . . . . . . . . . . .2-10
Product Repair . . . . . . . . . . . . . . . . .2-11
3 Central Processing Unit
MPC8560 Functions . . . . . . . . . . . . . . . . . 3-2
Microprocessor Core (e500). . . . . . . . . . 3-3
L1 Cache. . . . . . . . . . . . . . . . . . . . . . . . 3-3
L2 Cache. . . . . . . . . . . . . . . . . . . . . . . . 3-3
Interrupts and Exception Processing3-3
Machine State Register . . . . . . . . . . . 3-3
Communications Processor Module 3-4
Timers . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Interrupt Controller . . . . . . . . . . . . . . 3-4
Internal Interrupt Sources. . . . . 3-5
External Interrupt Sources . . . . 3-5
MPC8560 CPM Port Pin Assignment . . . 3-6
MPC8560 Peripheral Modules . . . . . . . . 3-9
Three-Speed Ethernet Controllers . 3-9
Local Bus Controller . . . . . . . . . . . . . . 3-9
Chip-Select Generation. . . . . . . . . . . 3-9
Processor Reset and Clocking Signals. 3-10
MPC8560 Exception Handling . . . .3-10
4 On-Card Memory
Soldered Flash. . . . . . . . . . . . . . . . . . . . . . .4-1
Serial EEPROMs . . . . . . . . . . . . . . . . . . . . . .4-2
Emerson Memory Map . . . . . . . . . . . 4-2
Double Data Rate SDRAM. . . . . . . . . . . . .4-3
DDR SDRAM Programming . . . . . . . 4-3
5 Serial I/O
Serial Ports. . . . . . . . . . . . . . . . . . . . . . . . . .5-1
Serial Port Connector P17 and Cable5-1
Baud Rate Selection . . . . . . . . . . . . . . . . . .5-2
Baud Rate Generator Configuration 5-3
6TDMInterface
TDM Framer and Line Interface . . . . . . . .6-1
Framer . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
Line Interface . . . . . . . . . . . . . . . . . . . 6-1
Framer Analog Interfaces . . . . . . . . . . . . .6-2
Framer to MPC8560 Interface . . . . . . . . .6-2
Interface Options. . . . . . . . . . . . . . . . 6-2
Signal Definitions. . . . . . . . . . . . . . . . 6-4
Framer Waveform Shape . . . . . . . . . . . . .6-5
Framer Interrupt Mechanism . . . . . . . . . .6-5
Rear Panel I/O Connector P14 . . . . . . . . .6-6
7PCIBusInterface
MPC8560 PCI Features . . . . . . . . . . . . . . .7-1
PCI Support. . . . . . . . . . . . . . . . . . . . . 7-1
MPC8560 PCI Memory Map. . . . . . . 7-2
PCI Vendor and Device ID. . . . . . . . . 7-2
Vital Product Data (VPD). . . . . . . . . . . . . .7-2
Monitor Display . . . . . . . . . . . . . . . . . 7-3
Accessing The Serial EEPROM VPD . 7-4
PCI Configuration Registers . . . . . . . . . . .7-4
Power-on Reset Modes. . . . . . . . . . . 7-5
Monarch Mode. . . . . . . . . . . . . . . . . . 7-5
PCI Interrupts . . . . . . . . . . . . . . . . . . . . . . .7-6
PMC Connector Pin Assignments . . . . . .7-6
PCI Bus Control Signals . . . . . . . . . . . 7-8
8 Programmable Logic
Device
PLD Register Summary . . . . . . . . . . . . . . .8-1

Pm8560 User’s Manual 10006609-03
iv
Product ID . . . . . . . . . . . . . . . . . . . . . . 8-2
Hardware Version . . . . . . . . . . . . . . . 8-2
PLD Version. . . . . . . . . . . . . . . . . . . . . 8-3
PLL Configuration. . . . . . . . . . . . . . . . 8-3
Hardware Configuration 1 . . . . . . . . 8-4
Jumper Settings . . . . . . . . . . . . . . . . . 8-5
LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
Reset Event . . . . . . . . . . . . . . . . . . . . . 8-6
Reset Command. . . . . . . . . . . . . . . . . 8-7
PCI Reset Out Enable. . . . . . . . . . . . . 8-8
PCI Status. . . . . . . . . . . . . . . . . . . . . . . 8-8
Boot Device Failover Mechanism . . 8-9
Miscellaneous Control. . . . . . . . . . .8-11
CT Bus Status . . . . . . . . . . . . . . . . . .8-12
Clock and Sync Registers. . . . . . . . . . . . 8-12
NETREF Control . . . . . . . . . . . . . . . .8-14
Framer Clock Source . . . . . . . . . . . .8-14
MT9045 System Synchronizer
Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-15
SYNC Source . . . . . . . . . . . . . . . . . . .8-16
Primary Clock Source. . . . . . . . . . . .8-17
Secondary Clock Source . . . . . . . . .8-18
TCLK Source . . . . . . . . . . . . . . . . . . .8-19
RCLK Source . . . . . . . . . . . . . . . . . . .8-19
Serial Presence Detect (SPD) Registers 8-20
Row Column . . . . . . . . . . . . . . . . . . .8-20
CAS Latency Refresh . . . . . . . . . . . .8-21
SDRAM Cycle Time for CAS
Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-21
Minimum Row Precharge Time . . .8-22
Minimum Row Delay Between
Activations . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-23
Minimum Row Delay Between RAS-to-
CAS Assertions . . . . . . . . . . . . . . . . . . . . . . . . .8-23
Minimum Active-to-Precharge . . .8-24
Minimum Auto-Refresh to Active/Auto-
Refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-24
Write Recovery Time . . . . . . . . . . . .8-25
Internal Write-to-Read Command
Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-25
9 Ethernet Interfaces
Ethernet Transceiver . . . . . . . . . . . . . . . . .9-1
MDIO/MDC Signals . . . . . . . . . . . . . . 9-1
Ethernet Address . . . . . . . . . . . . . . . . . . . .9-1
Ethernet Connector . . . . . . . . . . . . . . . . . .9-2
10Development Mezzanine
Card
DMC Circuit Board . . . . . . . . . . . . . . . . . 10-1
Connectors . . . . . . . . . . . . . . . . . . . . . . . 10-2
P1 Connector Pin Assignments. . . 10-3
P2 EIA-232 Interface . . . . . . . . . . . . 10-5
P3 JTAG/COP . . . . . . . . . . . . . . . . . . 10-5
P4 JTAG Chain Header. . . . . . . . . . . 10-6
DMC Jumpers and LEDs . . . . . . . . . . . . . 10-7
DMC Setup . . . . . . . . . . . . . . . . . . . . . . . 10-8
Installing the DMC Card . . . . . . . . . 10-8
Troubleshooting. . . . . . . . . . . . . . . . . . . 10-9
Technical Support . . . . . . . . . . . . . 10-10
Product Repair . . . . . . . . . . . . . . . . 10-10
11Monitor
Command-Line Features. . . . . . . . . . . . 11-1
Basic Operation . . . . . . . . . . . . . . . . . . . 11-2
Power-up/Reset Sequence . . . . . . 11-2
POST Diagnostic Results . . . . . . . . 11-4
Monitor SDRAM Usage . . . . . . . . . . 11-4
Updating the Monitor. . . . . . . . . . . 11-4
Boot Redirect and Monitor Recovery
(Watchdog) . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6
Updating the Monitor via TFTP . . . 11-6
Resetting Environment Variables . 11-7
Monitor Command Reference . . . . . . . 11-7
Command Syntax . . . . . . . . . . . . . . 11-7
Command Help . . . . . . . . . . . . . . . . 11-8
Typographic Conventions . . . . . . . 11-8
Boot Commands . . . . . . . . . . . . . . . . . . 11-8
bootbus . . . . . . . . . . . . . . . . . . . . . . . 11-8
bootd . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
bootm . . . . . . . . . . . . . . . . . . . . . . . . 11-9
bootp . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
bootv . . . . . . . . . . . . . . . . . . . . . . . . . 11-9
dhcp. . . . . . . . . . . . . . . . . . . . . . . . . 11-10
rarpboot . . . . . . . . . . . . . . . . . . . . . 11-10
tftpboot. . . . . . . . . . . . . . . . . . . . . . 11-10
Memory Commands . . . . . . . . . . . . . . 11-10
cmp . . . . . . . . . . . . . . . . . . . . . . . . . 11-10
cp . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
find . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
md . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11
mm. . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
nm . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12

Contents (continued)
10006609-03 Pm8560 User’s Manual v
mw . . . . . . . . . . . . . . . . . . . . . . . . . .11-12
Flash Commands . . . . . . . . . . . . . . . . . 11-13
cp . . . . . . . . . . . . . . . . . . . . . . . . . . .11-13
erase. . . . . . . . . . . . . . . . . . . . . . . . .11-13
flinfo . . . . . . . . . . . . . . . . . . . . . . . . .11-13
protect . . . . . . . . . . . . . . . . . . . . . . .11-14
I2C Commands . . . . . . . . . . . . . . . . . . . 11-14
icrc32 . . . . . . . . . . . . . . . . . . . . . . . .11-14
iloop . . . . . . . . . . . . . . . . . . . . . . . . .11-14
imd . . . . . . . . . . . . . . . . . . . . . . . . . .11-15
imd2 . . . . . . . . . . . . . . . . . . . . . . . . .11-15
imm . . . . . . . . . . . . . . . . . . . . . . . . .11-15
imm2 . . . . . . . . . . . . . . . . . . . . . . . .11-15
imw. . . . . . . . . . . . . . . . . . . . . . . . . .11-15
inm . . . . . . . . . . . . . . . . . . . . . . . . . .11-15
iprobe. . . . . . . . . . . . . . . . . . . . . . . .11-16
iprobe2. . . . . . . . . . . . . . . . . . . . . . .11-16
Environment Parameter Commands 11-16
printenv . . . . . . . . . . . . . . . . . . . . . .11-16
saveenv . . . . . . . . . . . . . . . . . . . . . .11-16
setenv. . . . . . . . . . . . . . . . . . . . . . . .11-16
srom_wp . . . . . . . . . . . . . . . . . . . . .11-17
Test Commands . . . . . . . . . . . . . . . . . . 11-17
diags. . . . . . . . . . . . . . . . . . . . . . . . .11-17
mtest . . . . . . . . . . . . . . . . . . . . . . . .11-17
um. . . . . . . . . . . . . . . . . . . . . . . . . . .11-17
test_watchdog . . . . . . . . . . . . . . . .11-17
Other Commands. . . . . . . . . . . . . . . . . 11-18
autoscr . . . . . . . . . . . . . . . . . . . . . . .11-18
base . . . . . . . . . . . . . . . . . . . . . . . . .11-18
bdinfo. . . . . . . . . . . . . . . . . . . . . . . .11-18
coninfo. . . . . . . . . . . . . . . . . . . . . . .11-18
crc32 . . . . . . . . . . . . . . . . . . . . . . . . 11-18
date . . . . . . . . . . . . . . . . . . . . . . . . . 11-18
echo . . . . . . . . . . . . . . . . . . . . . . . . . 11-19
enumpci . . . . . . . . . . . . . . . . . . . . . 11-19
getmonver . . . . . . . . . . . . . . . . . . . 11-19
go . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-19
help . . . . . . . . . . . . . . . . . . . . . . . . . 11-19
iminfo . . . . . . . . . . . . . . . . . . . . . . . 11-19
loop . . . . . . . . . . . . . . . . . . . . . . . . . 11-19
memmap . . . . . . . . . . . . . . . . . . . . 11-20
moninit . . . . . . . . . . . . . . . . . . . . . . 11-20
mon2init . . . . . . . . . . . . . . . . . . . . . 11-20
monrecovery . . . . . . . . . . . . . . . . . 11-21
pci. . . . . . . . . . . . . . . . . . . . . . . . . . . 11-21
ping . . . . . . . . . . . . . . . . . . . . . . . . . 11-21
reset. . . . . . . . . . . . . . . . . . . . . . . . . 11-21
run . . . . . . . . . . . . . . . . . . . . . . . . . . 11-22
script . . . . . . . . . . . . . . . . . . . . . . . . 11-22
showmac. . . . . . . . . . . . . . . . . . . . . 11-22
showpci . . . . . . . . . . . . . . . . . . . . . . 11-22
sleep. . . . . . . . . . . . . . . . . . . . . . . . . 11-22
version . . . . . . . . . . . . . . . . . . . . . . . 11-22
watchdog . . . . . . . . . . . . . . . . . . . . 11-22
Environment Variables . . . . . . . . . . . . 11-23
Troubleshooting. . . . . . . . . . . . . . . . . . 11-24
Download Formats. . . . . . . . . . . . . . . . 11-25
Binary. . . . . . . . . . . . . . . . . . . . . . . . 11-25
Motorola S-Record . . . . . . . . . . . . 11-25
12Glossary

Contents (continued)
Pm8560 User’s Manual 10006609-03
vi

10006609-03 Pm8560 User’s Manual vii
Figures
Figure 1-1: General System Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Figure 1-2: Memeory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Figure 2-1: Component Map, Top (Rev. 03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Figure 2-2: Component Map, Bottom (Rev. 01). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Figure 2-3: LED and Switch Locations, Top . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Figure 2-4: Reset Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Figure 2-5: System JTAG Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Figure 2-6: Installing the Pm8560 on the Baseboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Figure 2-7: Serial Number and Product ID on the Bottom Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Figure 3-1: CPM Interrupt Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Figure 4-1: MPC8560 To SDRAM Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Figure 5-1: Serial Cable Assembly (Emerson part number C00003555-xx) . . . . . . . . . . . . . . . . . . 5-2
Figure 6-1: Data Flow Between Framer and MPC8560 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
Figure 7-1: MPC8560 PCI Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
Figure 7-2: PMC Interface Connectors (P11-P14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
Figure 8-1: Boot Device Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10
Figure 8-2: Clock and Sync Registers Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13
Figure 10-1: DMC Component Map, Top and Bottom (rev.01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
Figure 10-2: P1 PCB-To-PCB Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
Figure 10-3: DMC P2 USB Mini-B Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
Figure 10-4: DMC P3 JTAG/COP Header. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
Figure 10-5: DMC P4 JTAG Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
Figure 10-6: DMC Jumper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
Figure 10-7: DMC Location on Pm8560. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
Figure 10-8: Serial Number and Product ID on Bottom Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10
Figure 11-1: Example Monitor Start-up Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
Figure 11-2: Power-up/Reset Sequence Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3

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10006609-03 Pm8560 User’s Manual ix
Tables
Table 1-1: Address Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Table 1-2: Regulatory Agency Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Table 1-3: Technical References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Table 2-1: Circuit Board Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Table 2-2: Environmental Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Table 3-1: Pm8560 CPU Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Table 3-2: External Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Table 3-3: MPC8560 Port Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Table 3-4: MPC8560 Chip Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Table 4-1: NVRAM SROM Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Table 4-2: DDR SDRAM Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Table 5-1: Front Panel Serial Port Connector P17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Table 5-2: Serial Cable Wiring Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Table 5-3: Baud Rates for 33 MHz and 66 MHz Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Table 6-1: Transmit Waveform Value Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
Table 6-2: Connector P14 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
Table 7-1: Pm8560 Vital Product Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Table 7-2: Power-on Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
Table 7-3: Interrupt Connections for Pm8560 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
Table 7-4: P11, P12, and P13 Connector Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
Table 8-1: PLD Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Table 9-1: MDIO/MDC Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
Table 9-2: Ethernet Port Address Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
Table 9-3: Ethernet Port Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2
Table 10-1: DMC Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1
Table 10-2: DMC P1 Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
Table 10-3: DMC P2 Connector Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
Table 10-4: DMC P3 JTAG/COP Header Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
Table 10-5: DMC P4 JTAG Header Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
Table 10-6: DMC Jumper Port Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
Table 11-1: Post Diagnostic Results—Bit Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4
Table 11-2: Monitor Address Per Flash Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
Table 11-3: Standard Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-23
Table 11-4: Optional Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-24

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10006609-03 Pm8560 User’s Manual i
Registers
Register 7-1: PCI1 Vendor and Device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Register 7-2: MPC8560 PCI Configuration Space Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4
Register 8-1: Product ID (PIDR), 0x00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
Register 8-2: Hardware Version (HVR), 0x04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
Register 8-3: PLD Version (PVR), 0x08 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
Register 8-4: PLL Configuration (PLLCR), 0x0C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
Register 8-5: Hardware Configuration 1 (HCR1), 0x14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
Register 8-6: Jumper Settings (JSR), 0x18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
Register 8-7: LED (LEDR), 0x1C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
Register 8-8: Reset Event (RER), 0x20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
Register 8-9: Reset Command (RCR), 0x24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7
Register 8-10: PCI Reset Out Enable (PROE), 0x28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
Register 8-11: PCI Status (PSR), 0x2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9
Register 8-12: Boot Device Failover Mechanism (BDFM), 0x30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-10
Register 8-13: Miscellaneous Control (MISC), 0x34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11
Register 8-14: CT Bus Status (CTSR), 0x38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12
Register 8-15: NETREF Control (NRCR), 0x40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14
Register 8-16: Framer Clock Source (FCSR), 0x44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-14
Register 8-17: MT4095 System Synchronizer Control (SSCR), 0x48 . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15
Register 8-18: SYNC Source (SSR), 0x4C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16
Register 8-19: Primary Clock Source (PCSR), 0x50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17
Register 8-20: Secondary Clock Source (SCSR), 0x54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
Register 8-21: TCLK Source (TCSR), 0x58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19
Register 8-22: RCLK Source (RCSR), 0x5C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19
Register 8-23: SPD Row Column (SPDRC), 0x60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20
Register 8-24: SPD CAS Latency Refresh (SPDCLR), 0x64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21
Register 8-25: SPD SDRAM Cycle Time for CAS Latency (SPDCT), 0x68 . . . . . . . . . . . . . . . . . . . . . . . 8-21
Register 8-26: SPD Minimum Row Precharge Time (SPDMRP), 0x6C . . . . . . . . . . . . . . . . . . . . . . . . . 8-22
Register 8-27: SPD Minimum Row Delay Between Activations (SPDMDBRA), 0x70 . . . . . . . . . . . . 8-23
Register 8-28: SPD Minimum Row Delay Between RAS-to-CAS Assertions (SPDMDBRCA), 0x74 . 8-23
Register 8-29: SPD Minimum Active-to-Precharge (SPDMAP), 0x78 . . . . . . . . . . . . . . . . . . . . . . . . . 8-24
Register 8-30: SPD Minimum Auto-Refresh to Active/Auto-Refresh (SPDMAA), 0x7C . . . . . . . . . . 8-24
Register 8-31: SPD Write Recovery Time (SPDWRT), 0x80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25
Register 8-32: SPD Internal Write-to-Read Command Delay (SPDIWR), 0x84 . . . . . . . . . . . . . . . . . 8-25

Pm8560 User’s Manual 10006609-03
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10006609-03 Pm8560 User’s Manual 1-1
Section 1
Overview
The Pm8560 is a single width PCI Telecom Mezzanine Card (PTMC) designed to provide
high-speed E1 and T1/J1 interfaces. The design is based on the Freescale™ Semiconductor
MPC8560 PowerQUICC™ III microprocessor.
The Pm8560 complies with Configuration 2 of the PCI Industrial Computer Manufacturers
Group (PICMG®) 2.15 PTMC Specification.
COMPONENTS AND FEATURES
The following is a brief summary of the Pm8560 hardware components and features:
CPU: The Freescale MPC8560 PowerQuicc III embedded Book E compatible core operates up to
800 MHz. Features include: RISC CPM operating up to 333 MHz, 32-kilobyte L1 instruction
cache, 32-kilobyte L1 data cache, and 256 kilobytes on-chip L2 cache.
SDRAM: The Pm8560 is populated with up to 512 megabytes of Double Data Rate (DDR) Synchro-
nous Dynamic Random Access Memory (SDRAM) and provides Error-correcting Code
(ECC). DDR interface operating speed is 133 MHz when the processor core is at 800 MHz.
Flash: The Pm8560 is capable of booting from either an 8-bit, 32-pin PLCC ROM socket on the
Development Mezzanine Card (DMC), or from the 16-bit on-card soldered flash (default)
region.
Serial In/Out: An EIA-232 console serial port from MPC8560 is available at the front panel, connector P14,
and the DMC; or connector P13 when a CT bus is present. This port is for boot flash pro-
gramming and initial setup. A second serial port is routed out connector P14.
Framer: The Pm8560 supports eight links using one IDT82P2288 octal T1/E1/J1 (long haul/short
haul) framer and line interface unit (LIU) transceiver.
CT Bus Clocks: Optionally, the Pm8560 can provide computer telephony (CT) bus clocking. The supported
clocks include C8A, C8B, FRAMEA, FRAMEB, NETREF1, and NETREF2.
PCI: The PCI bus operation is capable of 32-bit/66 MHz and is routed out connector P12.
The PCI bus clock must be between 25-33 MHz or 50-66 MHz. Operation is not guaranteed
outside of these ranges.
I2C Bus: The Pm8560 I2C bus consists of the following devices: MPC8560 configuration Serial Read-
Only Memory (SROM), Real-Time Clock (RTC), and two serial EEPROMs.
Ethernet: A 10/100/1000 Ethernet port is available through the front panel RJ45 connector.
RTC: The Real-Time Clock is an ST®Microelectronics M41T00 Serial Access Timekeeper®. This
device has power sense circuitry, and uses eight bytes of non-volatile RAM for the clock/cal-
endar function. The M41T00 is powered from the +3.3 volt rail during normal operation;
and uses a single, super capacitor which provides a minimum two hour backup.

Overview: Functional Overview
Pm8560 User’s Manual 10006609-03
1-2
Baseboard: The Katana752i is an input/output (I/O) processing blade for use in a CompactPCI (cPCI)
Packet Switched Backplane (cPSB) and is fully compliant with the cPCI Hot Swap Specifica-
tion (see reference in Table 1-3). See the Emerson Katana752i User’s Manual for more infor-
mation.
Transition Model (TM): TMcSpanP8E provides four or eight rear long- or short-haul T1 or E1 links. See the Emerson
TMcSpanP8E User’s Manual for more information.
Development Mezzanine Card:
An optional Development Mezzanine Card (DMC) is available for software development.
The DMC adds access to the 32-pin PLCC ROM/flash socket, MPC8560 JTAG header, CPLD
header, four LEDs, and four user-defined jumpers.
FUNCTIONAL OVERVIEW
The following block diagram provides a functional overview for the Pm8560:

Overview: Functional Overview
10006609-03 Pm8560 User’s Manual 1-3
Figure 1-1: General System Block Diagram
The Pm8560 monitor can boot from either the DMC socketed PLCC device or the soldered
flash (default). Based on the DMC jumper JP2 (see “DMC Jumpers and LEDs”), either the
DMC socket or the soldered flash is mapped to the boot bank at FFF0,000016. Information on
particular portions of the memory map can be found in later sections of this manual, see
Table 1-1.
8560
CFG ROM
RTC
Serial
EEPROM
Serial
EEPROM
LEDs
P12
P13
P14
P11
Development Mezzanine
Card (DMC)
Jum ers
LEDs (4)
COP Header
ROM Socket
CPLD Header
Magnetics
10/100/
1000 PHY
EIA-232
Serial
Reset
ETH
1
L
N K
A C
T
DMC Connector
Logic
Reset Control
Chip Select
Registers
Clock Control
Clock
Recovery
Flash
32 M
E1/T1/J1
Transceiver
Power
Monitor
DDR SDRAM
256/512 M
MPC8560
PowerQuicc III
Processor
Serial
EEPROM

Overview: Functional Overview
Pm8560 User’s Manual 10006609-03
1-4
Figure 1-2: Memeory Map
8000,0000
A100,0000
E000,0000
E200,0000
E808,0000
E810,0000
FFFF,FFFF
Hex Address
0000,0000
PCI Memory
(256 MB)
IDT82P228x SCT Registers
(4 KB)
Soldered Flash
(32 MB)
FFF0,0000
CPLD Registers
(512 KB)
Boot Bank
( 1 MB)
Reserved
Reserved
MPC8560 Registers
(1 MB)
FDF0,0000
FE00,0000
DDR SDRAM
(256 to 512 MB)
2000,0000
Reserved
A000,0000
Reserved
E800,8000
E800,0000
Reserved
Reserved
PCI I/O
(16 MB)
Reserved
Socket
(if DMC installed512 KB)
E880,0000
E888,0000
Hex Address
E808,0000
SPD Row Column
SPD CAS LAT Refresh
SPD Minimum Row Delay Activations
SPD Write-to-Read Command Delay
SPD Write Recovery Time
E808,0018
E808,001C
E808,0024
E808,0028
SPD Minmum Active-to-Precharge
E808,0020
SPD SDRAM Cycle Time for CAS/LAT
SPD Minimum Row Precharge
SPD Minimum Delay RAS to CAS
SPD Minimum Auto-Refresh to Active
E808,0004
E808,0008
E808,000C
E808,0010
E808,0014
E808,002C
E808,0030
E808,0034
E808,0038
E808,003C
E808,0040
E808,0044
E808,0048
E808,004C
E808,0050
E808,0054
E808,0058
E808,005C
E808,0060
E808,0064
E808,0068
E808,006C
E808,0070
E808,0074
E808,0078
E808,007C
E808,0080
E808,0084
RCLK Source
TCLK Source
Secondary Clock Source
Primary Clock Source
SYNC Source
System Synchronizer Control
Framer Clock Source
NETREF Control
CT Bus Status
Miscellaneous Control
Boot Device Failover Mechanism
PCI Status
PCI Reset Out Enable
Reset Command
Reset Event
LED
Jum er Setting
Hardware Configuration 1
PLL Configuration
PLD Version
Hardware Version
Product Identification (ID)
Reserved
Reserved

Overview: Functional Overview
10006609-03 Pm8560 User’s Manual 1-5
Table 1-1: Address Summary
Hex Physical
Address:
Access
Mode: Register Description:
See
page:
FFF0,0000 R/W Boot Area (1 MB) —
FE00,0000 —reserved —
FDF0,0000 R/W MPC8560 registers (1 MB) 3-3
E888,0000 —reserved —
E880,0000 R/W Socket, if DMC installed (512 KB) 10-7
E810,0000 —reserved —
E808,0084 R Serial Presence Detect (SPD) Internal Write-to-Read
Command Delay (SPDIWR)
8-25
E808,0080 R SPD Write Recovery Time (SPDWRT) 8-25
E808,007C R SPD Minimum Auto-refresh to Active (SPDMAA) 8-24
E808,0078 R SPD Minimum Active-to-Precharge (SPDMAP) 8-24
E808,0074 R SPD Minimum Delay Between RAS/CAS Assertions
(SPDMDBRC)
8-23
E808,0070 R SPD Minimum Delay Between Row Activations
(SPDMDBRA)
8-23
E808,006C R SPD Minimum Row Precharge Time (SPDMRP) 8-22
E808,0068 R SPD SDRAM Cycle Time for CAS LAT (SPDCT) 8-21
E808,0064 R/W SPD Channel Associated Signaling (CAS) Latency (LAT)
Refresh (SPDCLR)
8-21
E808,0060 R/W SPD Row Column (SPDRC) 8-20
E808,005C R/W RCLK Source (RCSR) 8-19
E808,0058 R/W TCLK Source (TCSR) 8-19
E808,0054 R/W Secondary Clock Source (SCSR) 8-18
E808,0050 R/W Primary Clock Source (PCSR) 8-17
E808,004C R/W SYNC Source (SSR) 8-16
E808,0048 R/W MT9045 System Synchronizer Control (SSCR) 8-15
E808,0044 R/W Framer Clock Source (FCSR) 8-14
E808,0040 R/W NETREF Control (NRCR) 8-14
E808,003C —reserved —
E808,0038 R/W CT Bus Status (CTSR) 8-12
E808,0034 R/W Miscellaneous Control (MISC) 8-11
E808,0030 R Boot Device Failover Mechanism (BDFM) 8-9
E808,002C R/W PCI Status (PSR) 8-8
E808,0028 R/W PCI Reset Out Enable (PROE) 8-8
E808,0024 R/W Reset Command (RCR) 8-7
E808,0020 R Reset Event (RER) 8-6
E808,001C R/W LED (LEDR) 8-5
E808,0018 R Jumper Setting (JSR) 8-5

Overview: Additional Information
Pm8560 User’s Manual 10006609-03
1-6
ADDITIONAL INFORMATION
This section lists the Pm8560 hardware’s regulatory certifications and briefly discusses the
terminology and notation conventions used in this manual. It also lists general technical
references.
Mean time between failures (MTBF) has been calculated at 780,138 hours using the Telcor-
dia SR-332, Issue 1, Reliability Prediction for Electronic Equipment at 30°C.
Product Certification
The Pm8560 hardware has been tested to comply with various safety, immunity, and emis-
sions requirements as specified by the Federal Communications Commission (FCC), Under-
writers Laboratories (UL) Inc., and others. The following table summarizes this compliance:
Table 1-2: Regulatory Agency Compliance
E808,0014 R Hardware Configuration 1 (HCR1) 8-4
E808,0010 —reserved —
E808,000C R/W Phase-locked Loop Configuration (PLLCR) 8-3
E808,0008 R PLD Version (PVR) 8-3
E808,0004 R Hardware Version (HVR) 8-2
E808,00001R Product Identification (PIDR) 8-2
E800,8000 —reserved —
E800,0000 R/W IDT82P228x SCT (4 KB) —
E200,0000 —reserved —
E000,0000 R/W Soldered Flash (32 MB) 4-1
A100,0000 —reserved —
A000,0000 R/W PCI I/O Space (16 MB) 7-2
8000,0000 R/W PCI Memory Space (256 MB) 7-2
2000,0000 —reserved —
0000,0000 R/W DDR SDRAM (256 to 512 Mb) 4-3
1. CPLD registers occupy 512 kilobytes of space.
Type: Specification:
Safety IEC60950/EN60950 – Safety of Information Technology Equipment
(Western Europe)
UL60950-1, CSA C22.2 No. 60950 Third Edition – Safety of Information
Technology Equipment, including Electrical Business Equipment (BI-
National)
Global IEC – CB Scheme Report IEC 60950, all country deviations
Hex Physical
Address:
Access
Mode: Register Description: (continued)
See
page: