EPOX P55-VP 2 User manual

Introduction1-1
Chapter 1
Introduction
R
The P55-VP 2mainboard is a high performance system hardware based
on Intel Pentium processor and is equipped with three PCI slots, four
standardISAslots,SuperMulti-I/O controlleranddual portPCI-IDE
connectorsforthefutureexpansion.Thehardwaredimensionis220mmx
230mmwithafour-layer-designtechnology.
Specification
VIAApolloVPXPCIsetchipset.
Intel Pentium Processor, AMD K5/K6 & Cyrix M1 operating at75 ~ 200
MHz andP55C with321 ZIF socket 7 and scalability to accept faster
Processors in the future.
Supports up to 192 MegaBytes of DRAM (a minimum of 8 MB) on board
(72-pinSIMMx4&168-pinDIMMx1). BIOSwillautometicallydetectand
configure FP/EDO and Synchronous DRAM (Refer to Chapter 2-3 System
MemoryConfiguration).
Supports Onboard Pipelined Burst (synchronous) L2WriteBack/Through
Cache.Thecachememorycombinationcanbe256KB/512KB(32KB*32,
64KB*32SRAM,respectively).
Supports four 16 bit ISA slots and three 32 bit PCI slots and provides two
independent high performance PCI IDE interfaces capable of supporting
PIOMode3/4andUltra-DMA33devices.TheP55-VP2supportsthreePCI
Bus Masters and a jumperless PCI INT# control scheme which reduces
configurationconfusion whenplugging in PCI I/O controller card(s).
SupportsATAPI(e.g.CD-ROM)devicesonbothIDEinterfaces.
Supports1floppyport,1parallelport(EPP,ECPport), 2 serial ports (16550
FastUARTcompatible)and1USB Connector.
Supports a PS/2 style mouse and standard AT style keyboard connectors.
SupportsAwardPlug & Play BIOS . TheBIOS is stored in Flash EPROM
form. It provides better upgradeability for the system.
Supports CPU Hardware sleep and SMM (System Management Mode).
P55-VP2utilizes Lithiumbatterywhichprovidesenvironmentalprotection
and longer battery life.
R

1-2 P55-VP 2
P55-VP 2 Layout
BIOS
PCI#1
<
BIOS
PRINTER
W83877F
5
1
82C585
VIA
VIA
K/B
CONN.
Power Conn.
J1
DIMM1 SIMM1 SIMM2 SIMM3 SIMM4
COM2COM1
J2 1
5
3 1 JP1
FDD CONN.
PCI#3 PCI#2
64K*32 64K*32
82C587
VIA
82C587
VIA
Figure1-1
HD-LED+
G-LED+ TB-LED+
SPEAKER
KEYLOCK J5
5 1 3 1 3 1
JP8 JP7
J3
JP3 1
3
TAG SRAM
\Bank 4,5 / \ Bank 2,3 /
Bank 0,1
Primary IDE
Secondary IDE
SLEEP
RESET
1 2
7 8
JP6
JP2-2 JP2-1
JP2-3
JP2-4
82C586A
JP4 1
3
Socket 7

Hardware Design 2-1
2-1 Mainboard Layout
TheP55-VP2isdesignedwithVIAApolloVPXPCIset chipset which isdevel-
oped by VIA Corporation to fully support Pentium Processor PCI/ISA system. The
VIAApolloVPXPCIsetchipsetcanincreaseintegrationandimproveperformance
designs.The chipset provides an integrated IDEcontroller with two high perfor-
manceIDEinterfacesforuptofourIDEdevices(harddevices,CD-ROM device,etc).
TheWinbondW83877FSuperI/Ocontroller providesthestandardPCI/Ofunction:
floppyinterface,two16ByteFIFOserialportsandEPP/ECPcapableparallelport.
The P55-VP 2 layout is shown in the previous page for user's reference. Care must
betakenwheninsertingmemorymodules,insertingCPUorevenpluggingPCIcard
into associated slots to avoid damaging any circuits or sockets on board. A cooling
fanisstronglyrecommendedwheninstallingP54C/P54CTB/P55C/K5/K6/6x86/6x86L/
M2 processor due to possible overheat.
TheP55-VP2supportsaminimumof4MBandamaximumof192MBofSystem
MemorywhileL2Cachecanbe256KB/512KBsynchronousSRAMOnboardto
increasesystemperformance.(RefertoPage2-6CacheMemoryConfigurationfor
thedetails.)
TheP55-VP 2supports standard Fast Page, EDO(ExtendedData Out or Hyper
Page Mode) or synchronous DRAM.The P55-VP 2provides four 72-pin SIMM
andone168-pin DIMM sites for memory expansion.Thesockets support 1M x
32(4MB),2Mx32(8MB),4Mx32(16MB),and8Mx32(32MB)single-sidedordouble-
sidedmemory modules.The memorytimingrequires70ns Fastpagedevicesor60
nsEDODRAM.(DRAMModulesmaybeparity[x36]ornon-parity[x32].
TheP55-VP2supportstwoOnboardPCIIDEconnectors,andautomaticallydetects
IDEharddisktypebyBIOSutilityautomatic.
The P55-VP 2supports Award Plug & PlayBIOSfor the ISA and PCI cards. The
BIOScanbelocated inFlashEPROMwhichcanreplace BIOS codeeasilyifneces-
sary.
Chapter 2
Hardware design
R

2-2 P55-VP 2
2-2ConnectorsandJumpers
This section describes all connectors and jumpers equipped in the mainboard. Please
refer to Figure 1-1for location of each connector and jumper.
1.Power LED(+)
2.N/C
3.GND
4.Keylock
5.GND
1
5
4
1.Speaker
2.N/C
3.GND
4.GND
J5 1
Power Saving LED indicator - LED ON when system is
in any Saving mode.
Reset Switch - Closed to restart system.
Speaker - connect to the system's speaker for beeping.
KeyLock-Keyboardlockswitch&PowerLEDconnector.
Sleep/Resume switch: Closedtoentersleepmode.
Akeystrobeormousemovement(mousedriverexists).Will
instantly "wake up" the system.
TurboLEDindicator-LEDONwhenhigherspeedisselected.
IDELEDindicator-LEDONwhenOnboardPCIIDE
Harddisksactivate.
+
+
+# There is no deturbo function so that the turbo LED is always ON.
J3 The Power Supply (+12V) of the CPU Cooling FAN
1.GND
2.+12V
3.GND
3
1

Hardware Design 2-3
1
5
J1 PS/2 MOUSE CONNECTOR
1.RED wire
2.BLUE wire
3.GREEN wire
4.NC
5.YELLOW wire
1
J2 IrDA/ASKIRCONNECTOR
5
1.VCC
2.NC
3.IRRX
4.GND
5.IRTX
JP1 EPROMBIOSSelection
1-2:5VFlashEPROM.(SST,Winbond).
2-3:12VFlashEPROM(Intel).
JP3 CPUVcorevoltageselection
1-2:2.9VForAMDK6-PR166/200
2-3:2.8VForPentiumMMXProcessor&Cyrix6x86L
Open: 3.2V (Reserved)
JP4 CPUTypeSelection
1-2:Auto(forIntelPentiumMMXProcessor,AMDK5/
K6andCyrix6x86/6x86L/M2)
2-3:Manual(forIntelPentiumProcessor)
3
1
3
1
3
1
JP6 DIMM Working Voltage Selection
1-2, 3-4 : 5V
5-6, 7-8 : 3.3V (Default)
(Refer to 2-3 : Memory Configuration for the detail)
1 2
7 8

2-4 P55-VP 2
6x86/L-PR120+
CPU TYPE JP2-1 JP2-2 JP2-3 JP2-4 JP7 JP8
6x86/L-PR150+
6x86/L-PR166+ ON
OFF
OFF
ON
IBM/ Cyrix 6x86(L)/6x86MXInstallation
*CPUOo.isCPUoperationat75,90,100MHz,andetc.
ON ON
ON
ON
OFF
OFF
ON
6x86/L-PR133+
6x86/L-PR200+
6x86/L-PR200+
2-3 1-2
OFF OFF
OFF
OFF
ON
ON
OFF OFF
ON
ON
OFF
OFF
ON
Note 1
Note 2
Note1:IBM/CyrixPR200withsynchornousPCI
Note2:IBM/CyrixPR200withasynchornousPCIforPCI2.0
spec. Bus Master Device
* Clock is System Clock.
Intel Pentium Processor / Pentium MMX Processor
/AMD K5 /K6 Installation
2-3 2-3
1-2 2-3
2-3 1-2
1-2 1-2
RR
ON OFF ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON ON
OFF
ON
OFF ON
ON
OFF
ON
OFF ON
ON
ON
ON
ON
ON
ON
ON
ON
Clock/CPU Op. JP2-1 JP2-2 JP2-3 JP2-4 JP7 JP8
66/200 MHz
JP8 JP7
3 1 3 1
60/90 MHz
66/100 MHz
66/133 MHz
60/150 MHz
60/180 MHz
66/166 MHz
JP2 1 2 3 4
50/75 MHz
60/120 MHz
OFF
6x86MX-PR200
6x86MX-PR166 ON
OFF
OFF
ON ON
ON
OFF
OFF6x86MX-PR166
6x86MX-PR200
6x86MX-PR200
2-3 2-3
OFF OFF
OFF
ON
ON
OFF OFF
ON
ON
OFF
OFF
ON
Note 1
Note 2
66MHz x 2
75MHz x 2
75MHz x 2
60MHz x 2.5
66MHz x 2.5

Hardware Design 2-5
*6x86-PR120+=50MHzx2/100MHz,6x86-PR133+=55MHzx2/110MHz
*6x86-PR150+=60MHzx2/120MHz,6x86-PR166+=66MHzx2/133MHz
*6x86-PR200+=75MHzx2/150MHz
2-3SystemMemoryConfiguration
The P55-VP 2 supports different type of settings for the system memory. The
followingfiguresand table providesallpossiblememorycombinations. (Pleaserefer
toAppendixC:MemoryConfigurationTableforthedetails).
3
1
JP3 CPUVcorevoltageselection
1-2:2.9VForAMDK6-PR166/200
2-3:2.8VForPentiumMMXProcessor&Cyrix6x86L
Open:3.2V(Reserved)
JP4 CPUTypeSelection
1-2:Auto(forIntelPentiumMMXProcessor,AMDK5/K6
andCyrix6x86/6x86L/M2)
2-3:Manual(for IntelPentiumProcessor)
1
3
>
>
>
DIMM
SIMM4
SIMM2
SIMM3 BANK 4,5 5V FP / EDO DRAM
BANK 2,3 5V FP / EDO DRAM
3V Synchronous DRAM
or 3V FP / EDO DRAM
BANK 0,1
NOTE :1.P55-VP2supports both FastPageDRAMandEDO DRAM SIMMs,but
they cannot be used in the same memory bank.
2.TheKEYZOOMoftheDIMMsocketis3.3V/Unbuffered.
SIMM1
LEFT KEY ZONE CENTER KEY ZONE
DRAM chip

2-6 P55-VP 2
2-4CacheMemoryConfiguration
The second level (L2) of cache is installed in the mainboard to increase the system
performance. The P55-VP 2 supports different type of combinations for the cache
installation.Pleaserefer to thefollowingconfigurationsforthe details.
DATA SRAM
64K*32
U19 U20
SYN.CACHE On Board
256KB 32K*32 x 2
512KB 64K*32 x 2
Size (U19,U20)
TAG SRAM
U21
The P55-VP 2supports168-pinDIMMmoduletoextend system memory size. You
caninstall(3.3V /Unbuffered)FastPage,EDO orSynchronousDRAM.Besides, to
support5VFP and EDO DRAM with DIMMsocket,TheP55-VP 2 provides JP6 to
allow user using 3.3V/Unbuffered DIMM module with 5V FP and EDO DRAM
chips. The setting of the JP6 is shown as follows:
When you have a DIMM module to plug into a 168-pin dual readout connnector,
youmustmakesurethattheKEYZOOMoftheDIMMmoduleis3.3V/Unbuffered
and supports Intel Pentium Processor System.
JP6 DIMM Working Voltage Selection
1-2, 3-4 : 5V
5-6, 7-8 : 3.3V (Default)
1 2
7 8
64K*32
R

Hardware Design 2-7
2-5IntegratedPCIBridge
The P55-VP 2 utilizes PCIsetchipsettosupportIntelPentium ProcessorPCI/ISA
system.TheVIAApolloVPXPCIsetchipsetconsistsofthe82C585VPsystem
controller(TSC),two82C587VPDataPath(TDP)devices,andone82C586APCIISA/
IDEAcceleratorbridge chip. Itprovidesaninterfacewhich translates CPUcycleinto
PCIbuscycle,andPCIburstread/writecapability.Inaddition,itprovideshigh
performancePCIarbitortosupportfourPCIMasters,RotatingPriorityMechanism,
andHiddenArbitrationSchemeMinimizesArbitrationOverhead.
TherearefourinterruptsineachPCIslot:INTA#,INTB#,INTC#,andINTD#.Since
the P55-VP 2adapts the PCI auto-configuration with the system BIOS Setup utility.
Whenthesystemis turned on after adding a PCI add-incard,theBIOS automatically
configure interrupts, DMA channels, I/O space, and other paramaters. You do not
have to configure jumpers or worry about potential resource conflicts. Because PCI
cards use the same interrupt resource as ISA cards, you must specify the interrupt
used by ISA add-in cards in the BIOS Setup utility.
However, if a "Legacy card" (such as plugging a paddle card and cable into an ISA
slot)ispluggedinthesystem,modificationinthe ROMSETUPUTILITYbecomes
necessary.Firstofall,youmustenterPCICONFIGURATIONSETUPutilityfrom
theROMSETUPUTILITYmainmenutoset"ISA"forthe"PCIIDEIRQMAPTO
Secondly,youmustentertheCHIPSETFEATURESSETUPUTILITYfromtheROM
SETUPUTILITYmainmenuandset"Disable"forthe"OnboardPrimaryPCIIDE
andtheOnboardSecondaryPCIIDE.WhenyouplugPCI/ISAIDEcardsintothe
system,Youshouldselect"Disabled"fortheOnboardPrimaryandSecondaryPCI
IDEfromtheCHIPSETFEATURESSETUPUTILITYtoo.
You can set the system interrupt request (IRQ) on some "Legacy cards" which have
on paddle card and cable. (refer to user's manual of the card) to a proper system IRQ
level (In general, card's Primary is assigned to INTA and Secondary is assigned to
INTB). If the card is plugged into slot 1(marked PCI#1), you cannot use second slot
(markedPCI#2) becausetheSecondaryINTsignaltakesINTBfromtheslot(refer to
Page3-12forcircuitdiagram).Theuserthenentersthe PCICONFIGURATION
SETUPutilityfromthe ROMSETUPUTILITYmainmenuandset"PCI-Slot1"for
the"PCI IDE IRQMAPTO(Thisdependsonthe slot#wheretheLegacy cardis
plugged).
.
R

AWARD BIOS 3-1
CHAPTER 3
AWARD BIOS SETUP
Award'sROMBIOSprovidesabuilt-insetupprogramwhichallowsusertomodifythe
basicsystemconfigurationandhardwareparameters.Themodifieddatawillbestored
inabattery-backedCMOSRAMsodatawillberetainedevenwhenthepoweristurned
off.Ingeneral,theinformationsavedintheCMOSRAMstaysunchangedunlessthere
isaconfigurationchangeinthesystem,suchasaharddrivereplacementoranewdevice
installation.
If this does happen you will need to reconfigure your configuration parameter.
To Enter Setup Propgram
Poweronthecomputerandpress<Del>keyimmediately.ThiswillbringyouintoBIOS
CMOSSETUPUTILITY.
ROMPCI/ISABIOS(2A5LDPA9)
CMOSSETUPUTILITY
AWARDSOFTWARE,INC.
STANDARD CMOS SETUP SUPERVISOR PASSWORD
BIOS FEATURES SETUP USER PASSWORD
CHIPSET FEATURES SETUP IDE HDD AUTO DETECTION
POWER MANAGEMENT SETUP HDD LOW LEVEL FORMAT
PNP/PCI CONFIGURATION SAVE & EXIT SETUP
INTEGRATED PERIPHERALS EXIT WITHOUT SAVING
LOAD SETUP DEFAULTS
ESC : QUIT : SELECT ITEM
F10 : Save & Exit Setup (Shift)F2 : Change Color
Time, Date, Hard Disk Type...
Figure 3-1 CMOS SETUP UTILITY
Themenudisplaysallmajorselectionitems. Select the item you need to reconfigure.
The selection is made by moving cursor (press any direction key ) to the item and
press the 'Enter' key. An on-line help message is displayed at the bottom of the
screen as the cursor is moving to various items which provides a better understand-
ingof each function. Whena selection is made,the menu of selecteditem will appear
so the user can modify the associated configuration parameters.