Analog Devices SHARC ADSP-21368 Application guide

a
ADSP-21368 SHARC®Processor
Hardware Reference
Includes ADSP-21367, ADSP-21369,
ADSP-21371, ADSP-21375
Revision 1.0, September 2006
Part Number
82-000100-01
Analog Devices, Inc.
One Technology Way
Norwood, Mass. 02062-9106

Copyright Information
© 2006 Analog Devices, Inc., ALL RIGHTS RESERVED. This
document may not be reproduced in any form without prior,
express written consent from Analog Devices, Inc.
Printed in the USA.
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Trademark and Service Mark Notice
The Analog Devices logo and icon bar, Blackfin, EZ-KIT Lite,
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All other brand and product names are trademarks or service marks
of their respective owners.

ADSP-21368 SHARC Processor Hardware Reference iii
CONTENTS
PREFACE
Purpose of This Manual ............................................................... xxxi
Intended Audience ....................................................................... xxxi
Manual Contents ........................................................................ xxxii
What’s New in This Manual ....................................................... xxxiv
Technical or Customer Support ................................................... xxxv
Supported Processors .................................................................. xxxvi
Product Information .................................................................. xxxvi
MyAnalog.com .................................................................... xxxvii
Processor Product Information ............................................. xxxvii
Related Documents ............................................................ xxxviii
Online Technical Documentation ......................................... xxxix
Printed Manuals ....................................................................... xli
Conventions ................................................................................ xliii
INTRODUCTION
Design Advantages ........................................................................ 1-1
Architectural Overview ................................................................. 1-6
Processor Core ......................................................................... 1-7

Contents
iv ADSP-21368 SHARC Processor Hardware Reference
Processor Peripherals ............................................................... 1-7
I/O Processor ..................................................................... 1-7
Digital Audio Interface (DAI) ............................................. 1-9
Digital Peripheral Interface (DPI) ..................................... 1-10
Development Tools ..................................................................... 1-10
Differences From Previous Processors .......................................... 1-11
I/O Architecture Enhancements ............................................ 1-11
Instruction Set Enhancements ............................................... 1-12
I/O PROCESSOR
General Procedure for Configuring DMA ...................................... 2-2
Core Access to IOP Registers ........................................................ 2-3
Configuring IOP/Core Interaction ................................................ 2-6
Interrupt-Driven I/O .............................................................. 2-6
Interrupt Latency in Interrupt-Driven Transfers ................ 2-11
Polling/Status-Driven I/O ..................................................... 2-12
DMA Controller Operation .................................................. 2-13
Chaining DMA Processes .................................................. 2-14
Transfer Control Block Chain Loading (TCB) ................... 2-16
Setting Up DMA Channel Allocation and Priorities ............... 2-18
Managing DMA Channel Priority ..................................... 2-19
DMA Bus Arbitration ....................................................... 2-20
Setting Up DMA Parameter Registers .......................................... 2-24
DMA Transfer Direction ....................................................... 2-24
Data Buffer Registers ............................................................ 2-25

ADSP-21368 SHARC Processor Hardware Reference v
Contents
Port, Buffer, and DMA Control Registers ............................... 2-26
Addressing ............................................................................ 2-29
External Port DMA ..................................................................... 2-35
Setting Up and Starting Chained DMA .................................. 2-36
Delay Line DMA ................................................................... 2-38
Serial Port DMA ......................................................................... 2-40
Setting Up and Starting Chained DMA .................................. 2-40
Inserting a TCB in an Active Chain ....................................... 2-41
Serial Peripheral Interface DMA .................................................. 2-42
Setting Up and Starting Chained DMA over the SPI .............. 2-42
UART DMA ............................................................................... 2-44
Notes On Using DMA With the UART ................................. 2-47
Memory-to-Memory DMA ......................................................... 2-48
Summary .................................................................................... 2-48
Programming Example ................................................................ 2-49
EXTERNAL PORT
External Memory Interface ............................................................ 3-2
External Memory Interface on the ADSP-2137x Processors ...... 3-3
Direct Execution of Instructions From External Memory ..... 3-3
Throughput and Instruction Execution Rate ........................ 3-3
Location of Interrupt Vector Table (IVT) ............................ 3-4
Instruction Cache ............................................................... 3-5
Instruction Storage and Packing .......................................... 3-9
Register Configurations for External Memory Execution .... 3-15

Contents
vi ADSP-21368 SHARC Processor Hardware Reference
EMI Registers and Signals ..................................................... 3-16
External Port Arbitration Logic ......................................... 3-18
Channel Freezing .............................................................. 3-18
Managing Data Paths ........................................................ 3-18
External Memory Interface Pins ............................................ 3-19
Asynchronous Memory Interface ................................................. 3-20
AMI Timing Control .................................................................. 3-21
Wait States ............................................................................ 3-21
Bus Idle Cycles ...................................................................... 3-22
Bus Hold Cycles .................................................................... 3-23
Setting AMI Modes .................................................................... 3-24
External Memory Reads ........................................................ 3-25
Data Packing .................................................................... 3-25
External Memory Writes ....................................................... 3-26
Data Packing .................................................................... 3-27
Read/Write Throughput ........................................................ 3-28
External Access Addressing .................................................... 3-28
External Port DMA ............................................................... 3-30
Booting Through the AMI .................................................... 3-30
SDRAM Controller .................................................................... 3-30
Definition of Terms .............................................................. 3-31
Timing External Memory Accesses ......................................... 3-36
Parallel Connection of SDRAMs ........................................... 3-39
SDRAM Control Register (SDCTL) ...................................... 3-39

ADSP-21368 SHARC Processor Hardware Reference vii
Contents
SDRAM Control Status Register (SDSTAT) ........................... 3-49
SDRAM Refresh Rate Control Register (SDRRC) .................. 3-49
SDRAM Initialization ........................................................... 3-51
SDRAM Address Mapping .................................................... 3-51
SDRAM Controller Address Mapping ............................... 3-58
SDC Operation ..................................................................... 3-58
Single Bank Operation ...................................................... 3-60
Multibank Operation (ADSP-2137x Processors) ................ 3-60
Data Mask (DQM) ........................................................... 3-61
SDC Configuration ............................................................... 3-61
SDC Commands ................................................................... 3-63
Load Mode Register .......................................................... 3-64
Single Bank Activation ...................................................... 3-65
Multibank Activation (ADSP-2137x Processors) ................ 3-66
Single Precharge (ADSP-2137x Processors) ........................ 3-66
Precharge All ..................................................................... 3-66
Read/Write ....................................................................... 3-67
Read/Write (ADSP-2137x Processors) ............................... 3-69
Burst Stop (ADSP-2137x Processors) ................................. 3-69
Auto-Refresh ..................................................................... 3-70
Self-Refresh Mode ............................................................. 3-70
No Operation/Command Inhibit ...................................... 3-71
Changing System Clock During Runtime .......................... 3-73

Contents
viii ADSP-21368 SHARC Processor Hardware Reference
SDRAM Timing ................................................................... 3-74
SDRAM Read Optimization ............................................. 3-75
External Memory Access Restrictions ................................ 3-78
Shared Memory Interface ............................................................ 3-79
Shared Memory Bus Arbitration ............................................ 3-79
Bus Arbitration Protocol ................................................... 3-82
Bus Arbitration Priority (RPBA) ....................................... 3-86
Bus Mastership Time-out .................................................. 3-87
Bus Synchronization After Reset ............................................ 3-88
Bus Synchronization Notes ............................................... 3-91
Bus Lock and Semaphores ..................................................... 3-92
Shared Memory Interface Status ........................................ 3-93
Shared Memory and the SDRAM Controller ......................... 3-94
Shared Memory Booting ....................................................... 3-94
DIGITAL AUDIO/DIGITAL PERIPHERAL INTERFACES
Structure of the Interfaces ............................................................. 4-2
DAI/DPI System Design ............................................................... 4-3
Signal Routing Units .................................................................... 4-8
Connecting Peripherals ........................................................... 4-8
Pin Interface ......................................................................... 4-10
Pin Buffers as Signal Output Pins .......................................... 4-11
Pin Buffers as Signal Input Pins ............................................. 4-12
Bidirectional Pin Buffers ....................................................... 4-13

ADSP-21368 SHARC Processor Hardware Reference ix
Contents
Making Connections in the SRUs ................................................ 4-15
DAI/SRU1 Connection Groups ............................................. 4-18
Group A Connections—Clock Signals ............................... 4-19
Group B Connections—Data Signals ................................. 4-25
Group C Connections—Frame Sync Signals ...................... 4-31
Group D Connections—Pin Signal Assignments ................ 4-36
Group E Connections—Interrupts and Miscellaneous
Signals ........................................................................... 4-43
Group F—Pin Enable Signals ............................................ 4-47
DPI/SRU2 Connection Groups ............................................. 4-51
Group A Connections—Input Routing Signals .................. 4-52
Group B Connections—Pin Assignment Signals ............... 4-56
Group C Connections—Pin Enable Signals ...................... 4-60
General-Purpose I/O (GPIO) and Flags ....................................... 4-64
DAI GPIO and Flags ............................................................. 4-64
DPI GPIO and Flags ............................................................. 4-65
Miscellaneous Signals .................................................................. 4-65
DAI/DPI Interrupt Controller ..................................................... 4-65
Relationship to the Core ........................................................ 4-65
DAI Interrupts ...................................................................... 4-66
DPI Interrupts ...................................................................... 4-67
High and Low Priority Latches .............................................. 4-69
Rising and Falling Edge Masks ............................................... 4-70

Contents
x ADSP-21368 SHARC Processor Hardware Reference
Configuring Peripherals Using SRU1 .......................................... 4-71
Configuring the SPORTs ...................................................... 4-71
Configuring the PCGs .......................................................... 4-72
Configuring Peripherals Using SRU2 .......................................... 4-72
Configuring the SPI .............................................................. 4-72
Choosing the Pin Enable for the SPI Clock ....................... 4-72
Configuring the Two Wire Interface ...................................... 4-73
Using the SRU() Macro to Configure
the DAI ................................................................................... 4-76
SERIAL PORTS
Features ........................................................................................ 5-2
Operation Modes ......................................................................... 5-3
Serial Port Signals ......................................................................... 5-5
Serial Port Signal Sensitivity .................................................... 5-9
SPORT Operation Modes ........................................................... 5-10
Standard DSP Serial Mode .................................................... 5-12
Standard DSP Serial Mode Control Bits ............................ 5-13
Clocking Options ............................................................. 5-13
Frame Sync Options ......................................................... 5-13
Data Formatting ............................................................... 5-14
Data Transfers .................................................................. 5-15
Status Information ............................................................ 5-15
Left-Justified Sample Pair Mode ............................................ 5-16
Setting the Internal Serial Clock and Frame Sync Rates ..... 5-17

ADSP-21368 SHARC Processor Hardware Reference xi
Contents
Left-Justified Sample Pair Mode Control Bits ..................... 5-17
Setting Word Length (SLEN) ............................................ 5-17
Enabling SPORT Master Mode (MSTR) ........................... 5-18
Selecting Transmit and Receive Channel Order (FRFS) ...... 5-18
Selecting Frame Sync Options (DIFS) ............................... 5-18
Enabling SPORT DMA (SDEN) ....................................... 5-19
I2S Mode .............................................................................. 5-20
Setting the Internal Serial Clock and Frame Sync Rates ...... 5-21
I2S Mode Control Bits ...................................................... 5-21
Setting Word Length (SLEN) ............................................ 5-22
Enabling SPORT Master Mode (MSTR) ........................... 5-23
Selecting Transmit and Receive Channel Order (FRFS) ...... 5-23
Selecting Frame Sync Options (DIFS) ............................... 5-23
Enabling SPORT DMA (SDEN) ....................................... 5-24
Multichannel Operation ........................................................ 5-25
Frame Syncs in Multichannel Mode ................................... 5-28
Multichannel Mode Control Bits ....................................... 5-29
Packed I2S Mode ................................................................... 5-33
Programming Packed I2S Mode ......................................... 5-34
SPORT Loopback ................................................................. 5-35
Clock Signal Options .................................................................. 5-36
Frame Sync Options .................................................................... 5-37
Framed Versus Unframed Frame Syncs ................................... 5-37
Internal Versus External Frame Syncs ..................................... 5-38

Contents
xii ADSP-21368 SHARC Processor Hardware Reference
Active Low Versus Active High Frame Syncs .......................... 5-39
Sampling Edge for Data and Frame Syncs .............................. 5-39
Early Versus Late Frame Syncs ............................................... 5-40
Data-Independent Frame Syncs ............................................. 5-41
Frame Sync Error Detection .................................................. 5-42
Data Word Formats .................................................................... 5-43
Word Length ........................................................................ 5-43
Endian Format ...................................................................... 5-45
Data Packing and Unpacking ................................................ 5-45
Data Type ........................................................................ 5-46
Companding .................................................................... 5-47
SPORT Control Registers and Data Buffers ................................ 5-49
Register Writes and Effect Latency ......................................... 5-58
Serial Port Control Registers (SPCTLx) ................................. 5-59
Transmit and Receive Data Buffers
(TXSPxA/B, RXSPxA/B) .................................................... 5-67
Clock and Frame Sync Frequency Registers (DIVx) ................ 5-69
SPORT Reset ........................................................................ 5-71
SPORT Interrupts ................................................................ 5-72
Moving Data Between SPORTs and Internal Memory ................. 5-73
DMA Block Transfers ............................................................ 5-73
Setting Up DMA on SPORT Channels ............................. 5-75
SPORT DMA Parameter Registers ......................................... 5-76
SPORT DMA Chaining ................................................... 5-81
Single Word Transfers ........................................................... 5-81

ADSP-21368 SHARC Processor Hardware Reference xiii
Contents
SPORT Programming Examples .................................................. 5-82
SERIAL PERIPHERAL INTERFACE PORTS
Functional Description ................................................................. 6-2
SPI Interface Signals ..................................................................... 6-4
SPI Clock Signal (SPICLK) ..................................................... 6-4
SPICLK Timing .................................................................. 6-5
SPI Slave Select Input (SPIDS) ............................................ 6-6
SPI Flag Signals (SPIFLG3-0) .................................................. 6-6
Master Out Slave In (MOSI) ................................................... 6-7
Master In Slave Out (MISO) ................................................... 6-7
SPI General Operations ................................................................. 6-8
SPI Enable .............................................................................. 6-9
Open Drain Mode (OPD) ....................................................... 6-9
Master Mode Operation ........................................................ 6-10
Slave Mode Operation ........................................................... 6-11
Multimaster Operation .......................................................... 6-12
SPI Data Transfer Operations ...................................................... 6-13
SPI Operation Using the Core ............................................... 6-13
SPI Operation Using DMA .................................................... 6-14
Master Mode DMA Operation .......................................... 6-15
Slave Mode DMA Operation ............................................. 6-19
Changing SPI Configuration ............................................. 6-21
Switching From Transmit To Receive DMA ....................... 6-23
Switching From Receive to Transmit DMA ........................ 6-24

Contents
xiv ADSP-21368 SHARC Processor Hardware Reference
DMA Error Interrupts ...................................................... 6-25
DMA Chaining ................................................................ 6-27
SPI Transfer Formats .................................................................. 6-27
Beginning and Ending an SPI Transfer .................................. 6-29
SPI Word Lengths ...................................................................... 6-31
8-Bit Word Lengths .............................................................. 6-31
16-Bit Word Lengths ............................................................ 6-32
32-Bit Word Lengths ............................................................ 6-32
Packing ................................................................................. 6-32
SPI Interrupts ............................................................................. 6-33
Error Signals and Flags ............................................................... 6-35
Mode Fault Error (MME) ..................................................... 6-35
Transmission Error Bit (TUNF) ............................................ 6-37
Reception Error Bit (ROVF) ................................................. 6-37
Transmit Collision Error Bit (TXCOL) ................................. 6-37
Programming Notes .................................................................... 6-38
Routing SPI Signals Using The DPI ...................................... 6-38
Programming Examples .............................................................. 6-38
INPUT DATA PORT
Serial Inputs ................................................................................. 7-3
Parallel Data Acquisition Port (PDAP) .......................................... 7-8
Masking .................................................................................. 7-9
Packing Unit ........................................................................... 7-9
Packing Mode 11 ................................................................ 7-9

ADSP-21368 SHARC Processor Hardware Reference xv
Contents
Packing Mode 10 .............................................................. 7-10
Packing Mode 01 .............................................................. 7-11
Packing Mode 00 .............................................................. 7-11
Clocking Edge Selection ........................................................ 7-12
Hold Input ............................................................................ 7-12
PDAP Strobe ......................................................................... 7-14
FIFO Control and Status ............................................................ 7-15
FIFO to Memory Data Transfer ................................................... 7-16
IDP Transfers Using the Core ................................................ 7-17
Starting an Interrupt-Driven Transfer ................................ 7-18
Core Transfer Notes .......................................................... 7-19
IDP Transfers Using DMA .................................................... 7-20
Simple DMA .................................................................... 7-20
Ping-Pong DMA ............................................................... 7-22
DMA Transfer Notes ......................................................... 7-25
DMA Channel Parameter Registers ........................................ 7-27
IDP (DAI) Interrupt Service Routines for DMAs ................... 7-28
FIFO Overflow ..................................................................... 7-30
Input Data Port Programming Example ....................................... 7-31
PULSE WIDTH MODULATION
PWM Implementation .................................................................. 8-1
PWM Waveforms .................................................................... 8-1
Edge-Aligned Mode ............................................................ 8-2
Center-Aligned Mode .......................................................... 8-3

Contents
xvi ADSP-21368 SHARC Processor Hardware Reference
Switching Frequencies ............................................................. 8-5
Dead Time ............................................................................. 8-6
Duty Cycles ............................................................................ 8-7
Duty Cycles and Dead Time ............................................... 8-8
Over Modulation .............................................................. 8-12
Update Modes ...................................................................... 8-15
Single Update ................................................................... 8-15
Double Update ................................................................. 8-15
Configurable Polarity ............................................................ 8-15
PWM Pins and Signals .......................................................... 8-16
Crossover ......................................................................... 8-16
PWM Accuracy ..................................................................... 8-17
PWM Registers .......................................................................... 8-18
Duty Cycles .......................................................................... 8-19
Output Enable ...................................................................... 8-20
Programming Example ................................................................ 8-21
S/PDIF TRANSMITTER/RECEIVER
AES3/SPDIF Stream Format ......................................................... 9-2
Subframe Format .................................................................... 9-3
Channel Coding ..................................................................... 9-5
Preambles ............................................................................... 9-6
S/PDIF Transmitter ...................................................................... 9-7
Channel Status ........................................................................ 9-9
SRU1 Signals for the S/PDIF Transmitter .............................. 9-10

ADSP-21368 SHARC Processor Hardware Reference xvii
Contents
S/PDIF Transmitter Registers ................................................ 9-12
Modes of Operation .............................................................. 9-12
Standalone Mode .............................................................. 9-13
Structure of the Serial Input Data .......................................... 9-14
S/PDIF Receiver ......................................................................... 9-16
S/PDIF Receiver Registers ..................................................... 9-17
SRU1 Receiver Signals ........................................................... 9-18
Phase-Locked Loop ..................................................................... 9-19
Channel Status Decoding ............................................................ 9-19
Compressed or Non-Linear Audio Data ................................. 9-20
Emphasized Audio Data ........................................................ 9-21
Single-Channel, Double-Sampling Frequency Mode ............... 9-21
Error Handling ........................................................................... 9-22
Interrupts ................................................................................... 9-24
DAI Programming Examples ....................................................... 9-24
S/PDIF Transmitter Programming Guidelines ........................ 9-24
Control Register ............................................................... 9-24
SRU1 Programming for Input and Output Streams ............ 9-25
Control Register Programming and Enable ........................ 9-25
S/PDIF Receiver Programming Guidelines ............................. 9-25
Control Register ............................................................... 9-25
SRU1 Programming .......................................................... 9-26
Control Register Programming .......................................... 9-26
Receiver Locking ............................................................... 9-26

Contents
xviii ADSP-21368 SHARC Processor Hardware Reference
Status Bits ........................................................................ 9-26
Interrupted Data Streams on the Receiver .......................... 9-27
ASYNCHRONOUS SAMPLE RATE CONVERTER
Theory of Operation .................................................................. 10-2
Conceptual Model ................................................................ 10-4
Hardware Model ................................................................... 10-7
Sample Rate Converter Architecture ............................................ 10-8
Group Delay ....................................................................... 10-12
SRC Operation ......................................................................... 10-12
Enabling the SRC ............................................................... 10-13
Serial Data Ports ................................................................. 10-13
Data Format ................................................................... 10-13
Time-Division Multiplex (TDM) Output Mode .............. 10-15
TDM Input Mode .......................................................... 10-16
Matched-Phase Mode ..................................................... 10-16
Bypass Mode .................................................................. 10-18
De-Emphasis Filter ............................................................. 10-18
Mute Control ..................................................................... 10-19
Soft Mute ....................................................................... 10-20
Hard Mute ..................................................................... 10-20
Auto Mute ...................................................................... 10-20
SRC Registers ........................................................................... 10-21
Programming the SRC Module ................................................. 10-22
SRC Control Register Programming .................................... 10-22

ADSP-21368 SHARC Processor Hardware Reference xix
Contents
SRU Programming .............................................................. 10-22
SRC Mute-Out Interrupt ..................................................... 10-23
Sample Rate Ratio ............................................................... 10-23
Programming Summary ....................................................... 10-23
UART PORT CONTROLLER
Serial Communications ............................................................... 11-2
UART Control and Status Registers ............................................. 11-3
UARTxLCR Registers ............................................................ 11-3
UARTxLSR Register .............................................................. 11-4
UARTxTHR Register ............................................................ 11-4
UARTxRBR Register ............................................................. 11-5
UARTxIER Register .............................................................. 11-7
UARTxIIR Register ............................................................... 11-9
UARTxDLL and UARTxDLH Registers .............................. 11-11
UARTxSCR Register ........................................................... 11-12
UARTxMODE Register ...................................................... 11-13
I/O Mode ................................................................................. 11-13
Packing Mode ........................................................................... 11-15
TWO WIRE INTERFACE CONTROLLER
Overview .................................................................................... 12-1
Architecture ................................................................................ 12-2
Register Descriptions .................................................................. 12-4
TWI Master Internal Time Register ....................................... 12-4

Contents
xx ADSP-21368 SHARC Processor Hardware Reference
TWIDIV Register ................................................................. 12-5
Slave Mode Control Register ................................................. 12-5
Slave Mode Address Register ................................................. 12-6
Slave Mode Status Register .................................................... 12-6
Master Mode Control Register .............................................. 12-6
Master Mode Address Register ............................................... 12-6
Master Mode Status Register ................................................. 12-7
FIFO Control Register .......................................................... 12-7
FIFO Status Register ............................................................. 12-7
Interrupt Source Register ...................................................... 12-7
Interrupt Enable Register ...................................................... 12-8
8-Bit Transmit FIFO Register ................................................ 12-8
16-Bit Transmit FIFO Register .............................................. 12-8
8-Bit Receive FIFO Register .................................................. 12-9
16-Bit Receive FIFO Register .............................................. 12-10
Data Transfer Mechanics ........................................................... 12-10
Clock Generation and Synchronization ................................ 12-11
Bus Arbitration ................................................................... 12-12
Start and Stop Conditions ................................................... 12-12
General Call Support .......................................................... 12-14
Fast Mode ........................................................................... 12-14
Programming Examples ............................................................ 12-15
General Setup ..................................................................... 12-15
Slave Mode ......................................................................... 12-15