Epson S5U13706B00C User manual

Rev. 5.1
S1D13706 Embedded Memory LCD Controller
S5U13706B00C Rev. 1.0
Evaluation Board User Manual
Document Number: X31B-G-004-05.1

NOTICE
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of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does
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All brands or product names mentioned herein are trademarks and/or registered trademarks of their respective
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©SEIKO EPSON CORPORATION 2001-2018. All rights reserved.
Evaluation Board/Kit and Development Tool Important Notice
1. This evaluation board/kit or development tool is designed for use for engineering evaluation, demonstration, or develop-
ment purposes only. Do not use it for other purposes. It is not intended to meet the requirements of design for finished
products.
2. This evaluation board/kit or development tool is intended for use by an electronics engineer and is not a consumer product.
The user should use it properly and in a safe manner. Seiko Epson does not assume any responsibility or liability of any
kind of damage and/or fire caused by the use of it. The user should cease to use it when any abnormal issue occurs even
during proper and safe use.
3. The part used for this evaluation board/kit or development tool may be changed without any notice.
2Seiko Epson Corporation S5U13706B00C Rev. 1.0 Evaluation Board
Rev. 5.1

S5U13706B00C Rev. 1.0 Evaluation Board Seiko Epson Corporation 3
Rev. 5.1
Table of Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Installation and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Configuration DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 CPU Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 CPU Bus Connector Pin Mapping . . . . . . . . . . . . . . . . . . . . . . 14
5 LCD Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1 PCI Bus Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2 Direct Host Bus Interface Support . . . . . . . . . . . . . . . . . . . . . . 18
6.3 S1D13706 Embedded Memory . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4 Manual/Software Adjustable LCD Panel Positive Power Supply (VDDH) . . . . . . . 18
6.5 Manual/Software Adjustable LCD Panel Negative Power Supply (VLCD) . . . . . . 19
6.6 Software Adjustable LCD Backlight Intensity Support Using PWM . . . . . . . . . 20
6.7 Passive/Active LCD Panel Support . . . . . . . . . . . . . . . . . . . . . . 20
6.7.1 Buffered LCD Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.7.2 Extended LCD Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7 Clock Synthesizer and Clock Options . . . . . . . . . . . . . . . . . . . . . . . . 21
7.1 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8 Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
9 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
10 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
11 Change Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
12 Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4Seiko Epson Corporation S5U13706B00C Rev. 1.0 Evaluation Board
Rev. 5.1
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Introduction
S5U13706B00C Rev. 1.0 Evaluation Board Seiko Epson Corporation 5
Rev. 5.1
1 Introduction
This manual describes the setup and operation of the S5U13706B00C Rev. 1.0 Evaluation
Board. The board is designed as an evaluation platform for the S1D13706 Embedded
Memory LCD Controller.
This document is updated as appropriate. Please check for the latest revision of this
document before beginning any development. The latest revision can be downloaded at
vdc.epson.com.
We appreciate your comments on our documentation. Please contact us via email at
vdc-document[email protected]pson.com.

Features
6Seiko Epson Corporation S5U13706B00C Rev. 1.0 Evaluation Board
Rev. 5.1
2 Features
Following are some features of the S5U13706B00C Rev. 1.0 Evaluation Board:
• 100-pin TQFP S1D13706F00A Embedded Memory LCD Controller with 80K bytes of
embedded SRAM.
• Headers for connecting to various Host Bus Interfaces.
• Configuration options.
• Manual or software adjustable positive LCD bias power supply from +20V to +40V.
• Manual or software adjustable negative LCD bias power supply from -24V to -8V.
• Software adjustable backlight intensity support.
• 4/8-bit 3.3V or 5V single monochrome passive LCD panel support.
• 4/8/16-bit 3.3V or 5V single color passive LCD panel support.
• 9/12/18-bit 3.3V or 5V active matrix TFT LCD panel support.
• Direct interface for 18-bit Epson D-TFD LCD panel support.
• Direct interface for 18-bit Sharp HR-TFT LCD panel support.
• Programmable clock synthesizer to CLKI and CLKI2 for maximum clock flexibility.
• Software initiated power save mode.
• Hardware or software Video Invert support.
• Selectable clock source for CLKI and CLKI2.
• External oscillator for CLKI and CLKI2.

Installation and Configuration
S5U13706B00C Rev. 1.0 Evaluation Board Seiko Epson Corporation 7
Rev. 5.1
3 Installation and Configuration
The S5U13706B00C is designed to support as many platforms as possible. The
S5U13706B00C incorporates a DIP switch and seven jumpers which allow both evaluation
board and S1D13706 LCD controller to be configured for a specified evaluation platform.
3.1 Configuration DIP Switches
The S1D13706 has configuration inputs (CNF[7:0]) which are read on the rising edge of
RESET#. In order to configure the S1D13706 for multiple Host Bus Interfaces a ten-
position DIP switch (S1) is required. The following figure shows the location of DIP switch
SW1 on the S5U13706B00C.
Figure 3-1: Configuration DIP Switch (SW1) Location
DIP Switch - SW1

Installation and Configuration
8Seiko Epson Corporation S5U13706B00C Rev. 1.0 Evaluation Board
Rev. 5.1
The S1D13706 has 8 configuration inputs (CONF[7:0]) which are read on the rising edge
of RESET#. All S1D13706 configuration inputs are fully configurable using a ten position
DIP switch as described below.
Note
1To enable the Hardware Video Invert function the following are required:
• GPIO pins must be enabled (S1-4 closed).
• GPIO0 must be connected to S1-9 (Jumper JP1 set to 1-2).
• GPIO Pin Input Enable (REG[A9h] bit 7) must be set to 1.
• GPIO0 Pin IO Configuration (REG[A8h] bit 0) must be set to 0.
• Hardware Video Invert Enable bit (REG[70h] bit 5) must be set to 1.
Table 3-1: Configuration DIP Switch Settings
Switch S1D13706
Signal
Value on this pin at rising edge of RESET# is used to configure:
Closed (On/1) Open (Off/0)
SW1-[3:1] CNF[2:0]
Select host bus interface as follows:
CNF2 CNF1 CNF0 Host Bus Interface
000 SH-4/SH-3
0 0 1 MC68K #1
0 1 0 MC68K #2
0 1 1 Generic #1
1 0 0 Generic #2
101 RedCap2
1 1 0 DragonBall
111 Reserved
Note: The host bus interface is 16-bit.
SW1-4 CNF3 Enable GPIO pins Enable additional pins for D-TFD/HR-TFT
SW1-5 CNF4 Big Endian bus interface Little Endian bus interface
SW1-6 CNF5 WAIT# is active high WAIT# is active low
SW1-[8:7] CNF[7:6]
CLKI to BClk divide select:
CNF7 CNF6 CLKI to BClk Divide Ratio
00 1:1
01 2:1
10 3:1
11 4:1
SW1-91- Hardware Video Invert - invert video data1Hardware Video Invert - normal video data1
SW1-10 - Disable FPGA for non-PCI host Enable FPGA for PCI host
= Required settings when used with PCI Bridge FPGA

Installation and Configuration
S5U13706B00C Rev. 1.0 Evaluation Board Seiko Epson Corporation 9
Rev. 5.1
3.2 Configuration Jumpers
The S5U13706B00C has seven jumper blocks which configure various setting on the
board. The jumper positions for each function are shown below.
JP1 - GPIO0 Connection
JP1 selects whether GPIO0 is connected to SW1-9. SW1-9 is used to enable hardware video
invert on the S1D13706.
When the jumper is on (position 1-2), SW1-9 controls the hardware video invert feature
(default setting).
When the jumper is off, the hardware video invert feature is disabled. This setting must be
used for HR/TFT and D-TFD panels as GPIO0 is required in each panels LCD interface pin
mapping. Refer to the S1D13706 Hardware Functional Specification, document number
X28B-A-001-xx for details.
Note
When configured for Sharp HR-TFT or Epson D-TFD panels, JP1 must be set to no
jumper and JP6 must be set to position 2-3.
Figure 3-2: Configuration Jumper (JP1) Location
Table 3-2: Jumper Summary
Jumper Function Position 1-2 Position 2-3 No Jumper
JP1 GPIO0 Connection GPIO0 connected to SW1-
9 for hardware video invert —
GPIO0 disconnected from
SW1-9 for direct
HR/TFT/D-TFD or GPIO
testing
JP2 CLKI2 Source MCLKOUT from clock
synthesizer External oscillator (U5) —
JP3 CLKI Source VCLKOUT from clock
synthesizer External oscillator (U6) —
JP4 GP0 Polarity on H1 Normal (Active High) Inverted (Active Low) —
JP5 Contrast adjust for +ve LCD bias
(VDDH) Software controlled Manual controlled —
JP6 LCD Panel Voltage +5V LCDVCC +3.3V LCDVCC —
JP7 Contrast adjust for -ve LCD bias
(VLCD) Software controlled — Manual controlled
= recommended settings
JP1
GPIO0 connected GPIO0 disconnected
to SW1-9 from SW1-9

Installation and Configuration
10 Seiko Epson Corporation S5U13706B00C Rev. 1.0 Evaluation Board
Rev. 5.1
JP2 - CLKI2 Source
JP2 selects the source for the CLKI2.
Position 1-2 sets the CLKI2 source to MCLKOUT from the Cypress clock synthesizer
(default setting).
Position 2-3 sets the CLKI2 source to the external oscillator at U5.
Figure 3-3: Configuration Jumper (JP2) Location
JP3 - CLKI Source
JP2 selects the source for the CLKI.
Position 1-2 sets the CLKI2 source to VCLKOUT from the Cypress clock synthesizer
(default setting).
Position 2-3 sets the CLKI2 source to the external oscillator at U6.
Figure 3-4: Configuration Jumper (JP3) Location
JP2
MCLKOUT External
Oscillator (U5)
JP3
VCLKOUT External
Oscillator (U6)

Installation and Configuration
S5U13706B00C Rev. 1.0 Evaluation Board Seiko Epson Corporation 11
Rev. 5.1
JP4 - GPO Polarity on H1
JP4 selects the polarity of the GPO signal available on the LCD Connector H1.
Position 1-2 sends the GPO signal directly to H1 (default setting).
Position 2-3 inverts the GPO signal before sending it to H1.
Figure 3-5: Configuration Jumper (JP4) Location
JP5 - Contrast adjust for +ve LCD bias (VDDH)
JP5 selects the type of control used for contrast adjustment of the +ve LCD bias (VDDH).
Position 1-2 selects software control of the contrast adjustment.
Position 2-3 selects manual control of the contrast adjustment using potentiometer R24
(default setting).
Figure 3-6: Configuration Jumper (JP5) Location
JP4
Inverted
Normal
JP5
Software Manual
Control Control

Installation and Configuration
12 Seiko Epson Corporation S5U13706B00C Rev. 1.0 Evaluation Board
Rev. 5.1
JP6 - LCD Panel Voltage
JP6 selects voltage level to the LCD panel.
Position 1-2 sets the voltage level to 5.0V (default setting).
Position 2-3 sets the voltage level to 3.3V.
Note
When configured for Sharp HR-TFT or Epson D-TFD panels, JP1 must be set to no
jumper and JP6 must be set to position 2-3.
Figure 3-7: Configuration Jumper (JP6) Location
JP7 - Contrast adjust for -ve LCD bias (VLCD)
JP7 selects the type of control used for contrast adjustment of the -ve LCD bias (VLCD).
Position 1-2 selects software control of the contrast adjustment.
Position 2-3 selects manual control of the contrast adjustment using potentiometer R31
(default setting).
Figure 3-8: Configuration Jumper (JP7) Location
JP6
5.0V 3.3V
JP7
Software
Control
Manual
Control

CPU Interface
S5U13706B00C Rev. 1.0 Evaluation Board Seiko Epson Corporation 13
Rev. 5.1
4 CPU Interface
4.1 CPU Interface Pin Mapping
Note
1A0 for these busses is not used internally by the S1D13706.
2If the target MC68K bus is 32-bit, then these signals should be connected to D[31:16].
3These pins are not used in their corresponding Host Bus Interface mode. Systems are
responsible for externally connecting them to the host interface IO VDD.
Table 4-1: CPU Interface Pin Mapping
S1D13706
Pin Name Generic #1 Generic #2 Hitachi
SH-3 /SH-4
Motorola
MC68K #1
Motorola
MC68K #2
Motorola
REDCAP2
Motorola
MC68EZ328/
MC68VZ328
DragonBall
AB[16:1] A[16:1] A[16:1] A[16:1] A[16:1] A[16:1] A[16:1] A[16:1]
AB0 A01A0 A01LDS# A0 A01A01
DB[15:0] D[15:0] D[15:0] D[15:0] D[15:0] D[15:0]2D[15:0] D[15:0]
CS# External Decode CSn# External Decode CSn# CSA#
M/R# External Decode
CLKI BUSCLK BUSCLK CKIO CLK CLK CLK CLK
BS# Connected to VDD3BS# AS# AS# Connected to VDD3
RD/WR# RD1# Connected to
VDD3RD/WR# R/W# R/W# R/W# Connected to VDD3
RD# RD0# RD# RD# Connected to
VDD3SIZ1 OE# OE#
WE0# WE0# WE# WE0# Connected to
VDD3SIZ0 EB1# LWE#
WE1# WE1# BHE# WE1# UDS# DS# EB0# UWE#
WAIT# WAIT# WAIT# WAIT#/
RDY# DTACK# DSACK1# N/A DTACK#
RESET# RESET# RESET# RESET# RESET# RESET# RESET# RESET#

CPU Interface
14 Seiko Epson Corporation S5U13706B00C Rev. 1.0 Evaluation Board
Rev. 5.1
4.2 CPU Bus Connector Pin Mapping
Table 4-2: CPU Bus Connector (H3) Pinout
Connector
Pin No. Comments
1Connected to DB0 of the S1D13706
2Connected to DB1 of the S1D13706
3Connected to DB2 of the S1D13706
4Connected to DB3 of the S1D13706
5Ground
6Ground
7Connected to DB4 of the S1D13706
8Connected to DB5 of the S1D13706
9Connected to DB6 of the S1D13706
10 Connected to DB7 of the S1D13706
11 Ground
12 Ground
13 Connected to DB8 of the S1D13706
14 Connected to DB9 of the S1D13706
15 Connected to DB10 of the S1D13706
16 Connected to DB11 of the S1D13706
17 Ground
18 Ground
19 Connected to DB12 of the S1D13706
20 Connected to DB13 of the S1D13706
21 Connected to DB14 of the S1D13706
22 Connected to DB15 of the S1D13706
23 Connected to RESET# of the S1D13706
24 Ground
25 Ground
26 Ground
27 +12 volt supply
28 +12 volt supply
29 Connected to WE0# of the S1D13706
30 Connected to WAIT# of the S1D13706
31 Connected to CS# of the S1D13706
32 Connected to MR# of the S1D13706
33 Connected to WE1# of the S1D13706
34 Connected to TXVDD1

CPU Interface
S5U13706B00C Rev. 1.0 Evaluation Board Seiko Epson Corporation 15
Rev. 5.1
Table 4-3: CPU Bus Connector (H4) Pinout
Connector
Pin No. Comments
1Connected to A0 of the S1D13706
2Connected to A1 of the S1D13706
3Connected to A2 of the S1D13706
4Connected to A3 of the S1D13706
5Connected to A4 of the S1D13706
6Connected to A5 of the S1D13706
7Connected to A6 of the S1D13706
8Connected to A7 of the S1D13706
9Ground
10 Ground
11 Connected to A8 of the S1D13706
12 Connected to A9 of the S1D13706
13 Connected to A10 of the S1D13706
14 Connected to A11 of the S1D13706
15 Connected to A12 of the S1D13706
16 Connected to A13 of the S1D13706
17 Ground
18 Ground
19 Connected to A14 of the S1D13706
20 Connected to A15 of the S1D13706
21 Connected to A16 of the S1D13706
22 Not connected
23 Not connected
24 Not connected
25 Ground
26 Ground
27 +5 volt supply
28 +5 volt supply
29 Connected to RD/WR# of the S1D13706
30 Connected to BS# of the S1D13706
31 Connected to BUSCLK of the S1D13706
32 Connected to RD# of the S1D13706
33 Not connected
34 Not connected

LCD Interface Pin Mapping
16 Seiko Epson Corporation S5U13706B00C Rev. 1.0 Evaluation Board
Rev. 5.1
5 LCD Interface Pin Mapping
Note
1These pin mappings use signal names commonly used for each panel type, however
signal names may differ between panel manufacturers. The values shown in brackets
represent the color components as mapped to the corresponding FPDATxx signals at
the first valid edge of FPSHIFT. For further FPDATxx to LCD interface mapping, see
S1D13706 Hardware Functional Specification, document number X31B-A-001-xx.
2GPO on H1 can be inverted by setting JP4 to 2-3.
3The Sharp HR-TFT MOD signal controls the panel power. This must not be confused
with the MOD signal used on many passive panels.
Table 5-1: LCD Signal Connector (H1)
Pin
Name
Connector
Pin No.
Monochrome
Passive Color Passive Panel Color TFT Panel
Single Single Others Sharp
HR-TFT1
Epson
D-TFD1
Format 1 Format 2
4-bit 8-bit 4-bit 8-bit 8-bit 16-Bit 9-bit 12-bit 18-bit 18-bit 18-bit
FPDAT0 1 driven 0 D0 driven 0 D0 (B5)1D0 (G3)1D0 (R6)1R2 R3 R5 R5 R5
FPDAT1 3 driven 0 D1 driven 0 D1 (R5)1D1 (R3)1D1 (G5)1R1 R2 R4 R4 R4
FPDAT2 5 driven 0 D2 driven 0 D2 (G4)1D2 (B2)1D2 (B4)1R0 R1 R3 R3 R3
FPDAT3 7 driven 0 D3 driven 0 D3 (B3)1D3 (G2)1D3 (R4)1G2 G3 G5 G5 G5
FPDAT4 9 D0 D4 D0 (R2)1D4 (R3)1D4 (R2)1D8 (B5)1G1 G2 G4 G4 G4
FPDAT5 11 D1 D5 D1 (B1)1D5 (G2)1D5 (B1)1D9 (R5)1G0 G1 G3 G3 G3
FPDAT6 13 D2 D6 D2 (G1)1D6 (B1)1D6 (G1)1D10 (G4)1B2 B3 B5 B5 B5
FPDAT7 15 D3 D7 D3 (R1)1D7 (R1)1D7 (R1)1D11 (B3)1B1 B2 B4 B4 B4
FPDAT8 17 driven 0 driven 0 driven 0 driven 0 driven 0 D4 (G3)1B0 B1 B3 B3 B3
FPDAT9 19 driven 0 driven 0 driven 0 driven 0 driven 0 D5 (B2)1driven0R0R2R2R2
FPDAT10 21 driven 0 driven 0 driven 0 driven 0 driven 0 D6 (R2)1driven 0 driven 0 R1 R1 R1
FPDAT11 23 driven 0 driven 0 driven 0 driven 0 driven 0 D7 (G1)1driven 0 driven 0 R0 R0 R0
FPDAT12 25 driven 0 driven 0 driven 0 driven 0 driven 0 D12 (R3)1driven0G0G2G2G2
FPDAT13 27 driven 0 driven 0 driven 0 driven 0 driven 0 D13 (G2)1driven 0 driven 0 G1 G1 G1
FPDAT14 29 driven 0 driven 0 driven 0 driven 0 driven 0 D14 (B1)1driven 0 driven 0 G0 G0 G0
FPDAT15 31 driven 0 driven 0 driven 0 driven 0 driven 0 D15 (R1)1driven0B0B2B2B2
FPDAT16 4 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 B1 B1 B1
FPDAT17 6 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 B0 B0 B0
FPSHIFT 33 FPSHIFT CLK XSCL
DRDY 35 & 38 MOD FPSHIFT2 MOD DRDY no
connect GCP
FPLINE 37 FPLINE LP LP
FPFRAME 39 FPFRAME SPS DY
GND 2, 8, 14, 20,
26 GND
PWMOUT 28 PWMOUT
VLCD 30 Adjustable -24V to -8V negative LCD bias
VCC 32 LCDVCC (3.3V / 5.0V)
+12V 34 +12V
VDDH 36 Adjustable +20V to +40V positive LCD bias
GPO 40 GPO2(for controlling on-board LCD bias power supply on/off) MOD3GPO2

LCD Interface Pin Mapping
S5U13706B00C Rev. 1.0 Evaluation Board Seiko Epson Corporation 17
Rev. 5.1
Note
1When dip switch SW1-4 is open (CNF3 = 0 at RESET#), GPIO[6:0] are at low output
states after reset. If REG[10h] bits[1:0] are set for either HR-TFT or D-TFD, some of
the pins are used for the HR-TFT or D-TFD interfaces and are not available as GPIO
pins.
Table 5-2: Extended LCD Signal Connector (H2)
Pin
Name
Connector
Pin No.
Monochrome
Passive Panel Color Passive Panel Color TFT Panel
Single Single Others HR-
TFT1D-TFD1
Format 1 Format 2
4-bit 8-bit 4-bit 8-bit 8-bit 16-Bit 9-bit 12-bit 18-bit 18-bit 18-bit
GPIO0 1 GPIO0 PS XINH
GPIO1 3 GPIO1 CLS YSCL
GPIO2 5 GPIO2 REV FR
GPIO3 7 GPIO3 SPL FRS
GPIO4 9 GPIO4 GPIO4 RES
GPIO5 11 GPIO5 GPIO5 DD_P1
GPIO6 13 GPIO6 GPIO6 YSCLD
CVOUT 15 CVOUT
GND 2, 4, 6, 8, 10,
12, 14, 16 GND

Technical Description
18 Seiko Epson Corporation S5U13706B00C Rev. 1.0 Evaluation Board
Rev. 5.1
6 Technical Description
6.1 PCI Bus Support
The S1D13706 does not have on-chip PCI bus interface support. The S1D13706B00C uses
the PCI Bridge FPGA to support the PCI bus.
6.2 Direct Host Bus Interface Support
The S5U13706B00C is specifically designed to work using the PCI Bridge FPGA in a
standard PCI bus environment. However, the S1D13706 directly supports many other host
bus interfaces. Connectors H3 and H4 provide the necessary IO pins to interface to these
host buses. For further information on the host bus interfaces supported, see “CPU
Interface” on page 13.
Note
The PCI Bridge FPGA must be disabled using SW1-10 in order for direct host bus inter-
face to operate properly.
6.3 S1D13706 Embedded Memory
The S1D13706 has 80K bytes of embedded SRAM. The 80K byte display buffer address
space is directly and contiguously available through the 17-bit address bus.
6.4 Manual/Software Adjustable LCD Panel Positive Power Supply (VDDH)
Most passive LCD color and passive single monochrome LCD panels require a positive
bias voltage between +24V and +40V. The S5U13706B00C uses a Maxim MAX754 LCD
Contrast Controller to provide this voltage range. The signal VDDH can be adjusted
manually (using a potentiometer) or controlled through software.
When JP5 is set to position 1-2, VDDH can be controlled through software to provide an
output voltage from +20V to +40V. CVOUT and GPO of the S1D13706 are connected to
LADJ and LON of MAX754. The output voltage (VDDH) can be adjusted from +20V to
+40V in 64 steps by sending pulses to CVOUT. Each CVOUT pulse decrements VDDH
one step towards +20V. When decremented beyond +20V, VDDH resets to +40V again. In
other words, 63 pulses equal incrementing 1 step. After the MAX754 is reset (see
“Controlling the MAX754” on page 19), VDDH is set at +30V.

Technical Description
S5U13706B00C Rev. 1.0 Evaluation Board Seiko Epson Corporation 19
Rev. 5.1
The S5U13706B00C uses GPO and CVOUT to control the MAX754 as shown in the
following table..
When JP5 is set to position 2-3, VDDH is adjustable using R24 (200potentiometer) to
provide an output voltage from +24V to +40V.
Note
When manually adjusting the voltage, set the potentiometer according to the panel’s
specific power requirements before connecting the panel.
6.5 Manual/Software Adjustable LCD Panel Negative Power Supply (VLCD)
Most passive monochrome LCD panels require a negative bias voltage between -14V and
-24V. The S5U13706B00C uses a Maxim MAX749 Digitally Adjustable LCD Bias Supply
to provide this voltage range. The signal VLCD can be adjusted manually (using a potenti-
ometer) or controlled through software.
When JP7 is set to position 1-2, VLCD can be controlled through software to provide an
output voltage from -8V to -24V. CVOUT and GPO of the S1D13706 are connected to ADJ
and CTRL of MAX749. The output voltage (VLCD) can be adjusted from -8V to -24V in
64 steps by sending pulses to CVOUT. Each CVOUT pulse increments VLCD one step
towards -24V. When decremented beyond -24V, VLCD resets to -8V again. In other words,
63 pulses equal incrementing 1 step. After the MAX749 is reset (see “Controlling the
MAX749” on page 19), VLCD is set at -16V.
The S5U13706B00C uses GPO and CVOUT to control the MAX749 as shown in the
following table..
When jumper JP7 is set to position 2-3, VLCD can be adjusted by R41 (500K potenti-
ometer) to provide an output voltage from -16V to -23V.
Note
When using manual adjust, set the potentiometer according to the panel’s specific power
requirements before connecting the panel.
Table 6-1: Controlling the MAX754
Signal Turn MAX754 On Turn MAX754 Off Reset MAX754
GPO high low low
CVOUT X low high
X = don’t care
Table 6-2: Controlling the MAX749
Signal Turn MAX749 On Turn MAX749 Off Reset MAX749
GPO high low low
CVOUT X low high
X = don’t care

Technical Description
20 Seiko Epson Corporation S5U13706B00C Rev. 1.0 Evaluation Board
Rev. 5.1
6.6 Software Adjustable LCD Backlight Intensity Support Using PWM
The S1D13706 provides Pulse Width Modulation output on PWMOUT. PWMOUT can be
used to control LCD panels which support PWM control of the backlight inverter. The
PWMOUT signal is provided on the buffered LCD connector (H1).
6.7 Passive/Active LCD Panel Support
The S1D13706 directly supports:
• 4/8-bit, single monochrome passive panels.
• 4/8/16-bit single color passive panels.
• 9/12/18-bit TFT active matrix panels.
• 18-bit Sharp HR-TFT panels.
• 18-bit Epson D-TFD panels.
All the necessary signals are provided on the 40-pin LCD connector H1. For connection
information, refer to Table 5-1: “LCD Signal Connector (H1)” on page 16.
6.7.1 Buffered LCD Connector
The buffered LCD connector (H1) provides the same LCD panel signals as those directly
from S1D13706, but with voltage-adapting buffers selectable to 3.3V or 5.0V. Pin 32 on
this connector provides a voltage level of 3.3V or 5.0V to the LCD panel logic (see “JP6 -
LCD Panel Voltage” on page 12 for information on setting the panel voltage).
6.7.2 Extended LCD Connector
The S1D13706 directly supports Sharp 18-bit HR-TFT and Epson 18-bit D-TFD panels.
The extended LCD connector (H3) provides the extra signals required to support these
panels. The signals on this connector are also buffered from the S1D13706 and adjustable
to 3.3V or 5.0V (see “JP6 - LCD Panel Voltage” on page 12 for details on setting the panel
voltage).