Epson S5U13709P00C100 User manual

Rev.1.1
S1D13709 Embedded Memory Graphics LCD Controller
S5U13709P00C100 Evaluation
Board User Manual Rev.1.0
Document Number: XA8A-G-001-01.1

Evaluation board/kit and Development tool important notice
1. This evaluation board/kit or development tool is designed for use for engineering evaluation, demonstration,
or development purposes only. Do not use it for other purposes. It is not intended to meet the requirements of
design for finished products.
2. This evaluation board/kit or development tool is intended for use by an electronics engineer and is not a
consumer product. The user should use it properly and in a safe manner. Seiko Epson dose not assume any
responsibility or liability of any kind of damage and/or fire coursed by the use of it. The user should cease to
use it when any abnormal issue occurs even during proper and safe use.
3. The part used for this evaluation board/kit or development tool may be changed without any notice.
NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written
permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.
Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material
or due to its application or use in any product or circuit and, further, there is no representation that this material is
applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any
intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that
anything made in accordance with this material will be free from any patent or copyright infringement of a third
party. When exporting the products or technology described in this material, you should comply with the
applicable export control laws and regulations and follow the procedures required by such laws and regulations.
You are requested not to use, to resell, to export and/or to otherwise dispose of the products (and any technical
information furnished, if any) for the development and/or manufacture of weapon of mass destruction or for other
military purposes.
All brands or product names mentioned herein are trademarks and/or registered trademarks of their respective
companies.
©SEIKO EPSON CORPORATION 2014-2018,All rights reserved.

S5U13709P00C100 Evaluation Board Seiko Epson Corporation i
(Rev.1.1)
Table of Contents
1. Introduction................................................................................................................ 1
2. Features...................................................................................................................... 2
3. Installations and Configuration ................................................................................ 3
3.1 3.1 Switches................................................................................................................................3
3.2 3.2 Configuration Jumpers........................................................................................................5
3.3 Power Requirement....................................................................................................................7
3.3.1 HIOVDD, NIOVDD, COREVDD, PLLVDD ............................................................................7
3.3.2 Backlight Power Supply for LCD Panel.................................................................................7
4. Connectors................................................................................................................. 8
4.1 P1, P2 Host Interface Connector ..............................................................................................9
4.2 H1, H2 Host Interface Connector..............................................................................................9
4.3 H3, H4 Panel Interface Connector ............................................................................................9
5. Technical Descriptions............................................................................................ 10
5.1 Current Measurement ..............................................................................................................10
5.2 Clock source select..................................................................................................................10
5.3 Hardware Reset ........................................................................................................................10
6. Parts List....................................................................................................................11
7. Schematic Diagrams................................................................................................ 13
8. S5U13709P00C100 Board Layout........................................................................... 17
9. Installation Guide for the S5U13U00P00C100 ....................................................... 18
9.1 Installation and connecting.....................................................................................................18
10. Using the panel I/F board........................................................................................ 21
10.1 Connecting the panel I/F board ..............................................................................................21
11. Change Record ........................................................................................................ 23
12. Sales and Technical Support .................................................................................. 24

ii Seiko Epson Corporation S5U13709P00C100 Evaluation Board
(Rev.1.1)

Introduction
S5U13709P00C100 Evaluation Board Seiko Epson Corporation 1
(Rev.1.1)
1. Introduction
This manual describes the setup and operation of the S5U13709P00C100 Rev.1.0 Evaluation Board. This
evaluation board is designed as an evaluation platform for the S1D13709 Embedded Memory Graphics LCD
Controller.
The S5U13709P00C100 Evaluation Board can be used with the USB Interface Board (S5U13U00P00C100), thus
providing an easy connection to Personal Computer with a USB interface.
This document is updated as appropriate. Please check for the latest revision of this document before beginning
any development. The latest revision can be downloaded at vdc.epson.com.
We appreciate your comments on our documentation. Please contact us via email at
vdc-documentati[email protected]

Features
2 Seiko Epson Corporation S5U13709P00C100 Evaluation Board
(Rev.1.1)
2. Features
The S5U13709P00C100 Evaluation Board includes the following features:
•80-pin TQFP14 S1D13709 Embedded Memory Graphics LCD Controller
•2.0mm pitch 40pin connector (x2) for USB Interface Board. (S5U13U00P00C100)
•2.54mm pitch 34pin connector (x2) for connecting other host interface.
•2.54mm pitch 40pin connector (x2) for panel interface.
•Clock source can be selected from two types.
Use on-board 24MHz crystal oscillator or set crystal in the 14pin socket.
•SW1, SW2 are switches to change the configuration for the S1D13709.
•On-board voltage regulator (LM1117MPX-3.3) with 3.3V output for HIOVDD/NIOVDD.
•On-board white LED driver (TPS61161A) for the panel backlight power supply.

Installation and Configuration
S5U13709P00C100 Evaluation Board Seiko Epson Corporation 3
(Rev.1.1)
3. Installation and Configuration
3.1 3.1 Switches
The S5U13709P00C100 Evaluation Board incorporates DIP switches (SW1, SW2), which allow configuration of
the board. For switch locations on the evaluation board, see Figure 3-1: “Configuration DIP Switches Location”.
Figure 3.1 Configuration DIP Switches (SW1), (SW2) Location

Installation and Configuration
4 Seiko Epson Corporation S5U13709P00C100 Evaluation Board
(Rev.1.1)
The 12-position DIP switch (SW1) is used to configure the S1D13709 for different host bus interfaces and for
TFT panel or STN panel for TFT-LCD Automatic Setting Mode.
Table 3.1 Summary of Configuration Options
S5U13709P00C100
SW1-[12:1]
Configuration
S1D13709
Pin
Configuration State
1 (ON)
0 (OFF)
SW1-[12]
TESTEN
Not use
Normal use “GND”
SW1-[11]
CNF10
CLKI (XCG1) frequency is 24MHz
This setting is available only when the TFT-LCDAutomatic
Setting Mode is enabled (CNF[7:5] = 001,010, 011 or 100)
CLKI (XCG1) frequency is 20MHz
SW1-[10]
CNF9
TFT Interface Output Drive is 6mA@3.3V
(8mA@5V)
This setting is available only when the TFT-LCD Automatic
Setting Mode is enabled (CNF[7:5] = 001,010, 011 or 100)
TFT Interface Output Drive is [email protected]
(3mA@5V)
SW1-[9]
CNF8
All output video signals change at rising edge
of FPSHIFT
This setting is available only when the TFT-LCD Automatic
Setting Mode is enabled (CNF[7:5] = 001,010, 011 or 100)
All output video signals change at the
falling edge of FPSHIFT
SW1-[8:6]
CNF[7:5]
CNF7 CNF6 CNF5 TFT-LCD Automatic Setting Mode
0 0 0 Disable (Manual setting)
0 0 1 S1D13700 S/W: QVGA TFT: QVGA
0 1 0 S1D13700 S/W: QVGA TFT: WQVGA
0 1 1 S1D13700 S/W: QVGA TFT: VGA
1 0 0 S1D13700 S/W: QVGA TFT: WVGA
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Reserved
When the STN interface is used (REG[34h] bit0 = 0), CNF[7:5]
should be 000.
TFT interface is used. (TFT-LCD Automatic
Setting Mode Disable)
Or STN interface is used. (REG[34h] bit0
= 0)
SW1-[5]
CNF4
Indirect Addressing Mode:
1-bit address bus, 8-bit data bus
9pin are used
Direct Addressing Mode:
16bit address bus, 8-bit data bus
24pin are used.
SW1-[4:3]
CNF[3:2]
Select the host bus interface as follows:
CNF3 CNF2 Host Bus
0 0 Generic Bus
0 1 Reserved
1 0 M6800 Family Bus Interface
1 1 MC68K Family Bus Interface
Select the host bus interface as “Generic
Bus”.
SW1-[2:1]
CNF[1:0]
Select the XSCL cycle time (XSCL:CLOCK
Input) as follows:
For 1bpp mode (REG[20h] bit 1-0 = 00)
CNF1 CNF0 XSCL Cycle Time
0 0 4:1
0 1 8:1
1 0 16:1
1 1 Reserved
For 2bpp mode (REG[20h] bit 1-0 = 01)
CNF1 CNF0 XSCL Cycle Time
0 0 8:1
0 1 16:1
1 0 32:1
1 1 Reserved
For 4bpp mode (REG[20h] bit 1-0 = 10)
CNF1 CNF0 XSCL Cycle Time
0 0 16:1
0 1 32:1
1 0 64:1
1 1 Reserved
When the TFT Interface is used (REG[34h] bit0 = 1), CNF[1:0]
should be 00.
For 1bpp mode (REG[20h] bit 1-0 = 00)
CNF1 CNF0 XSCL Cycle Time
0 0 4:1
For 2bpp mode (REG[20h] bit 1-0 = 01)
CNF1 CNF0 XSCL Cycle Time
0 0 8:1
For 4bpp mode (REG[20h] bit 1-0 = 10)
CNF1 CNF0 XSCL Cycle Time
0 0 16:1
= default setting

Installation and Configuration
S5U13709P00C100 Evaluation Board Seiko Epson Corporation 5
(Rev.1.1)
The 2-position DIP switch (SW2) is used to configure for production test only. For normal use this switch state
should be set to "ON".
Table 3.2 Summary of Configuration Options
S5U13709P00C100
SW2-[2:1]
Configuration
S1D13709
Pin
Configuration State
1 (ON)
0 (OFF)
SW2-[1]
CORECE
Normal use
Not use
SW2-[2]
PLLCE
Normal use
Not use
= default setting
3.2 3.2 Configuration Jumpers
The S5U13709P00C100 Evaluation Board includes the following 2-pin, 3-pin and 8-pin jumper blocks which are
used to control function and for power consumption measurement. For jumper locations on the evaluation board,
see Figure 3-2: “Configuration Jumper Location”
Figure 3.2 Configuration Jumper Location

Installation and Configuration
6 Seiko Epson Corporation S5U13709P00C100 Evaluation Board
(Rev.1.1)
Table 3.3 2-Pin Jumper Settings
Jumper
Position1-2
No Jumper
JP1
COREVDD power supply
COREVDD no power
Connect a current meter for power
measurement
JP3
PLLVDD power supply
PLLVDD no power
Connect a current meter for power
measurement
JP5
HIOVDD power supply
HIPVDD no power
Connect a current meter for power
measurement
JP6
NIOVDD power supply
NIOVDD no power
Connect a current meter for power
measurement
JP11
Use OSC clock source
Disable OSC clock source
= default setting
Table 3.4 3-Pin Jumper Settings
Jumper
Position1-2
Position2-3
JP2
Select power supply HIOVDD
Select power supply NIOVDD
JP4
Select power supply HIOVDD
Select power supply NIOVDD
JP7
Select clock source OSC1
Select clock source P1-4pin
(S5U13U00P00C100)
JP8
Select clock input OSCI
Select clock input MCLK
JP9
Select HIOVDD Voltage 3.3V
Select HIOVDD Voltage 5.0V
JP10
Select NIOVDD Voltage 3.3V
Select NIOVDD Voltage 5.0V
JP12
Reset# pulse supply from SW3
Reset# pulse supply from P1-21pin,
H1-30pin
= default setting
Table 3.5 8-Pin Jumper Settings
Jumper
Position
Function
J1
Position1-2
No Jumper
TPS61161A Enable
Position3-4
No Jumper
Vout = 20mA
Position5-6
No Jumper
Vout = 40mA ( and Position3-4)
Position7-8
No Jumper
Vout = 60mA (And position3-4/5-6)
= default setting

Installation and Configuration
S5U13709P00C100 Evaluation Board Seiko Epson Corporation 7
(Rev.1.1)
3.3 Power Requirement
3.3.1 HIOVDD, NIOVDD, COREVDD, PLLVDD
The S5U13709P00C100 Evaluation Board is designed to generate HIOVDD, NIOVDD, COREVDD and
PLLVDD from 5V via the S5U13U00P00C100 USB Interface Board. 5V must be supplied from the
S5U13U00P00C100. JP1 on the S5U13U00P00C100 USB Interface Board should be set to position 2-3. 3.3V
power supply is generated by one voltage regulator (U3) and fixed output. HIOVDD and NIOVDD can be
selected 3.3V or 5V using jumper JP9 and JP10. COREVDD is possible to select HIOVDD, NIOVDD or
LDOVDD0. PLLVDD are possible to select HIOVDD, NIOVDD or LDOVDD1. If use the LDOVDD0 and
LDOVDD1, it is external input from JP1 and JP3. Refer to Table 3-2a and 3-2b on page 9.
3.3.2 Backlight Power Supply for LCD Panel
The S5U13709P00C100 Evaluation Board has an incorporated White LDE Driver Controller (TPS61161A) for
the panel backlight. White LED Driver Controller drives the panel at a constant current. The S5U13709P00C100
Evaluation Board is possible to change the output current (20mA, 40mA, 60mA/ Max 38V). Please set J1 with
the specifications of the panel. Refer to Table 3-2c on page 9.

Connectors
8 Seiko Epson Corporation S5U13709P00C100 Evaluation Board
(Rev.1.1)
4. Connectors
The S5U13709P00C100 Evaluation Board has host interface connectors and panel interface connectors (P1, P2,
H1, H2, H3 and H4). For connector locations on the evaluation board, see Figure 4-1: “Evaluation board
Connector Location”
Figure 4.1 Evaluation board Connector Location

Connectors
S5U13709P00C100 Evaluation Board Seiko Epson Corporation 9
(Rev.1.1)
4.1 P1, P2 Host Interface Connector
The S5U13709P00C100 Evaluation Board is designed to connect to a S5U13U00P00C100 USB Interface Board.
The USB Interface Board provides a simple connection to any computer via USB 2.0 connection. The
S5U13709P00C100 directly connects to the USB Interface Board through connectors P1 and P2.
When the S5U13709P00C100 is connected to the S5U13U00P00C100, there is a LED on the
S5U13U00P00C100 which provide a quick visual status of the power supply (5V). And S5U13709P00C100 has
a LED too. This LED indicates that the 3.3V power is supplied. P1 and P2 connectors are 2mm pitch, dual row,
and 40-pin female headers (20x2).
Note:
A windows driver must be installed on the PC when the S5U13709P00C100 is used with the S5U13U00P00C100
USB Interface Board. The S1D13xxxUSB driver is available at vdc.epson.com.
4.2 H1, H2 Host Interface Connector
When the S5U13709P00C100 Evaluation Board connects with the S5U13U00P00C100 USB Interface Board, H1
and H2 connectors can be used as monitor terminals.
The S5U13709P00C100 is designed to connect to a S5U13U00P00C100. But H1 and H2 connectors allow a
variety of development platforms to be used with the S5U13709P00C100. When not used with the
S5U13U00P00C100, please supply the 5V power to TP1 terminal.
4.3 H3, H4 Panel Interface Connector
The LCD interface uses the FPFRAME, FPSHIFT, FPDRDY, FPLINE and FPDAT [3:0] pins. All signals on
these pins are available on connectors H3 and H4. Connectors H3 and H4 are 2.54mm pitch, dual row, and 40-pin
female headers (20x2).

Technical Descriptions
10 Seiko Epson Corporation S5U13709P00C100 Evaluation Board
(Rev.1.1)
5. Technical Descriptions
5.1 Current Measurement
Current measurement can be performed individually for each power supplies: HIOVDD, NIOVDD, COREVDD
and PLLVDD. For details on which jumper block is used for each power supply, refer to Table 3-2a: “2-Pin
Jumper Settings,” on page 9.
To measure current for a particular power supply, remove the corresponding jumper shunt and place an ammeter
on the jumper terminals to measure the current draw. Use the lowest possible range for the measurement to
minimize loading from the ammeter.
Note:
Attaching an ammeter while doing other tests can cause a voltage drop across the ammeter and may produce
invalid test results.
5.2 Clock source select
The S5U13709P00C100 Evaluation Board has an on-board 24MHz oscillator (Y1) which drives the input with
the internal oscillator circuit (XCG1). When not using the internal oscillator circuit, this board allows the usage
of a variety of crystal oscillators with osc1 connectors (CLKI). The XCG1 source selection is determined with
jumper on 1-2pin of JP8 and 1-2pin of JP11. The CLKI source selection is determined with jumper on 1-2pin of
JP7 and 2-3pin of JP8. For details on configuring the clock source, refer to Table 3-2a and Table 3-2b on page 9.
5.3 Hardware Reset
The S5U13709C00100 Evaluation Board has an on-board reset IC which drives the RESET# input pin on the
panel. This occurs when push button SW3 is pressed.

Parts List
S5U13709P00C100 Evaluation Board Seiko Epson Corporation 11
(Rev.1.1)
6. Parts List
Table 6.1 S5U13531B02C100 Parts List
Item
Qty
Reference
Part
Description
Manufacture Part
No. / Comments
1
5
C1, C2, C3, C4, C25
Capacitance
1uF
2
2
C5, C10
Capacitance
4.7uF
3
11
C6, C7, C8, C9, C11,
C12, C15, C17, C20,
C24, C26
Capacitance
0.1uF
4
1
C14
Capacitance
100uF / 16V
5
1
C16
Capacitance
0.01uF
6
1
C18
Capacitance
100uF / 10V
7
1
C19
Capacitance
10uF /16V
8
2
C21, C22
Capacitance
10pF
9
1
C23
Capacitance
0.22uF
10
1
D1
LED
BG1111C
STANLEY
11
1
D2
Diode
CRS04
TOSHIBA
12
1
F1
Inductance
MINISMDC110F-2
TE
13
2
H1, H2
Connector
A1-34PA-2.54DSA
HIROSE
14
2
H3, H4
Connector
HIF3FC-40PA-2.54DSA
HIROSE
15
5
JP1, JP3, JP5, JP6,
JP11
Header Pin
A2-2PA-2.54DSA
HIROSE
16
7
JP2, JP4, JP7, JP8,
JP9, JP10, JP12
Header Pin
A2-3PA-2.54DSA-
HIROSE
17
1
J1
Header Pin
A1-8PA-2.54DSA
HIROSE
18
1
L1
Inductance
VLCF5020T-220MR75-1
TDK
19
1
OSC1
SOCKET
4-1571552-2
TE
20
2
P1, P2
Connector
PRPN202PAEN
SULLINS
21
1
R1
Resister
1K
22
7
R2, R3, R4, R5, R6
R28, R31
Resister
0
23
32
R7, R8, R9, R10, R11,
R12, R13, R14, R15,
R16, R17, R18, R19,
R20, R35, R36, R37,
R38, R39, R40, R41,
R42, R43, R44, R45,
R46, R47, R48, R49,
R50, R51, R52
Resister
10K
24
1
R21
Resister
22K
25
1
R22
Resister
10K
26
1
R23
Resister
0
27
1
R29
Resister
240
28
1
R30
Resister
10M
29
3
R32, R33, R34
Resister
10
30
16
SH1, SH2, SH3, SH4,
SH5, SH6, SH7, SH8,
SH9, SH10, SH11,
SH12, SH13, SH14,
SH15, SH16
Short socket
XJ8A-0211
OMRON
31
1
SW1
DIP switch
219-12MST
CTS
32
1
SW2
DIP switch
219-2MST
CTS
33
1
SW3
Switch
KSC241J
C&K

Parts List
12 Seiko Epson Corporation S5U13709P00C100 Evaluation Board
(Rev.1.1)
Table 6.2 S5U13531B02C100 Parts List (continued)
Item
Qty
Reference
Part
Description
Manufacture Part
No. /
Comments
34
3
TP1, TP2, TP3
Monitor pin
HK-2-S
MAC8
35
7
T1, T2, T3, T4, T5, T6,
T7
Monitor TH
TH
36
1
U1
IC
S1D13709
EPSON
37
1
U2
Regulator
LM1117MPX-3.3
NS
38
1
U3
LDE Driver
TPS61161A
TI
39
3
U4
Power Supply
TPS3801K33DCKR
TI
40
1
Y1
Crystal
FA-238 (24MHz)
EPSON TOYOCOM

Schematic Diagrams
S5U13709P00C100 Evaluation Board Seiko Epson Corporation 13
(Rev.1.1)
7. Schematic Diagrams
Figure 7.1 S5U13709P00C100 Schematics (1 of 4)

Schematic Diagrams
14 Seiko Epson Corporation S5U13709P00C100 Evaluation Board
(Rev.1.1)
Figure 7.2 S5U13709P00C100 Schematics (2of 4)
5 5
4 4
3 3
2 2
1 1
DD CC BB AA
2-3 : PIOVDD 1-2 : HIOVDD
RG0VOUT
VCP
FPSHIFT
YDIS
S1D13709
RG1VOUT
SEL5 SEL7 SEL6 SEL2 RG1CE SEL3 RG0CE SEL1
SEL10
SEL0 SEL8 TESTEN SEL9 SEL4
LDOVDD0
LDOVDD1
2-3 : PIOVDD 1-2 : HIOVDD
<Doc> <RevCode
>
<Title>
A3
24
Thursday, September 12, 2013
Title Size Document Number Rev Date: Sheet of
A5
D4
FPDAT1
A9
D0
A11
FPDAT0
A12
D7
A7
A15
D1
A2
A14
A6
D6
D2
A[15:0]
A4
A10
A8
D5
A3 FPDAT2 A1
D3
A13
A0 FPDAT3
SEL10
RD# 3
SEL4
WAIT#
3
SEL6
RG1CE
SEL9
MCLK 4
SEL7 SEL5
TESTEN
SEL8 SEL0 SEL1
WR# 3
RG0CE
CS# 3 RESET# 4
D[7:0]
3
SEL2 SEL3
A[15:0]
3
AS#
3
OSCI4
OSCO4
SEL10 RG1CE SEL6 SEL8 SEL1 TESTEN SEL4 SEL2 SEL0 SEL3 SEL5 SEL9 SEL7 RG0CE
FPSHIFT 3 FPDRDY 3 FPFRAME 3 FPLINE 3
FPDAT[3:0]
3
HIOVDD
PIOVDD_IC
HIOVDD_IC
PIOVDD
PIOVDD
LDOVDD0
HIOVDD_IC
HIOVDD
PIOVDD_IC
HIOVDD
LDOVDD1
HIOVDD PIOVDD
HIOVDD
LDOVDD1
PIOVDD
LDOVDD0
HIOVDD
JP5
A2-2PA-2.54DSA
12
T3
TH
R1510K
R2 0
R6
0
T5TH
R8 10K
T2
TH
R1010K R1610K R1210K
C2
1uF
SH1
XJ8A-0211
C4 1uF
JP6
A2-2PA-2.54DSA
12
C1 1uF
T1
TH
R9 10K R1910K
C9 0.1uF
R1 1K
R1110K
C3
1uF
R2010K
C8 0.1uF
C10
4.7uF
R1810K
T7TH
SH4 XJ8A-0211
C7 0.1uF
R1310K
JP3
A2-2PA-2.54DSA
21
SW1 219-12MST
1 2 3 4 5 6 7 8 9
24 23 22 21 20 19 18 17 16
10 12
11 15
14 13
C5
4.7uF
R5 0
JP1
A2-2PA-2.54DSA
21
JP4 A2-3PA-2.54DSA
23
1
C6 0.1uF
JP2
A2-3PA-2.54DSA
2
3 1
R4 0
T4TH
R3 0
T6TH
U1
S1D13709
21
25
24
23
22
26
34
27
30
29
31
28
32
33
35
36
37
38
39
40
41 42 43 44 45 46 47 48 49 52 50 51 53 54 55 56 57 58 59 60
61
62
63
64
65
66
69
68
67
75
76
77
3 4
10 11 12 13 14 15 16 17 18 19 20
72
71
70
73
74
78
79
80
1 2 5 6 7 8 9
VSS
FPDAT3/XD3
FPDAT2/XD2
FPDAT1/XD1
FPDAT0/XD0
NIOVDD
FPSHIFT/XSCL
FPDAT4/XECL
FPLINE/LP
FPDRDY/WF
VSS
FPDAT5/YSCL
FPFRAME/YD
YDIS
NIOVDD
SEL0
SEL1
NC
VCP
PLLVSS
NC
RG1VOUT
LDOVDD
VSS
RG1CE
VSS
XCG1
XCD1
MCLK
RD
SEL10
RESET
WR
TESTEN
CS
D7 D6 D5 D4
HIOVDD
D3
D2
D1
D0
VSS
WAIT
A15
AS
HIOVDD
A9
HIOVDD
A8
A3 A2 SEL7 SEL6 SEL5 SEL4 SEL3 SEL2 RG0CE VSS LDOVDD RG0VOUT NC
A12
A13
A14
A11
A10
A7
A6
A5
VSS A4 A1 A0 HIOVDD SEL9 SEL8
SH6 XJ8A-0211
R7 10K
C11 0.1uF
SW2 219-2MST
1 24
3
SH3
XJ8A-0211
SH5 XJ8A-0211
R1710K
C12 0.1uF
SH2 XJ8A-0211
R36 10K
R1410K

Schematic Diagrams
S5U13709P00C100 Evaluation Board Seiko Epson Corporation 15
(Rev.1.1)
Figure 7.3 S5U13709P00C100 Schematics (3of 4)
5 5
4 4
3 3
2 2
1 1
DD CC BB AA
Host I nt erf ace
Nomount
SULLINS SULLINS
Nomount
LED Backlight
Panel I nt erf ace
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<Title>
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Thursday, September 12,2013
Title Size Document Number Rev Date: Sheet of
D0 D1 D2 D3 D4 D5
D7
D5 D3
D0 D4
D6
D2 D1 D6 D7
FPDAT1
FPDAT3
FPDAT0
FPDAT0
FPDAT1
FPDAT1 FPDAT2 FPDAT2 FPDAT3 FPDAT3
A0
A1
A2
A3
A4
A6
A7
A5
A10
A11
A9
A12
A14
A15
A13
A11
A5
A4 A12
A2
A7 A12
A8
A8
A6 A2
A11
A10
A0
A3
A13 A9
A6
A15
A14
A3 A9
A1
A14 A1 A10
A4
A7 A5 A13
A8
A15
A0
FPDAT0
FPDAT0
FPDAT2 FPDAT0 FPDAT3 FPDAT1
FPDAT0
FPDAT2
FPDAT1
FPDAT3
FPDAT3 FPDAT2
FPDAT1 FPDAT2
CLK 4 WAIT# 2
RESET_BUS#4
D[7:0]
2
CS#
2
AS#
2
A[15:0] 2
D[7:0]
2
CS# 2 WAIT# 2 RESET_BUS# 4 CLK 4
A[15:0]
2
FPDRDY2
FPFRAME
2
FPSHIFT2
FPDAT[3:0]
2
FPLINE
2
LED_CTRL
4LED+ 4LED- 4
WR# 2
WR#
2
RD#
2
RD# 2
PIOVDD
5V_CON_SUPPLY 5V_CON_SUPPLY
HIOVDD
R44
10K
R52
10K
R43
10K
R22
10K
H2
A1-34PA-2,54DSA
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33
2 4
6 8
10 12 14 16 18 20 22 24 26 28 30 32 34
R51
10K
H4
HIF3FC-40PA-2.54 DSA
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
1 3 5 7 9
11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
R23 0
R42
10K
R50
10K
P1 PRPN202PAEN 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
2
4 6 8
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
P2 PRPN202PAEN 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
2
4
6 8
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
R41
10K
R49
10K
R40
10K
R48
10K
R21 22K
R39
10K
R47
10K
R38
10K
H1
A1-34PA-2,54DSA
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33
2 4
6
8
10 12 14 16 18 20 22 24 26 28 30 32 34
R46
10K
R37
10K
R45
10K
H3
HIF3FC-40PA-2.54 DSA
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
1 3 5 7 9
11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

Schematic Diagrams
16 Seiko Epson Corporation S5U13709P00C100 Evaluation Board
(Rev.1.1)
Figure 7.4 S5U13709P00C100 Schematics (4of 4)
5 5
4 4
3 3
2 2
1 1
DD CC BB AA
Clock Traceshould be as short as possible. Isolate Crystal with ground trace
Input Disable 1-2_Oscillator 2-3_Crystal
Surround crystal with ground island
PIOVDD Selection 1-2 3.3V 2-3 5.0V
Place circuit as close as poss ible to S1D13709
HIOVDD Select 1-2 3.3V 2-3 5.0V
CLKI Select 1-2 : Oscillator
Crystal 1-2 Short : Enabled
Voltage regulator 3.3V @ 800mA PCB HeatSinked
3.3V
GND
SATNLEY
Green
5V
Ih= 1.1A
POWER Cl ock
NS
1-2 Manual Reset 2-3 Host Interface Reset
RESET
White LED Driver VIN 2.7-18.0V
3.3V/800mA max 5.0V/600mA max
VOUT 38V/60mA max
Whi t e LED Dr i ver
3-4: Vout= 20m A
3-4, 5-6: Vout= 40mA
3-4, 5- 6, 7-8: Vout= 60mA
1-2 Open: ShutDown 1-2 Shor t : Drive
1-2 Open : Disable
with14- Pin DIP Socket 27MHz/50 ppm
2-3 : P1_ Connector
<Doc><RevCode
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<Title>
A3
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Thursday, September 12, 2013
Title Size Document NumberRev Date: Sheet of
LED-
CLK
3
OSCI 2
MCLK 2
OSCO 2
RESET# 2
RESET_BUS#
3
LED_CTRL 3 LED+ 3
LED-
3
5V
3.3V
HIOVDD
C22
10pF
HIOVDD
3.3V
3.3V
3.3V
5V HIOVDD 5V PIOVDD
3.3V
5V_CON_SUPPLY 5V
3.3V
JP11
A2-2PA-2.54DSA
1 2
U3 TPS61161A
1 2 34
5 6
FB COMP
GND SW
CTRL
VIN
TP1
U4 TPS3801K33DCKR
1 2 5
3
4
GND GND MR#
RESET#
VDD
JP7
A2-3PA-2.54DSA
1 2 3
SH8 XJ8A-0211
D2
CRS04
C24 0.1uF
R31
0
1 2
R30
10M
1 2
TP2
SH12 XJ8A-0211
F1
MINISMDC110F-2
12
L1
22uH VLCF5020T-220MR75-1
C20
0.1uF
1 2
SH13 XJ8A-0211
C21 10pF
1 2
SH9 XJ8A-0211
+C19
10uF/16V
SH14 XJ8A-0211
SH10 XJ8A-0211
U2
LM1117MPX-3.3
32
1
4
VIN VOUT
GND
VOUT
SH15 XJ8A-0211
R3210R3310
C25 1uF
Y1
FA-238 (24MHz)
1
3 2
4
#1
#3 #2
#4
SH16 XJ8A-0211
C16 0.01uF
R3410
D1 BG1111C
+C14
100uF/16V
JP12
A2-3PA-2.54DSA
1 2 3
SW3 KSC241J
2 4
31
SH11 XJ8A-0211
JP9
A2-3PA-2.54DSA
2
3 1
SH7 XJ8A-0211
+C18
100uF/10V
R29 240
JP8
A2-3PA-2.54DSA
1 2 3
C15 0.1uF
R28 0
C23
0.22uF
C17 0.1uF
TP3
C26 0.1uF
J1
A1-8PA-2.54DSA
1 3 5 7
2 4 6 8
+ + + +
+ + + +
OSC1
4-1571552-2
1 2 3 4 5 6 78
9 10 11 12 13 14
JP10
A2-3PA-2.54DSA
2
3
R35 10K
1