Epson S5U13700B00C User manual

Revision 1.0
S1D13700 Embedded Memory Graphics LCD Controller
S5U13700B00C Rev. 1.0 Evaluation
Board User Manual
Document Number: X42A-G-002-01
Status: Revision 1.0
Issue Date: 2005/07/15
© SEIKO EPSON CORPORATION 2005. All Rights Reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in
evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any
representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain
material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.

Page 2 Epson Research and Development
Vancouver Design Center
S1D13700 S5U13700B00C Rev. 1.0 Evaluation Board User Manual
X42A-G-002-01 Issue Date: 2005/07/15
Revision 1.0

Epson Research and Development Page 3
Vancouver Design Center
S5U13700B00C Rev. 1.0 Evaluation Board User Manual S1D13700
Issue Date: 2005/07/15 X42A-G-002-01
Revision 1.0
Table of Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Installation and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Configuration DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1 Host interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1.1 Epson PC Card Extender Support . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1.2 Host Bus Interface Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2 LCD Panel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.3 Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5 Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6 Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7 S5U13700B00C Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8 Connecting the S5U13700B00C to the PC Card Adapter . . . . . . . . . . . . . . 28
9 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9.1 Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9.2 Document Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
10 Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10.1 EPSON Mobile Graphics Engines (S1D13700) . . . . . . . . . . . . . . . . . 30
10.2 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Appendix A Epson PC Card Extender . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
A.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
A.2 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
A.3 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
A.4 Bus Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
A.5 16-Bit PC Card Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
A.6 Generic #1 / #2 Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
A.7 Epson Evaluation Boards . . . . . . . . . . . . . . . . . . . . . . . . . . 32
A.8 Epson Evaluation Board Header Pin Mapping . . . . . . . . . . . . . . . . . . 32

Page 4 Epson Research and Development
Vancouver Design Center
S1D13700 S5U13700B00C Rev. 1.0 Evaluation Board User Manual
X42A-G-002-01 Issue Date: 2005/07/15
Revision 1.0

Epson Research and Development Page 5
Vancouver Design Center
S5U13700B00C Rev. 1.0 Evaluation Board User Manual S1D13700
Issue Date: 2005/07/15 X42A-G-002-01
Revision 1.0
1 Introduction
This manual describes the setup and operation of the S5U13700B00C Rev. 1.0 Evaluation
Board. This evaluation board is designed as an evaluation platform for the S1D13700
Embedded Memory Graphics LCD Controller.
The S5U13700B00C is designed for connection to the Epson PC Card Extender
(S5UPCMCIAB00C), thus providing an easy connection to a laptop or a desktop computer
with a PC Card reader. This module can also be used with other native platforms via the
host connectors which provide the appropriate signals to support a variety of CPUs.
This user manual is updated as appropriate. Please check the Epson Research and Devel-
opment Website at www.erd.epson.com for the latest revision of this document before
beginning any development.
We appreciate your comments on our documentation. Please contact us via email at
documentati[email protected]n.com.

Page 6 Epson Research and Development
Vancouver Design Center
S1D13700 S5U13700B00C Rev. 1.0 Evaluation Board User Manual
X42A-G-002-01 Issue Date: 2005/07/15
Revision 1.0
2 Features
The S5U13700B00C Rev. 1.0 evaluation board includes the following features:
• 64-pin TQFP13 S1D13700F0x Embedded Memory Graphics LCD Controller
• Headers for connecting to various Host Bus Interfaces or to the Epson PC Card
Extender
• 0.1x0.1” header with all the LCD interface signals allowing connection to a LCD panel
• On-board 32MHz crystal and option to use an oscillator instead of the crystal
• On-board +3.3V regulator

Epson Research and Development Page 7
Vancouver Design Center
S5U13700B00C Rev. 1.0 Evaluation Board User Manual S1D13700
Issue Date: 2005/07/15 X42A-G-002-01
Revision 1.0
3 Installation and Configuration
The S5U13700B00C evaluation board incorporates a DIP switch and 9 jumpers, which
allow configuration of the board.
3.1 Configuration DIP Switches
An 8 position DIP switch (S1) is used to configure the S1D13700 for different Host Bus
interfaces and to select the FPSHIFT cycle time. The following figure shows the location
of DIP switch S1 on the S5U13700B00C.
Figure 3-1: Configuration DIP Switch (S1) Location
DIP Switch - S1
Top View

Page 8 Epson Research and Development
Vancouver Design Center
S1D13700 S5U13700B00C Rev. 1.0 Evaluation Board User Manual
X42A-G-002-01 Issue Date: 2005/07/15
Revision 1.0
All S1D13700 configuration inputs (CNF[4:0]) are fully configurable using DIP switch S1
as described below.
Table 3-1: Summary of Configuration Options
SDU13700B00C
S1-[8:1]
Configuration
S1D13700
Pin
Configuration State
1 (ON) 0 (OFF)
S1-[8:7] - Not used
S1-[6] AS# Generic Bus or M6800 Family Bus Interface M68K Family Bus Interface
S1-[5] CNF4 Indirect Addressing Mode Direct Addressing Mode
S1-[4:3] CNF[3:2]
Selects the host bus interface as follows:
CNF3 CNF2 Host Bus
00 Generic Bus
01 Reserved
1 0 M6800 Family Bus Interface
1 1 MC68K Family Bus Interface
S1-[2:1] CNF[1:0]
Selects the FPSHIFT cycle time (FPSHIFT:Clock Input) as follows:
CNF1 CNF0 FPSHIFT Cycle Time
0 0 FPSHIFT Divide 4:1
0 1 FPSHIFT Divide 8:1
1 0 FPSHIFT Divide 16:1
11 Reserved
= Required settings when using the PC Card adapter

Epson Research and Development Page 9
Vancouver Design Center
S5U13700B00C Rev. 1.0 Evaluation Board User Manual S1D13700
Issue Date: 2005/07/15 X42A-G-002-01
Revision 1.0
3.2 Configuration Jumpers
The S5U13700B00C has 9 jumper blocks which allow the configuration of the board.
Table 3-2: Jumper Summary
Jumper Function Position 1-2 Position 2-3 No Jumper
JP1 HIOVDD Normal — HIOVDD current
measurement
JP2 NIOVDD Normal — NIOVDD current
measurement
JP3 COREVDD Normal — COREVDD current
measurement
JP4 CLKI Source On Board Oscillator (U2) Host Interface Connector —
JP5 CLKI Input Disable Disable CLKI Input
(CLKI is tied to VSS)
Disable Crystal Input
(XCG1 is tied to VSS) —
JP6 Crystal Enable Enable Crystal Output Disable Crystal Output —
JP7 HIOVDD Voltage +3.3V +5V —
JP8 NIOVDD Voltage +3.3V +5V —
JP9 RESET Source Manual Reset Host Interface Reset —
= Required settings when using the PC Card adapter

Page 10 Epson Research and Development
Vancouver Design Center
S1D13700 S5U13700B00C Rev. 1.0 Evaluation Board User Manual
X42A-G-002-01 Issue Date: 2005/07/15
Revision 1.0
JP1 - HIOVDD
JP1 can be used to measure the current consumption of the S1D13700 host interface.
When the jumper is at position 1-2, normal operation is selected.
When no jumper is installed, host interface current consumption can be measured across
JP1.
Note
The HIOVDD voltage can be selected to be +3.3V or +5V using jumper JP7.
Figure 3-2: Configuration Jumper JP1 Location
Top View
JP1
Normal Operation HIOVDD current
measurement

Epson Research and Development Page 11
Vancouver Design Center
S5U13700B00C Rev. 1.0 Evaluation Board User Manual S1D13700
Issue Date: 2005/07/15 X42A-G-002-01
Revision 1.0
JP2 - NIOVDD
JP2 can be used to measure the current consumption of the S1D13700 LCD panel interface.
When the jumper is at position 1-2, normal operation is selected.
When no jumper is installed, panel interface current consumption can be measured across
JP2.
Note
The NIOVDD voltage can be selected to be +3.3V or +5V using jumper JP8.
Figure 3-3: Configuration Jumper JP2 Location
Top View
JP2
Normal Operation NIOVDD current
measurement

Page 12 Epson Research and Development
Vancouver Design Center
S1D13700 S5U13700B00C Rev. 1.0 Evaluation Board User Manual
X42A-G-002-01 Issue Date: 2005/07/15
Revision 1.0
JP3 - COREVDD
JP3 can be used to measure the current consumption of the S1D13700 core.
When the jumper is at position 1-2, normal operation is selected.
When no jumper is installed, core current consumption can be measured across JP3.
Figure 3-4: Configuration Jumper JP3 Location
Top View
JP3
Normal Operation COREVDD current
measurement

Epson Research and Development Page 13
Vancouver Design Center
S5U13700B00C Rev. 1.0 Evaluation Board User Manual S1D13700
Issue Date: 2005/07/15 X42A-G-002-01
Revision 1.0
JP4 - CLKI Source
JP4 is used to select the clock source for the S1D13700 CLKI input.
When the jumper is at position 1-2, the clock source is the on-board oscillator (U2).
When the jumper is at position 2-3, the clock source is from the host interface connector
(connector P1, pin 4).
Figure 3-5: Configuration Jumper JP4 Location
Top View
JP4
On-board oscillator Host interface
connector
(U2)

Page 14 Epson Research and Development
Vancouver Design Center
S1D13700 S5U13700B00C Rev. 1.0 Evaluation Board User Manual
X42A-G-002-01 Issue Date: 2005/07/15
Revision 1.0
JP5 - CLKI Input Disable
JP5 is used to disable the S1D13700 clock input that is not used by connecting it to ground.
When the jumper is at position 1-2, CLKI input is disabled.
When the jumper is at position 2-3, XCG1 input is disabled.
Note
When jumper JP5 is at position 1-2, jumper JP6 must also be at position 1-2.
When jumper JP5 is at position 2-3, jumper JP6 must also be at position 2-3.
Figure 3-6: Configuration Jumper JP5 Location
Top View
JP5
Disable CLKI input Disable XCG1input

Epson Research and Development Page 15
Vancouver Design Center
S5U13700B00C Rev. 1.0 Evaluation Board User Manual S1D13700
Issue Date: 2005/07/15 X42A-G-002-01
Revision 1.0
JP6 - Crystal Enable
JP6 is used to enable or disable the S1D13700 crystal output (XCD1).
When the jumper is at position 1-2, XCD1 output is enabled by connecting it to the crystal.
When the jumper is at position 2-3, XCD1 output is disabled by disconnecting it from the
crystal.
Note
When jumper JP6 is at position 1-2, jumper JP5 must also be at position 1-2.
When jumper JP6 is at position 2-3, jumper JP5 must also be at position 2-3.
Figure 3-7: Configuration Jumper JP6 Location
Top View
JP6
Enable XCD1 output Disable XCD1
output

Page 16 Epson Research and Development
Vancouver Design Center
S1D13700 S5U13700B00C Rev. 1.0 Evaluation Board User Manual
X42A-G-002-01 Issue Date: 2005/07/15
Revision 1.0
JP7 - HIOVDD Voltage
JP7 is used to select the voltage for HIOVDD.
When the jumper is at position 1-2, HIOVDD is +3.3V.
When the jumper is at position 2-3, HIOVDD is +5V.
Figure 3-8: Configuration Jumper JP7 Location
JP8 - NIOVDD Voltage
JP8 is used to select the voltage for NIOVDD.
When the jumper is at position 1-2, NIOVDD is +3.3V.
When the jumper is at position 2-3, NIOVDD is +5V.
Figure 3-9: Configuration Jumper JP8 Location
Top View
JP7
+3.3V +5V
Top View
JP8
+3.3V +5V

Epson Research and Development Page 17
Vancouver Design Center
S5U13700B00C Rev. 1.0 Evaluation Board User Manual S1D13700
Issue Date: 2005/07/15 X42A-G-002-01
Revision 1.0
JP9 - RESET# Source
JP9 is used to select the source of the RESET# signal to the S1D13700.
When the jumper is at position 1-2, the S1D13700 is reset by the on-board reset button
(SW1).
When the jumper is at position 2-3, the S1D13700 is reset by the system (connector P1, pin
21).
Figure 3-10: Configuration Jumper JP9 Location
Top View
JP9
Manual reset Host interface reset

Page 18 Epson Research and Development
Vancouver Design Center
S1D13700 S5U13700B00C Rev. 1.0 Evaluation Board User Manual
X42A-G-002-01 Issue Date: 2005/07/15
Revision 1.0
4 Technical Description
4.1 Host interface
4.1.1 Epson PC Card Extender Support
The evaluation board is designed to connect to the Epson PC Card Extender
(S5UPCMCIAB00C). The extender provides an easy connection to any computer with an
available PC Card slot. The S5U13700B00C directly connects to the extender via
connectors P1 and P2 (see Section 8, “Connecting the S5U13700B00C to the PC Card
Adapter” on page 28).
Note
When using this evaluation board with the Epson PC Card Extender, the maximum cur-
rent draw of 750mA provided by the PC Card slot may be exceeded. If the combination
of module and LCD panel exceeds this limit, an external 5V power supply may be re-
quired. The 5V regulated power supply may be connected to the 5V test point (TP5V1)
and the GND test point (TPGND1) to power the on-board regulator. In this case, the 0
Ohm resistor R2 must be removed from the board.
4.1.2 Host Bus Interface Support
The S1D13700 supports several host bus interfaces. All S1D13700 host interface pins are
available on connectors P1 and P2 allowing the S5U13700B00C to be used for interfacing
to other platforms.
All host interface signals must match HIOVDD of the S1D13700. The default value for
HIOVDD on the board is +3.3V, so it will work with the Epson PC Card Extender
(S5UPCMCIAB00C). HIOVDD can be selected between +3.3V and +5V using jumper
JP7.

Epson Research and Development Page 19
Vancouver Design Center
S5U13700B00C Rev. 1.0 Evaluation Board User Manual S1D13700
Issue Date: 2005/07/15 X42A-G-002-01
Revision 1.0
The following diagram shows the location of the host bus connectors (P1 and P2).
Connectors P1 and P2 are 2x2mm headers, 40 pins (20x2) each.
Figure 4-1: CPU Bus Connectors (P1 and P2) Location
For the pinout of connectors P1 and P2, refer to the schematics (see Section 6, “Schematic
Diagrams” on page 23).
Note
1. When the board is connected to a PC using the Epson PC Card Extender, the signal
AS# is not used and R12 must NOT be populated. AS# input of S1D13700 should
be connected to HIOVDD by setting the dip switch (S1) position 6 to ON.
2. When the board is connected to different platforms, the Epson PC Card Extender is
not used. If using MC68K Family Bus interface, the signal AS# is used and it can be
provided to the P2 connector by populating R12 and the dip switch (S1) position 6
must be set to OFF position to disconnect AS# input from HIOVDD.
P1 and P2
CPU Bus Connectors
Bottom View

Page 20 Epson Research and Development
Vancouver Design Center
S1D13700 S5U13700B00C Rev. 1.0 Evaluation Board User Manual
X42A-G-002-01 Issue Date: 2005/07/15
Revision 1.0
4.2 LCD Panel Interface
All the LCD interface signals are available on connector H1. Connector H1 is a 8x2 header,
0.1x0.1” pitch. The following diagram shows the location of the LCD connector (H1).
Figure 4-2: LCD Connector (H1) Location
For the pinout of connector H1, refer to the schematics (see Section 6, “Schematic
Diagrams” on page 23).
4.3 Clock
The S1D13700 accepts a clock signal from an oscillator or from a crystal. If the oscillator
is used, the crystal input (XCG1) must be connected to ground and the crystal output
(XCD1) must not be connected. If the crystal is used, the clock input (CLKI) must be
connected to ground. For details on connecting CLKI or XCG1 to ground, refer to the JP5
description (see “JP6 - Crystal Enable” on page 15).
The default configuration of the S5U13700B00C uses a 32MHz crystal. Jumper JP5 is in
position 1-2 to connect the CLKI input to ground because it is not used. Jumper JP6 is in
position 1-2 to connect the XCD1 output to the crystal.
The board can use the CLKI input instead of the crystal. To use the CLKI input, JP5 must
be moved to position 2-3 to connect the XCG1 input to ground. Also, jumper JP6 must be
moved to position 2-3 to disconnect the XCD1 output from the crystal.
The CLKI signal can be provided on the host interface connector or by an on-board oscil-
lator. Jumper JP4 is used to select the clock source. In position 1-2, the clock is provided
by populating an oscillator into the 14-pin DIP socket U2. In position 2-3, the clock must
be provided on pin 4 of the host interface connector P1.
H1
LCD Connector
Top View