Freescale Semiconductor MCF54455 User manual

© Freescale Semiconductor, Inc., 2012. All rights reserved.
Freescale Semiconductor MCF54455RM
Rev. 6.1, 03/2012
This is the MCF54455 Reference Manual set consisting of the following files:
• MCF54455 Reference Manual Errata, Rev 1
• MCF54455 Reference Manual, Rev 6
MCF54455 Reference Manual
by: Microcontroller Solutions Group

© Freescale Semiconductor, Inc., 2011. All rights reserved.
Freescale Semiconductor
Reference Manual Errata
MCF54455RMAD
Rev. 1, 11/2011
Table of Contents
This errata document describes corrections to the
MCF54455 Reference Manual, order number
MC54455RM. For convenience, the addenda items are
grouped by revision. Please check our website at
http://www.freescale.com for the latest updates.
The current available version of the MCF54455
Reference Manual is Revision 6.
MCF54455 Reference Manual
Errata
by: Microcontroller Solutions Group
1 Errata for Revision 6 . . . . . . . . . . . . . . . . . . . . . . . 2
2 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . 2

MCF54455 Reference Manual Errata, Rev. 1
Errata for Revision 6
Freescale Semiconductor2
1 Errata for Revision 6
2 Revision History
Table 2 provides a revision history for this document.
Table 1. MCF54455 Reference Manual Rev 6 Errata
Location Description
Section 16.2, “External Signal
Description”/Table 16-2/Page
16-11
Add pin N7 to the VSS pin list for the 360 TEPBGA.
Table 2. Revision History Table
Rev. Number Substantive Changes Date of Release
1.0 Initial release. Correct errors in section 16.2, “External Signal Description”. 11/2011

MCF54455 Reference Manual Errata, Rev. 1
Freescale Semiconductor 3
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© Freescale Semiconductor, Inc. 2011. All rights reserved.
MCF54455RMAD
Rev. 1
November 2011

MCF54455 Reference Manual
Devices Supported:
MCF54450
MCF54451
MCF54452
MCF54453
MCF54454
MCF54455
Document Number: MCF54455RM
Rev. 6
5/2011

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Freescale Semiconductor reserves the right to make changes without further
notice to any products herein. Freescale Semiconductor makes no warranty,
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particular purpose, nor does Freescale Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or
incidental damages. “Typical” parameters that may be provided in Freescale
Semiconductor data sheets and/or specifications can and do vary in different
applications and actual performance may vary over time. All operating
parameters, including “Typicals”, must be validated for each customer
application by customer’s technical experts. Freescale Semiconductor does
not convey any license under its patent rights nor the rights of others.
Freescale Semiconductor products are not designed, intended, or authorized
for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other
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rights reserved.
MCF54455RM
Rev. 6
5/2011

Freescale Semiconductor iii
Table of Contents
About This Book .............................................................................................................xxv
Audience .................................................................................................................xxv
Suggested Reading ..................................................................................................xxv
General Information ................................................................................................xxv
ColdFire Documentation ...................................................................................... xxvi
Conventions .......................................................................................................... xxvi
Register Figure Conventions ............................................................................... xxvii
Chapter 1
Overview
1.1 MCF5445xFamily Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.3 Operating Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.4 Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.5 Chip Level Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.6 Module-by-Module Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.6.1 Version 4 ColdFire variable-length RISC processor . . . . . . . . . . . . . . . . . . . . . 1-5
1.6.2 On-chip Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.6.3 Phase Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.6.4 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.6.5 Chip Configuration Module (CCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.6.6 Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.6.7 System Control Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.6.8 Crossbar Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.6.9 Peripheral Component Interconnect (PCI) Bus . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.6.10 Universal Serial Bus (USB) 2.0 On-The-Go (OTG) Controller . . . . . . . . . . . . . 1-6
1.6.11 DDR SDRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.6.12 FlexBus (External Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.6.13 Synchronous Serial Interface (SSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.6.14 ATA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.6.15 Fast Ethernet Media Access Controller (FEC MAC) . . . . . . . . . . . . . . . . . . . . . 1-7
1.6.16 Random Number Generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.6.17 Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.6.18 Software Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.6.19 Programmable Interrupt Timers (PIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.6.20 DMA Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.6.21 DMA Serial Peripheral Interface (DSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.6.22 Universal Asynchronous Receiver Transmitters (UARTs) . . . . . . . . . . . . . . . . 1-9

iv Freescale Semiconductor
1.6.23 I2C Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.6.24 Interrupt Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.6.25 Edge Port Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.6.26 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.6.27 General Purpose I/O interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.6.28 System Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.6.29 JTAG Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.7 Memory Map Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.7.1 Internal Peripheral Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.8 Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
Chapter 2
Signal Descriptions
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.2 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.3 Signal Primary Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.3.1 Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
2.3.2 PLL and Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.3.3 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
2.3.4 FlexBus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
2.3.5 SDRAM Controller Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.3.6 PCI Controller Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.3.7 Serial Boot Facility Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.3.8 External Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.3.9 DMA Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.3.10 Fast Ethernet Controller (FEC0 and FEC1) Signals . . . . . . . . . . . . . . . . . . . . 2-14
2.3.11 I2C I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.3.12 ATA Controller Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.3.13 DMA Serial Peripheral Interface (DSPI) Signals . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.3.14 Synchronous Serial Interface (SSI) Signals . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
2.3.15 Universal Serial Bus (USB) Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.3.16 UART Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.3.17 DMA Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.3.18 Debug Support Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.3.19 Test Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2.3.20 Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
2.4 External Boot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
Chapter 3
ColdFire Core
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2

Freescale Semiconductor v
3.2 Memory Map/Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.2.1 Data Registers (D0–D7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.2.2 Address Registers (A0–A6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.2.3 Supervisor/User Stack Pointers (A7 and OTHER_A7) . . . . . . . . . . . . . . . . . . . 3-8
3.2.4 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.2.5 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.2.6 Cache Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.2.7 MMU Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.2.8 Vector Base Register (VBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.2.9 Status Register (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.2.10 Memory Base Address Register (RAMBAR) . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.3.1 Version 4 ColdFire Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.3.2 Instruction Set Architecture (ISA_C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
3.3.3 Exception Processing Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
3.3.4 Processor Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
3.3.5 Instruction Execution Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
Chapter 4
Memory Management Unit (MMU)
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4.2.1 Address Space ID (ASID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.2.2 MMU Base Address Register (MMUBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4.2.3 MMU Control Register (MMUCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.2.4 MMU Operation Register (MMUOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.2.5 MMU Status Register (MMUSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
4.2.6 MMU Fault, Test, or TLB Address Register (MMUAR) . . . . . . . . . . . . . . . . . . . 4-8
4.2.7 MMU Read/Write Tag Entry Registers (MMUTR) . . . . . . . . . . . . . . . . . . . . . . . 4-8
4.2.8 MMU Read/Write Data Entry Register (MMUDR) . . . . . . . . . . . . . . . . . . . . . . . 4-9
4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
4.3.1 Virtual Memory Management Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
4.3.2 Debugging in a Virtual Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
4.3.3 Virtual Memory Architecture Processor Support . . . . . . . . . . . . . . . . . . . . . . . 4-15
4.3.4 Effective Address Attribute Determination . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
4.3.5 MMU Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
4.3.6 MMU TLB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
4.3.7 MMU Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
4.3.8 MMU Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
4.3.9 MMU Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23