Freescale Semiconductor MSC8144ADS User manual

MSC8144ADS Processor Board
Reference Manual
MSC8144ADSRM
Rev 0, February 2007
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MSC8144ADSRM
Rev. 0
2/2007
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MSC8144ADS Reference Manual, Rev. 0
Freescale Semiconductor iii
Contents
1General Information
1.1 Working Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1.1 Standalone Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.1.2 AMC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.1.3 Debugging Chain Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.1.3.1 Single . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.1.3.2 Chain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2 MSC8144ADS processor board Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.3 External Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.4 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.5 Definitions, Acronyms, and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.6 Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.7 Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
2Hardware Preparation and Installation
2.1 Unpacking Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.2 Installation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
3Memory Map
3.1 MPC8560 Host Mapping for the MSC8144ADS . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.2 MSC8144 Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
4Controls and Indicators
4.1 DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
4.2 Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.3 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4.4 Push Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
5ADS Functional Description
5.1 MSC8144 Memory System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.1.1 DDR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.1.2 DDR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5.1.3 DDR Connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
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Contents
5.1.4 Power for DDR Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.2 MPC8560 PCI Host Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.3 GETH Interface Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5.4 Serial RapidIO Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.5 TDM Ports and Peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.5.1 16-bit Voice Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.5.2 E1/T1 Framer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
5.5.3 TDM Bus Interconnection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
5.6 RS-232 on UART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.7 I2C Bus Interconnection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.7.1 Serial EEPROM for MPC8560 Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
5.7.2 Serial EEPROM for MSC8144 Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.7.3 RTC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.7.4 Codec. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
5.7.5 Power Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5.8 SPI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
5.9 Reset Operation and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
5.9.1 Reset Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
5.9.2 PORESET Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
5.9.3 Hard Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13
5.10 Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
5.10.1 Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
5.10.2 SHMOO Programmable Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
5.11 JTAG Debug Port Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
5.12 Host Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
5.12.1 Host Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
5.12.2 Host Memory Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
5.12.3 Host Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
5.12.3.1 Flash on LBIU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
5.12.3.2 DS3 Framer on LBIU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20
5.12.3.3 BCSR on FPGA (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
5.13 Interrupt Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22
5.14 Board Control and Status Registers (BCSRs) . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
5.14.1 BCSR0 Board Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24
5.14.2 BCSR1 Board Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25
5.14.3 BCSR2 Board Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25
5.14.4 BCSR3 Board Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26
5.14.5 BCSR4 Board Control Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27
5.14.6 BCSR5 Board Control Register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28
5.14.7 BCSR6 Board Control Register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28
5.14.8 BCSR7 Board Control Register 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28
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MSC8144ADS Reference Manual, Rev. 0
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Contents
5.14.9 BCSR8 Board Miscellaneous Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-29
5.14.10 BCSR9 Board Control Miscellaneous Register 2 . . . . . . . . . . . . . . . . . . . . . . 5-29
5.14.11 BCSR10 Board Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30
5.14.12 BCSR11 Board Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30
5.14.13 BCSR12 Board Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31
5.14.14 BCSR13 FA Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31
5.14.15 BCSR14 FA_M3 Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31
5.14.16 BCSR15 Reserved. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32
5.14.17 BCSR16 Board Status Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32
5.14.18 BCSR17 Board Status Register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32
5.14.19 BCSR18 Board Status Register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32
5.14.20 BCSR19 Board Status Register 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32
5.14.21 BCSR20 Board Status Register 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33
5.15 Power Supply System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33
5.15.1 Primary Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33
5.15.2 Power Supply Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33
5.16 Interconnection Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35
6Expansion Options
6.1 PTMC Expansion Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
6.2 AMC in ATCA Environment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10
7Replacing the MSC8144 DSP
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MSC8144ADS Reference Manual, Rev. 0
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Contents
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MSC8144ADS Reference Manual, Rev. 0
Freescale Semiconductor 1-1
General Information 1
This document describes the MSC8144ADS processor board. The MSC8144ADS processor
board is an application development system (ADS) that provides a complete debugging
environment for engineers developing applications for the Freescale MSC8144 DSP family.The
MSC8144ADS processor board is intended to serve as a platform for software and hardware
development in the MSC8144 processor environment. On-board resources and the associated
debugger enable developers to perform a variety of tasks: download and run code, set
breakpoints, display memory and registers, and connect proprietary h/w via the expansion
connector. This board answers the development needs of three different infrastructure
applications: wireless transcoding, IP telephony, and video transcoding. It can also be used as a
demonstration tool for these types of applications, and for control processing in applications such
as network routers and switches, mass storage subsystems, network appliances, and print and
imaging systems.
The MSC8144 device is a highly integrated DSP processor that contains four StarCore SC3400
DSP subsystems, 512 Kbyte of M2 shared memory, 10 Mbyte of M3 shared memory, L1
instruction and data caches optimized for packet telephony, 128 Kbyte of shared L2 instruction
cache, a DDR memory controller, a serial RapidIO® interface, two 10/100/1000Base-T Ethernet
controllers, an ATM Controller Supporting various ATM adaptation layers, eight 512-channel
time-division multiplexing (TDM) interfaces, a 16-channel DMA controller, 32-bit PCI interface
that runs at 66/33MHz, a UART interface, and an I2C interface.
The MSC8144ADS processor board is based on the 64-bit MSC8144 as a slave processor
controlled from an MPC8560 host processor via a PCI bus or GETH switch. However, the board
can be configured to bypass the host in certain situations. In addition, the board can function in a
standalone configuration or as an AMC card in the ATCA system. The ADS board uses a triple
AMC form factor.
1.1 Working Configurations
The MSC8144ADS has two basic operating modes, as discussed in the following sections. In
addition to the basic modes, there are two debugging chain options that can be used with either
operating mode.
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MSC8144ADS Reference Manual, Rev. 0
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General Information
1.1.1 Standalone Mode
The MSC8144ADS processor board can be run in a standalone mode, like other application
development systems, with direct connections to debuggers, power supply, and other external
connections.
1.1.2 AMC Mode
As opposed to standalone mode, in this mode, the MSC8144ADS processor board can be
connected to an additional MSC8144ADS processor board via the AMC ATCA edge connector.
For details on this mode, see Chapter 6, Expansion Options. The MSC8144ADS processor
board can also be connected to a TUNDRA platform via the edge connector.
1.1.3 Debugging Chain Options
Both options can be used in standalone and AMC modes.
1.1.3.1 Single
A single debugger connection can be used to debug applications for the MSC8144ADS processor
board. The debugger can be connected to either the MSC8144, or the MPC8560, or both of them
simultaneously (but independently). For a single connection to the MSC8144, use the P1
connection, and configure the board for this using the DIP switches (SW[2–3]). For a single
connection to the MPC8560, use the P11 connection, and configure the board for this using the
DIP switches (SW[2–3]).
1.1.3.2 Chain
A chain connection can be used to debug applications for the MSC8144ADS processor board. In
such a case, the debugger can only be connected to the MSC8144-MPC8560 via the P1
connection. Use the DIP switches (SW2.3) to configure the board for this.
1.2 MSC8144ADS processor board Features
The ADS is based on the MSC8144 as slave processor controlled from a PQIII (MPC8560) via
the PCI bus or GETH switch.
Supports MSC8144 running at up to 1000MHz, with cores voltages at 1V.
Dual DDR (DDR1 and DDR2) on SODIMM with 32 bits utilized, which provides a 256
Mbyte capacity, at a data rate up to 533 MHz
Programmable Hard Reset Configuration for MSC8144 is executed from PCI host
(MPC8560), I2C EEPROM or other sources.
Configuration and boot code for the host is loaded from Flash memory.
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External Connections
MSC8144ADS Reference Manual, Rev. 0
Freescale Semiconductor 1-3
PTMC expansion connectors carries most signals of both processors (except High Speed
signals)
PTMC pinout is designed to comply with the PT3MC or PT5MC standard.
RGMII GETH switch and SGMII GETH switch (expands connectivity options)
Two E1/T1 framers and codec on TDM bus.
Debugging is performed via an external command converter connected to the OnCE
14-pin header or COP 16-pin header for separate access to the processors.
JTAG Chain mode is provided via EOnCE header.
After MSC8144 reset, the MSC8144 Debug Enable/Disable options may be selected. The
processor EE pins enable and support the noted options.
Board Control and Status Register (BCSR) implemented in FPGA.
Board Identification and board status may be read via the BCSR.
Two SMB form RF-connectors enable the connection of up to two external pulse
generators to the two clock inputs of the MSC8144.
Various configurations (configurable via DIP switches or BCSR):
— Standalone mode with an external power 12 VDC @ 6 A.
— As an AMC card in the ATCA system.
— No host (the host MPC8560 stays in continued reset—configurable via SW 2.1). All
local bus operations are emulated by I2C expanders and controlled from the MSC8144.
Push Buttons
— Main Power-On Reset (for both Host and Slave);
— Hard Reset, Soft Reset, and NMI for MSC8144
1.3 External Connections
The MSC8144ADS processor board interconnects with external devices via the following set of
connectors (see Figure 1-1 and Figure 1-2):
1. Double RS232 9-pin connector (P2).
Upper - connects to Host UART port.
Lower - connects to MSC8144 UART port
2. Stereo Jack, LINE-IN (P4)
3. Stereo Jack, LINE-OUT (P6)
4. Four GETH ports RJ-45 connectors with LEDs (100 MHz displays green and 1GHz
displays amber) (P9)
5. Double RJ-48 eight pin E1/T1 connectors (J5)
6. Four 64-pin PTMC connectors for expansion cards (J1–J4).
7. Mictor LA Connectors hold host (MPC8560) LBC signals (P7–P8]).
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MSC8144ADS Reference Manual, Rev. 0
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General Information
8. 5 V connection for fan (J6)
Mounted: Fan is connected
Removed: Fan is not connected
9. Host (MPC8560) COP Debug connector 16-pin (P11 to work with host only with single
JTAG).
10. Power jack for 12 V @ 6 A external power supply (P10)
11. ISP 14-pin connector to program Altera FPGA. (P3)
12. MSC8144 OnCE Debug connector 14-pin (P1 for single or chain).
13. AMC edge connector (P26)
Figure 1-1. MSC8144ADS processor board External Connections (front view)
Figure 1-2. MSC8144ADS processor board External Connections (rear view)
321
1
45 6
7
8
11
12
910
13
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Block Diagram
MSC8144ADS Reference Manual, Rev. 0
Freescale Semiconductor 1-5
1.4 Block Diagram
Figure 1-3. MSC8144ADS Block Diagram
RJ48
E1/T1
Framer
U-Boot, Linux
RCW,Boot Code
FLASH
16Mbyte@16bit
DDR 256 Mbyte
SODIMM
PCI 32bit@66MHz
TDM[0:3]
UTOPIA2-16
sRIO-1x/4x
RGMII
SGMII1
256 Mbyte on DDR2
SODIMM
RGMII(Mode1,2)
MSC8144
on solderless socket
GE2
GE1
RGMII(Mode5)
RMII/SMII
TDM[0:3]
RJ48
12V
Ext 12V
PS
I2C
ZM7108
Ctrl
Core PS: 0.6~1.5V
COP
16pin
JTAG/OnCE
14pin
UTP16
TDM[4-7]/PCI32
GPHY
RJ45
RJ45
I2C
I2C EEPROM
Ext CLK
Clock
Synth.
66MHz
MMC
JTAG
Chain
FPGA
on FPGAa
RESETs
LEDs
DS3
Framer
TxD
RxD
I2C
OnCE
CLKIN
JTAG
Chain
JTAG
Chain
SPI
GETH RGMII
DB9
UART
CODEC
Vitesse 7380
Signals assignment:
Analog
TDM Bus
UTOPIA2 Bus
Diff Signals: SGMII & SRIO
GETH interfaces
I
2
C
SPI
solder
bridge
RS232
Power
Manager
ZY7007
ZY7007
ZY7115
ZY7115
DB9
STEREO
TDM[0:7]
88E1145
Cooper/SGMII
cfg2
cfg1,2
RS232
TLV320AIC22PT
PCI_CLK_IN
SPD
SPD
MICTOR
MICTOR
LA connector
IPMB over I2C
DIP-sw
TBD
opt.
R
T
C
I2C EEPROM
MPC8560
LBIUI2C2
COP
TSEC1
TSEC2
UART
PCI
FCC2/RMII
FCC1/UTP
MCC/TDM[0:7]
I2C1
RTC
JTAG
Mux
SGMII2
P0 P3 P5
P7
NMI
PCI_CLK
SPI
SerDes2
PTMC Ext. Cards
PT3MC
TP Header Field
RMII/SMII
Board Control Functions;
MSC8144 Pin Configuration
SPI
M/S
E1/T1
Framer
RJ45
RJ45
GPHY
Marvell
88E1145
ports
Switch
Cooper
Marvell
port 0
MICTOR
SerDes1
RESETs
SPI EEPROM
GETH switch
SGMII Marvell
88E6152
sRIO-4x
sRIO-4x
sRIO-4x
sRIO hw switch
AMC
Edge Connector
GPHY
Marvell
88E1145
port 3
SPI Flash
8M
a. Optional function
D
1,2
C
B
A
cfg
cfg
Mode <number> mean MSC8144 Pinmux Mode
(optional)
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MSC8144ADS Reference Manual, Rev. 0
1-6 Freescale Semiconductor
General Information
1.5 Definitions, Acronyms, and Abbreviations
Table 1-1. List of Terms and Acronyms
Term Definition
ADS Application Development System
AMC Advanced Mezzanine Card
ATCA Advanced Telecommunications Computing Architecture
BCSR Board Control and Status Register
BSP Board Support Package
COP Common On-chip Processor (JTAG Debug Port)
CS Chip Select
DDR Double Data Rate
DIP Dual-In-Line Package.
DMA Direct Memory Access
DUART Dual UART
EEPROM Electrical Erasable Programmable Memory
FLASH Non volatile reprogrammable memory.
FPGA Field-Programmable Gate Array
GETH Giga-bit Ethernet
GPCM General Purpose Chip-select Machine
GPL General Purpose Line
I2C Philips Semi Serial Bus
JTAG Joint Test Access Group refers to the IEEE debug and test protocols
LBIU Local Bus Interface Unit
LED Light Emitting Diode
lsb least significant bit
MII Media Independent Interface
msb most significant bit
PCI Peripheral Components Interconnect
Phy Physical Layer
POL Point-of-Load DC-DC converter
PSU Power Supply Unit
RGMII Reduced Gigabit Media Independent Interface
RMII Reduced Media Independent Interface
RCW(L,H) Reset Configuration Word (Low/High)
RTC Real Time Clock
SGMII Serial Gigabit Media Independent Interface
SerDes Serializer/Deserializer
SMB Type of Mini-RF connector
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Related Documentation
MSC8144ADS Reference Manual, Rev. 0
Freescale Semiconductor 1-7
1.6 Related Documentation
Freescale Documentation
— MSC8144 Data Sheet
— MSC8144 Reference Manual
— MSC8144 ADS Processor Board Hardware Getting Started
— MSC8144 ADS Using Code Warrior™ and MSC8144ADS Kit Configuration Guide
Third Party Documentation
— PICMG2.15 PCI Telecom Mezzanine/Carrier Card Specification
1.7 Specifications
The MSC8144ADS processor board specifications are given in Table 1-2.
SMII Serial Media Independent Interface
SODIMM Mini DIMM Form Factor
SPD Serial Present Detect
SPI Serial Peripheral Interface
SRIO Serial Rapid I/O High Speed differential interface
Table 1-2. MSC8144 ADS Specifications
Characteristics Specifications
Power requirements 12 V @ 4 A external DC power supply for stand alone mode.
No extra power supply for AMC mode - powering from ATCA carrier
board.
Operating temperature 0OC to 70OC
Storage temperature –25OC to 85OC
Relative humidity 5% to 90% (non-condensing)
Dimensions according to triple AMC form factor: Length: 222 mm
Width: 181 mm
Thickness: 1.6 mm
MSC8144 processor as slave and its interfaces Cores run up to 1 GHz @ 1 V
Memory Internal: M2,M3 Total: 10.96 Mbyte.
DDR2 Module 256 Mbyte space 32 bits wide + 8-bit ECC Memory Module in
SODIMM200 form factor (these are the quantities utilized from a device
whose capacity is 512 Mbyte, and 64 bit).
Clock = 200 MHz
Data rate = 400 MHz
Proprietary Interposer allows connecting a standard DDR1
SODIMM200 to the DDR2 SODIMM200 socket.
I2C EEPROM
SPI Flash 64 kB serial EEPROM for Boot Code. 8 Mbyte serial Flash for Program Code.
Table 1-1. List of Terms and Acronyms
Term Definition
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MSC8144ADS Reference Manual, Rev. 0
1-8 Freescale Semiconductor
General Information
Buses PCI PCI specification revision 2.2 compliant.
33 MHz/66 MHz,32-bit PCI interface. 3.3-V compatible
Availableonly when the Host (MPC8560) operates the MSC8144 as an
agent (present on J1, J2 of PTMC connection)
UTOPIA UTOPIA level II supports 8/16 bits up to 50MHz. Slave/Host Mode are
available (present on J4 of PTMC connection)
Communication
ports GETH Two GETH Controllers with five Ethernet physical interfaces: MII, RMII, SMII (all legacy interfaces), SGMII (over SerDes), RGMII.
RMII and SMII are supported over PT3MC expansion card.
TDM Eight TDM ports together support up to 2 K time-slots for receive and
2K time-slots for transmit -up to 256 PCM channels per link.
TDM ports are present on AMC connector and on PTMC (J3): four
ports for PT3MC configuration and eight ports for PT5MC board
configuration.
UART Bit rate up to 6.25 Mbps. RS-232 transceiver allows data exchange at
115 Kbps.
I2C Compliant with standard.
SPI Synchronous peripheral serial bus.
SerDes 1x/4x serial RapidIO endpoint operates at 1.25 Gbaud and complies
with Specification 1.2.
MPC8560 processor as host and its interfaces Core runs at up to 667 MHz @ 1.2 V
Memory DDR1 256 Mbyte space 64-bit wide in one standard SODIMM200.
Clock - 133 MHz
Data rate - 266 MHz
Flash 16 Mbyte, may be upgraded to 32 Mbyte
Buses PCI PCI specification revision 2.2 compliant.
33 MHz/ 66 MHz,32-bit PCI interface. 3.3-V compatible.
Acts as PCI Host.
Present on J1,J2 of PTMC.
Local Bus
I2CUp to 166 MHz, 32-bit.
Serial EEPROM 256 Kb for boot code.
Communication
ports GETH Two TSEC Controllers with five Ethernet physical interfaces: GMII, TBI, RGMII, RTBI; configured as RGMII on the ADS.
TDM Eight TDM ports, shared with MSC8144 communication ports
UART RS-232 transceiver allows data exchange at 115 Kbps
I2C Compliant with standard. Used to control peripheral devices
UTOPIA2 8/16-bit UTOPIA level II interfaces for ATM running up to 50 MHz. Acts
as a master
Table 1-2. MSC8144 ADS Specifications (Continued)
Characteristics Specifications
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MSC8144ADS Reference Manual, Rev. 0
Freescale Semiconductor 2-1
Hardware Preparation and Installation 2
This chapter provides unpacking instructions, hardware preparation, and installation instructions
for the MSC8144ADS processor board. For more details on hardware preparation, see the
Hardware Getting Started document for the MSC8144ADS processor board.
2.1 Unpacking Instructions
Note: If the shipping carton is damaged upon receipt, request carrier agent to be present
during unpacking and inspection of equipment.
Caution: Avoid touching areas of integrated circuitry; static discharge can damage
circuits.
Unpack equipment from shipping carton.
Refer to packing list and verify that all items are present.
Save packing material for storing and reshipping of equipment.
2.2 Installation Instructions
To install the MSC8144ADS processor board properly, perform the following steps in the order
indicated:
1. Verify that Jumpers and Switches are in default positions
(see Chapter 4, Controls and Indicators for a list of default positions).
2. Connect external cables in accordance with your development needs
(see Section 1.3 for details).
3. Connect PSU (to P10).
4. Move the power switch S1 to ON.
5. Verify that LEDs LD8 and LD1 display light. This indicates that board power is applied.
Verify that LD3 and LD4 briefly display light.
If the boot source is I2C, LD5 will display light during code loading.
6. Check for completion of the reset sequence-indicated by all relevant LEDs reaching a
steady state, according to their respective meanings. (see Figure 2-1 for location of
these LEDs, see Table 4-6 for a more detailed description).
7. Operate the CodeWarrior™ software to verify that the board has been installed properly.
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MSC8144ADS Reference Manual, Rev. 0
2-2 Freescale Semiconductor
Hardware Preparation and Installation
Figure 2-1. LED Locations
The LEDs operate in the following sequences during reset:
1. LD8 and LD1 light
2. LD3 and LD4 light and then go off
LD1
-
LD7
LD8
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MSC8144ADS Reference Manual, Rev. 0
Freescale Semiconductor 3-1
Memory Map 3
Each of the processors on the ADS board uses its own memory map.
3.1 MPC8560 Host Mapping for the MSC8144ADS
The MPC8560 Memory Controller governs all access to the processor memory slaves.
Consequently, the memory map may be reprogrammed according to specific user needs. After
performing a Hard Reset sequence, the debug host may initialize the memory controller via the
JTAG/COP connector to allow additional access to bus addressable peripherals. The SDRAM
DDR responds to all types of memory access including program, data, and direct memory
accesses (DMA).
Table 3-1. MPC8560 Host Memory Map
Address Range
Target
Device Name Volume
in Byte
Port
Size
in
Bits
MPC8560
Port Ext. Devices
00000000–0FFFFFFF
(3FFFFFFF) DDR DDR1
SODIMM on CS0 MT8VDDT3264H(I)Y-335 w/o ECC 256 Mbyte
(1 Gbyte opt) 64
10000000–3FFFFFFF
(40000000) —Empty Space
(if 1GB DDR1 not used) —~66 Mbyte —
40000000–400FFFFF Internal
8560 — Configuration Registers
Space 1 Mbyte 32
40100000–7FFFFFFF — Empty Space — ~1 Gbyte —
80000000–9FFFFFFF PCI ~512 Mbyte 32
80000000–87FFFFFF MSC8144 PCI port
88000000–8BFFFFFF PTMC Exp. Card
A0000000–F7FFFFFF — Empty Space — 1.5 Gbyte —
F8000000VF8007FFF LBIU GPCM BCSR on CS1 Altera
MAX2 32 Kbyte 8
F8008000–F800FFFF LBIU
GPCM DS3/E3 Framer on CS2 Exar
XRT79L71 32 Kbyte 8
F8010000–FDFFFFFF — Empty Space — ~88 Mbyte —
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MSC8144ADS Reference Manual, Rev. 0
3-2 Freescale Semiconductor
Memory Map
3.2 MSC8144 Mapping
The memory map defined in Table 3-2 is only a recommendation. The user can choose to work
with alternative memory mapping. It should be noted that the described mode is supported by
Freescale CodeWarrior and Smart-DOS debug tools.
FE000000–FEFFFFFF
(FFFFFFFF) LBIU
GPCM/UP
MA
FLASH on CS0 (PC28F256P30B85) (32 Mbyte)
16
FF000000–FFFFFFFF Intel Strata-Flash
PC28F128P30B85
(Ifusingthis16Mbyteoption,
FF000000–FFFFFFFF, and
the lower 16 Mbyte are free)
16 Mbyte
Table 3-2. MSC8144 Memory Map
Address Range
Target
Device Name Volume
in Byte
Port
Sizein
Bits
MSC8144
Port Ext. Devices
40000000–4FFFFFFF
(5FFFFFFF) DDR DDR2 SODIMM on CS0 MT8HTF6464HDY-53E 512 Mbyte @ 64 bit On-board 256 Mbyte @ 32
bit
is available
(512 Mbyte opt)
50000000–BFFFFFFF
(60000000– BFFFFFFF) — Empty Space — 1.5 Gbyte (512Mbyteifusing
the 512 Mbyte
DDR2 option)
C0000000–C007FFFF M2 Shared — Internal 512 Kbyte
C0080000–CFFFFFFF — Empty Space — 255.5 Mbyte
D0000000–D09FFFFF M3 Memory — Internal 10 Mbyte
D0A00000–DFFFFFFF — Empty Space — 1 Gbyte
E0000000–E7FFFFFF PCI port — — 128 Mbyte
E0000000–E3FFFFFF MPC8560 PCI Port
E4000000–E7FFFFFF PTMC Exp. Card
E8000000–FEDFFFFF — Empty Space — 366 Mbyte
FEE00000–FEE3FFFF Packet
Processor — Internal 256 Kbyte
FEE40000–FEEFFFFF Empty Space — 768 Kbyte
FEF00000–FEF17FFF Boot ROM — Internal 96 Kbyte
FEF18000–FFFFFFFF — Empty Space — 928 Kbyte
Table 3-1. MPC8560 Host Memory Map
Address Range
Target
Device Name Volume
in Byte
Port
Size
in
Bits
MPC8560
Port Ext. Devices
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MSC8144ADS Reference Manual, Rev. 0
Freescale Semiconductor 4-1
Controls and Indicators 4
This chapter describes controls and indicators of the MSC8144ADS processor board, which
includes switches, jumpers, LEDs, and push buttons.
Figure 4-1. MSC8144ADS Switches, Jumpers, LEDs, Push Buttons Locations
LD1-
LD7
LD8
JP2
JP5
SW2SW3
SW1SW4
SW5
SW6
SW7
SW8
JP9
JT1
JP8
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MSC8144ADS Reference Manual, Rev. 0
4-2 Freescale Semiconductor
Controls and Indicators
4.1 DIP Switches
Figure 4-1 shows the locations on the board of the DIP-switches. Table 4-1 describes the
possible settings of the DIP switches. Note that when ON, the value of the switch is zero. For
more detailed descriptions of the bits and fields, see the MSC8144 Reference Manual. Check the
default positions, and verify that the board is operational before changing any settings.
Table 4-2 on page 4 shows default DIP-switch positions when the configuration word is taken
from the I2C EEPROM. Notice certain values are indicated as not specified (x). These values are
taken from the EEPROM itself instead of from the DIP switch settings (which are ignored in
these cases). The specific default values are the same as in 4-3, with the following exceptions:
Pinmux = 6 (refer also to SW1.6–7)
Boot port = EEPROM (refer also to SW3.1–3)
Table 4-1 shows default DIP-switch positions when the reset configuration word is taken from
external pins.
Table 4-1. DIP Switch Settings Descriptions
Switch Setting Definitions
SW1 Configuration SW1.1–SW1.5: (RCW[5:9]) Device ID (labelled RCn on board)
00000 Device ID
(works together with SW4.8)
For more details, see MSC8144 Reference Manual, under the RCW field
SW1.6–SW1.7: (RCW[10,11]) Pin Muxing[1:0]
11 Sets Pin Mux Mode equal to 3 (default)
10 Sets Pin Mux Mode equal to 2
01 Sets Pin Mux Mode equal to 1
00 Sets Pin Mux Mode equal to 0
SW1.8: (RCW[12]) Boot Port Select (labelled RC12 on board)
0 Sets PCI as boot port (default)
(works together with SW3.1–SW3.3)
for more details and all options, see MSC8144 Reference Manual, under the
RCW field
Factory setting: '00000110
1 <- ->0
1: RC5 ON
2: RC6 ON
3: RC7 ON
4: RC8 ON
5: RC9 ON
6: RC10
OFF
7: RC11 OFF
8: RC12 ON
12345678
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