Freescale Semiconductor MC9S12DJ128E User manual

HCS12
Microcontrollers
freescale.com
MC9S12DT128
Device User Guide
Covers MC9S12DT128E, MC9S12DG128E,
MC9S12DJ128E, MC9S12DG128, MC9S12DJ128,
MC9S12DB128,MC9S12A128,SC515846,SC515847,
SC515848, SC515849, SC101161DT, SC101161DG,
SC101161DJ, SC102202, SC102203, SC102204,
SC102205
9S12DT128DGV2/D
V02.16
12 APR 2008

Device User Guide — 9S12DT128DGV2/D V02.16
2Freescale Semiconductor
Revision History
Version
Number Revision Date Effective Date Author Description of Changes
V01.00 18 Jun
2001 18 June 2001 Initial version (parent doc v2.03 dug for dp256).
V01.01 23 July
2001 23 July 2001 Updated version after review
V01.02 23 Sep
2001 23 Sep 2001
Changed Partname, added pierce mode, updated electrical
characteristics
some minor corrections
V01.03 12 Oct
2001 12 Oct 2001 Replaced Star12 by HCS12
V01.04 27 Feb
2002 27 Feb 2002
Updated electrical spec after MC-Qualification (IOL/IOH), Data for
Pierce, NVM reliability
New document numbering. Corrected Typos
V01.05 4 Mar
2002 4 Mar 2002 Increased VDD to 2.35V, removed min. oscillator startup Removed Document order number except from Cover Sheet
V01.06 8 July
2002 22 July 2002
Added:
Pull-up columns to signal table,
example for PLL Filter calculation,
Thermal values for junction to board and package,
BGND pin pull-up
Part Order Information
Global Register Table
Chip Configuration Summary
Modified:
Reduced Wait and Run IDD values
Mode of Operation chapter
changed leakage current for ADC inputs down to +-1uA
Corrected:
Interrupt vector table enable register inconsistencies
PCB layout for 80QFP VREGEN position
V02.00 11 Jan
2002 11 Jan 2002
NEW MASKSET
Changed part number from DTB128 to DT128
Functional Changes:
ROMCTL changes in Emulation Mode
80 Pin Byteflight package Option available
Flash with 2 Bit Backdoor Key Enable
Additional CAN0 routing to PJ7,6
Improved BDM with sync and acknowledge capabilities
New Part ID number
Improvements:
Significantly improved NVM reliability data
Corrections:
Interrupt vector Table
V02.01 01 Feb
2002 01 Feb 2002 Updated Block User Guide versions in preface Updated Appendix A Electrical Characteristics

Device User Guide — 9S12DT128DGV2/D V02.16
Freescale Semiconductor 3
V02.02 08 Mar
2002 08 Mar 2002
Changed XCLKS to PE7 in Table 2-2
Updated device part numbers in Figure 2-1
Updated BDM clock in Figure 3-1
Removed SIM description in overview & nUPOSC spec in Table A-15
Updated electrical spec of VDD & VDDPLL (Table A-4), IOL/IOH
(Table A-6), CINS (Table A-9), CIN (Table A-6 & A-15),
Updated interrupt pulse timing variables in Table A-6
Updated device part numbers in Figure 2-1
Added document numbers on cover page and Table 0-2
V02.03 14 Mar
2002 14 Mar 2002
Cleaned up Fig. 1-1, 2-1
Updated Section 1.5 descriptions
Corrected PE assignment in Table 2-2, Fig. 2-5,6,7.
Corrected NVM sizes in Sections 16, 17
Added IREF spec for 1ATD in Table A-8
Added Blank Check in A.3.1.5 and Table A-11
Updated CRG spec in Table A-15
V02.04 16 Aug
2002 16 Aug 2002
Added:
Pull-up columns to signal table,
Example for PLL Filter calculation,
Thermal values for junction to board and package,
BGND pin pull-up
Part Order Information
Global Register Table
Chip Configuration Summary
Device specific info on CRG
Modified:
Reduced Wait and Run IDD values
Mode of Operation chapter
Changed leakage current for ADC inputs down to +-1uA
Minor modification of PLL frequency/ voltage gain values
Corrected:
Pin names/functions on 80 pin packages
Interrupt vector table enable register inconsistencies
PCB layout for 80QFP VREGEN position
V02.05 12 Sep
2002 12 Sep 2002 Corrected: Register address mismatches in 1.5.1
V02.06 06 Nov
2002 06 Nov 2002
Removed document order no. from Revision History pages
Renamed "Preface" section to "Derivative Differences and
Document references". Added details for derivatives missing
CAN0/1/4, BDLC, IIC and/or Byteflight
Added 2L40K mask set in section 1.6
Added OSC User Guide in Preface, “Document References”
Added oscillator clock connection to BDM in S12_CORE in fig 3-1
Corrected several register and bit names in “Local Enable” column
of Table 5.1 Interrupt Vector Locations
Section HCS12 Core Block Description: mentioned alternate clock
of BDM to be equivalent to oscillator clock
Added new section: “Oscillator (OSC) Block Description”
Corrected in footnote of Table "PLL Characteristics": fOSC = 4MHz
Version
Number Revision Date Effective Date Author Description of Changes

Device User Guide — 9S12DT128DGV2/D V02.16
4Freescale Semiconductor
V02.07 29 Jan
2003 29 Jan 2003
Added 3L40K mask set in section 1.6
Corrected register entries in section 1.5.1 “Detailed Memory Map”
Updated description for ROMCTL in section 2.3.31
Updated section 4.3.3 “Unsecuring the Microcontroller”
Corrected and updated device-specific information for OSC
(section 8.1) & Byteflight (section 15.1)
Updated footnote in Table A-4 “Operating Conditions”
Changed reference of VDDM to VDDR in section A.1.8
Removed footnote on input leakage current in Table A-6 “5V I/O
Characteristics”
V02.08 26 Feb
2003 26 Feb 2003
Added part numbers MC9S12DT128E, MC9S12DG128E, and
MC9S12DJ128E in “Preface” and related part number references
Removed mask sets 0L40K and 2L40K from Table 1-3
V02.09 15 Oct
2003 15 Oct 2003
Replaced references to HCS12 Core Guide by the individual
HCS12 Block guides in Table 0-2, section 1.5.1, and section 6;
updated Fig.3-1 “Clock Connections” to show the individual HCS12
blocks
Corrected PIM module name and document order number in Table
0-2 “Document References”
Corrected ECT pulse accumulators description in section 1.2
“Features”
Corrected KWP5 pin name in Fig 2-1 112LQFP pin assignments
Corrected pull resistor CTRL/reset states for PE7 and PE4-PE0 in
Table 2.1 “Signal Properties”
Mentioned “S12LRAE” bootloader in Flash section 17
Corrected footnote on clamp of TEST pin under Table A-1
“Absolute Maximum Ratings”
Corrected minimum bus frequency to 0.25MHz in Table A-4
“Operating Conditions”
Replaced “burst programming” by “row programming” in A.3 “NVM,
Flash and EEPROM”
Corrected blank check time for EEPROM in Table A-11 “NVM
Timing Characteristics”
Corrected operating frequency in Table A-18 “SPI Master/Slave
Mode Timing Characteristics
V02.10 6 Feb
2004 6 Feb 2004
Added A128 information in “Derivative Differences”, 2.1 “Device
Pinout”, 2.2 “Signal Properties Summary”, Fig 23-2 & Fig 23-4
Added lead-free package option (PVE) in Table 0-2 “Derivative
Differences for MC9S12DB128” and Fig 0-1 “Order Partnumber
Example”
Added an “AEC qualified” row in the “Derivative Differences” tables
0-1 & 0-2.
V02.11 3 May
2004 3 May 2004
Added part numbers SC515846, SC515847, SC515848, and
SC515849 in “Derivative Differences” tables 0-1 & 0-2, section 2,
and section 23.
Corrected and added maskset 4L40K in tables 0-1 & 0-2 and
section 1.6.
Corrected BDLC module availability in DB128 80QFP part in
“Derivative Differences” table 0-2.
Version
Number Revision Date Effective Date Author Description of Changes

Device User Guide — 9S12DT128DGV2/D V02.16
Freescale Semiconductor 5
V02.12 06 Dec
2004 06 Dec 2004
Added maskset 0L94R
Added items VIH,EXTAL, VIL,EXTAL, & VHYS,EXTAL in table A-15
“Oscillator characteristics”
Removed item “Oscillator” from table A-4 “Operating Conditions” as
it is already covered in table “Oscillator Characteristics”
V02.13 04 Mar
2005 04 Mar 2005 Amended feature list of A128 in Table 0-1 “Derivative Differences”
V02.14 28 Apr
2005 28 Apr 2005
Updated cover page
Added part numbers SC101161DT, SC101161DG, SC101161DJ,
SC102202, SC102203, SC102204, & SC102205
Added masksets 5L40K &1L59W
Changed TJavg to 85°C in table A-12 “NVM Reliability” & added
footnote concerning data retention
V02.15 05 Oct
2005 05 Oct 2005 Updated “NVM Reliability” table A-12 format with added data. Added figure A-2 “Typical Endurance vs Temperature”
V02.16 12 Apr
2008 12 Apr 2008 Added maskset 2L94R
Version
Number Revision Date Effective Date Author Description of Changes

Device User Guide — 9S12DT128DGV2/D V02.16
6Freescale Semiconductor

Device User Guide — 9S12DT128DGV2/D V02.16
7
Freescale Semiconductor
Table of Contents
Section 1 Introduction
1.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.5 Device Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.5.1 Detailed Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1.6 Part ID Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Section 2 Signal Description
2.1 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.2 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.3 Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.1 EXTAL, XTAL — Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.2 RESET — External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.3 TEST — Test Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.4 XFC — PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.5 BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode Pin . . . . . 64
2.3.6 PAD[15] / AN1[7] / ETRIG1 — Port AD Input Pin [15] . . . . . . . . . . . . . . . . . . . . . 65
2.3.7 PAD[14:8] / AN1[6:0] — Port AD Input Pins [14:8]. . . . . . . . . . . . . . . . . . . . . . . . 65
2.3.8 PAD[7] / AN0[7] / ETRIG0 — Port AD Input Pin [7] . . . . . . . . . . . . . . . . . . . . . . . 65
2.3.9 PAD[6:0] / AN0[6:0] — Port AD Input Pins [6:0]. . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.3.10 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins . . . . . . . . . . . . . . . . . . . . 65
2.3.11 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins . . . . . . . . . . . . . . . . . . . . . . 65
2.3.12 PE7 / NOACC / XCLKS — Port E I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.3.13 PE6 / MODB / IPIPE1 — Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.3.14 PE5 / MODA / IPIPE0 — Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.3.15 PE4 / ECLK — Port E I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.3.16 PE3 / LSTRB / TAGLO — Port E I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.3.17 PE2 / R/W — Port E I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.3.18 PE1 / IRQ — Port E Input Pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.3.19 PE0 / XIRQ — Port E Input Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.3.20 PH7 / KWH7 — Port H I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Device User Guide — 9S12DT128DGV2/D V02.16
8Freescale Semiconductor
2.3.21 PH6 / KWH6 — Port H I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
2.3.22 PH5 / KWH5 — Port H I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
2.3.23 PH4 / KWH4 — Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
2.3.24 PH3 / KWH3 / SS1 — Port H I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
2.3.25 PH2 / KWH2 / SCK1 — Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
2.3.26 PH1 / KWH1 / MOSI1 — Port H I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
2.3.27 PH0 / KWH0 / MISO1 — Port H I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
2.3.28 PJ7 / KWJ7 / TXCAN4 / SCL / TXCAN0 — PORT J I/O Pin 7. . . . . . . . . . . . . . . 68
2.3.29 PJ6 / KWJ6 / RXCAN4 / SDA / RXCAN0 — PORT J I/O Pin 6 . . . . . . . . . . . . . . 69
2.3.30 PJ[1:0] / KWJ[1:0] — Port J I/O Pins [1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.3.31 PK7 / ECS / ROMCTL — Port K I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.3.32 PK[5:0] / XADDR[19:14] — Port K I/O Pins [5:0] . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.3.33 PM7 / BF_PSLM / TXCAN4 — Port M I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.3.34 PM6 / BF_PERR / RXCAN4 — Port M I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.3.35 PM5 / BF_PROK / TXCAN0 / TXCAN4 / SCK0 — Port M I/O Pin 5 . . . . . . . . . . 69
2.3.36 PM4 / BF_PSYN / RXCAN0 / RXCAN4/ MOSI0 — Port M I/O Pin 4. . . . . . . . . . 70
2.3.37 PM3 / TX_BF / TXCAN1 / TXCAN0 / SS0 — Port M I/O Pin 3 . . . . . . . . . . . . . . 70
2.3.38 PM2 / RX_BF / RXCAN1 / RXCAN0 / MISO0 — Port M I/O Pin 2. . . . . . . . . . . . 70
2.3.39 PM1 / TXCAN0 / TXB — Port M I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
2.3.40 PM0 / RXCAN0 / RXB — Port M I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
2.3.41 PP7 / KWP7 / PWM7 — Port P I/O Pin 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
2.3.42 PP6 / KWP6 / PWM6 — Port P I/O Pin 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
2.3.43 PP5 / KWP5 / PWM5 — Port P I/O Pin 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
2.3.44 PP4 / KWP4 / PWM4 — Port P I/O Pin 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
2.3.45 PP3 / KWP3 / PWM3 / SS1 — Port P I/O Pin 3. . . . . . . . . . . . . . . . . . . . . . . . . . 71
2.3.46 PP2 / KWP2 / PWM2 / SCK1 — Port P I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . 71
2.3.47 PP1 / KWP1 / PWM1 / MOSI1 — Port P I/O Pin 1. . . . . . . . . . . . . . . . . . . . . . . . 71
2.3.48 PP0 / KWP0 / PWM0 / MISO1 — Port P I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . 71
2.3.49 PS7 / SS0 — Port S I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
2.3.50 PS6 / SCK0 — Port S I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
2.3.51 PS5 / MOSI0 — Port S I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2.3.52 PS4 / MISO0 — Port S I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2.3.53 PS3 / TXD1 — Port S I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2.3.54 PS2 / RXD1 — Port S I/O Pin 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2.3.55 PS1 / TXD0 — Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2.3.56 PS0 / RXD0 — Port S I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Device User Guide — 9S12DT128DGV2/D V02.16
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2.3.57 PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2.4.1 VDDX,VSSX — Power & Ground Pins for I/O Drivers. . . . . . . . . . . . . . . . . . . . . 73
2.4.2 VDDR, VSSR — Power & Ground Pins for I/O Drivers & for Internal Voltage Regulator
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
2.4.3 VDD1, VDD2, VSS1, VSS2 — Internal Logic Power Supply Pins. . . . . . . . . . . . 73
2.4.4 VDDA, VSSA — Power Supply Pins for ATD and VREG . . . . . . . . . . . . . . . . . . 74
2.4.5 VRH, VRL — ATD Reference Voltage Input Pins . . . . . . . . . . . . . . . . . . . . . . . . 74
2.4.6 VDDPLL, VSSPLL — Power Supply Pins for PLL. . . . . . . . . . . . . . . . . . . . . . . . 74
2.4.7 VREGEN — On Chip Voltage Regulator Enable. . . . . . . . . . . . . . . . . . . . . . . . . 74
Section 3 System Clock Description
3.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Section 4 Modes of Operation
4.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.2 Chip Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.3 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
4.3.1 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.3.2 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.3.3 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.4 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.4.1 Stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.4.2 Pseudo Stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.4.3 Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.4.4 Run. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Section 5 Resets and Interrupts
5.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.2 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.2.1 Vector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5.3.1 I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5.3.2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Section 6 HCS12 Core Block Description
6.1 CPU Block Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Device User Guide — 9S12DT128DGV2/D V02.16
10 Freescale Semiconductor
6.1.1 Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.2 HCS12 Module Mapping Control (MMC) Block Description. . . . . . . . . . . . . . . . . . . 85
6.2.1 Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.3 HCS12 Multiplexed External Bus Interface (MEBI) Block Description . . . . . . . . . . . 85
6.3.1 Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.4 HCS12 Interrupt (INT) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.5 HCS12 Background Debug Module (BDM) Block Description. . . . . . . . . . . . . . . . . 86
6.5.1 Device-specific information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.6 HCS12 Breakpoint (BKP) Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Section 7 Clock and Reset Generator (CRG) Block Description
7.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Section 8 Oscillator (OSC) Block Description
8.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Section 9 Enhanced Capture Timer (ECT) Block Description
Section 10 Analog to Digital Converter (ATD) Block Description
Section 11 Inter-IC Bus (IIC) Block Description
Section 12 Serial Communications Interface (SCI) Block Description
Section 13 Serial Peripheral Interface (SPI) Block Description
Section 14 J1850 (BDLC) Block Description
Section 15 Byteflight (BF) Block Description
15.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Section 16 Pulse Width Modulator (PWM) Block Description
Section 17 Flash EEPROM 128K Block Description
Section 18 EEPROM 2K Block Description
Section 19 RAM Block Description

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Section 20 MSCAN Block Description
Section 21 Port Integration Module (PIM) Block Description
Section 22 Voltage Regulator (VREG) Block Description
Section 23 Printed Circuit Board Layout Proposal
Appendix A Electrical Characteristics
A.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
A.1.2 Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
A.1.4 Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
A.1.6 ESD Protection and Latch-up Immunity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 101
A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
A.2 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
A.2.1 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
A.2.2 Factors influencing accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
A.2.3 ATD accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
A.3 NVM, Flash and EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
A.3.1 NVM timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
A.3.2 NVM Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
A.4 Voltage Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
A.5 Reset, Oscillator and PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
A.5.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
A.5.2 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
A.5.3 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
A.6 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
A.7 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
A.7.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
A.7.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

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12 Freescale Semiconductor
A.8 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
A.8.1 General Multiplexed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Appendix B Package Information
B.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
B.2 112-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
B.3 80-pin QFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

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List of Figures
Figure 0-1 Order Partnumber Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 1-1 MC9S12DT128 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 1-2 MC9S12DT128 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 2-1 Pin assignments 112 LQFP for MC9S12DT128E, MC9S12DT128,
MC9S12DG128E, MC9S12DG128, MC9S12DJ128E, MC9S12DJ128, MC9S12DB128
MC9S12A128, SC515846, SC515847, SC515848, SC515849, SC101161DT, SC101161DG,
SC101161DJ, SC102202, SC102203, SC102204, and SC102205 . . . . . . . . . . . . . . . . . . 58
Figure 2-2 Pin Assignments in 80 QFP for MC9S12DG128E, MC9S12DG128,
MC9S12DJ128E, MC9S12DJ128, MC9S12A128, SC515847, SC515848, SC101161DG,
SC101161DJ, SC102203, and SC102204 Bondout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 2-3 Pin Assignments in 80 QFP for MC9S12DB128, SC515846, and SC102202 Bond-
out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 2-4 PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 2-5 Colpitts Oscillator Connections (PE7=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 2-6 Pierce Oscillator Connections (PE7=0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 2-7 External Clock Connections (PE7=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 3-1 Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 23-1 Recommended PCB Layout for 112LQFP Colpitts Oscillator . . . . . . . . . . . . 91
Figure 23-2 Recommended PCB Layout for 80QFP (MC9S12DG128E, MC9S12DG128,
MC9S12DJ128E, MC9S12DJ128, MC9S12A128, SC515847, SC515848, SC101161DG,
SC101161DJ, SC102203, and SC102204) Colpitts Oscillator . . . . . . . . . . . . . . . . . . . . . . 92
Figure 23-3 Recommended PCB Layout for 112LQFP Pierce Oscillator . . . . . . . . . . . . . 93
Figure 23-4 Recommended PCB Layout for 80QFP (MC9S12DG128E, MC9S12DG128,
MC9S12DJ128E, MC9S12DJ128, MC9S12A128, SC515847, SC515848, SC101161DG,
SC101161DJ, SC102203, and SC102204) Pierce Oscillator . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 23-5 Recommended PCB Layout for 80QFP (MC9S12DB128, SC515846, and
SC102202) Pierce Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure A-1 ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure A-2 Typical Endurance vs Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure A-3 Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure A-4 Jitter Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure A-5 Maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figure A-6 SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure A-7 SPI Master Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure A-8 SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Figure A-9 SPI Slave Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

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14 Freescale Semiconductor
Figure A-10 General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 23-6 112-pin LQFP mechanical dimensions (case no. 987) . . . . . . . . . . . . . . . . 138

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List of Tables
Table 0-1 Derivative Differences1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 0-2 Derivative Differences for MC9S12DB1281. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 0-3 Document References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 1-1 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
$0000 - $000FMEBI map 1 of 3 (HCS12 Multiplexed External Bus Interface) ................... 32
$0010 - $0014 MMC map 1 of 4 (HCS12 Module Mapping Control) ................................. 32
$0015 - $0016 INT map 1 of 2 (HCS12 Interrupt) .............................................................. 33
$0017 - $0017MMC map 2 of 4 (HCS12 Module Mapping Control) .................................. 33
$0018 - $0019Reserved ..................................................................................................... 33
$001A - $001B Device ID Register ((Table 1-3)) ............................................................... 33
$001C - $001D MMC map 3 of 4 (HCS12 Module Mapping Control, (Table 1-4)) ............ 33
$001E - $001EMEBI map 2 of 3 (HCS12 Multiplexed External Bus Interface) .................. 33
$001F - $001FINT map 2 of 2 (HCS12 Interrupt) ............................................................... 34
$0020 - $0027 Reserved .................................................................................................... 34
$0028 - $002F BKP (HCS12 Breakpoint) ........................................................................... 34
$0030 - $0031 MMC map 4 of 4 (HCS12 Module Mapping Control) ................................. 34
$0032 - $0033 MEBI map 3 of 3 (HCS12 Multiplexed External Bus Interface) .................. 34
$0034 - $003F CRG (Clock and Reset Generator) ............................................................ 35
$0040 - $007F ECT (Enhanced Capture Timer 16 Bit 8 Channels) ................................... 35
$0080 - $009F ATD0 (Analog to Digital Converter 10 Bit 8 Channel) ................................ 38
$00A0 - $00C7 PWM (Pulse Width Modulator 8 Bit 8 Channel) ........................................ 39
$00C8 - $00CF SCI0 (Asynchronous Serial Interface) ...................................................... 41
$00D0 - $00D7 SCI1 (Asynchronous Serial Interface) ....................................................... 41
$00D8 - $00DF SPI0 (Serial Peripheral Interface) ............................................................. 42
$00E0 - $00E7 IIC (Inter IC Bus) ....................................................................................... 42
$00E8 - $00EF BDLC (Byte Level Data Link Controller J1850) ......................................... 43
$00F0 - $00F7 SPI1 (Serial Peripheral Interface) .............................................................. 43
$00F8 - $00FF Reserved ................................................................................................... 43
$0100 - $010F Flash Control Register (fts128k2) .............................................................. 44
$0110 - $011B EEPROM Control Register (eets2k) .......................................................... 44
$011C - $011F Reserved for RAM Control Register .......................................................... 45
$0120 - $013F ATD1 (Analog to Digital Converter 10 Bit 8 Channel) ................................ 45
$0140 - $017F CAN0 (Motorola Scalable CAN - MSCAN) ................................................ 46

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Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout. . . . . . . . 47
$0180 - $01BF CAN1 (Motorola Scalable CAN - MSCAN)................................................ 48
$01C0 - $01FF Reserved ................................................................................................... 49
$0200 - $023F Reserved .................................................................................................... 49
$0240 - $027F PIM (Port Integration Module) .................................................................... 50
$0280 - $02BF CAN4 (Motorola Scalable CAN - MSCAN) ................................................ 52
$02C0 - $02FF Reserved ................................................................................................... 53
$0300 - $035F Byteflight .................................................................................................... 53
$0360 - $03FF Reserved ................................................................................................... 55
Table 1-3 Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 1-4 Memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 2-1 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 2-2 MC9S12DT128 Power and Ground Connection Summary . . . . . . . . . . . . . . . 72
Table 4-1 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 4-2 Clock Selection Based on PE7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 4-3 Voltage Regulator VREGEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 5-1 Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 23-1 Suggested External Component Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table A-1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table A-2 ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table A-3 ESD and Latch-Up Protection Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 100
Table A-4 Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table A-5 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table A-6 5V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table A-7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table A-8 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table A-9 ATD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table A-10 ATD Conversion Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table A-11 NVM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table A-12 NVM Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table A-13 Voltage Regulator Recommended Load Capacitances. . . . . . . . . . . . . . . . . 117
Table A-14 Startup Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table A-15 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table A-16 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table A-17 MSCAN Wake-up Pulse Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table A-18 SPI Master Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

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Table A-19 SPI Slave Mode Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table A-20 Expanded Bus Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

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Derivative Differences and Document References
Derivative Differences
(Table 0-1) and (Table 0-2) show the availability of peripheral modules on the various derivatives. For
details about the compatibility within the MC9S12D-Family refer also to engineering bulletin EB386.
Table 0-2 Derivative Differences for MC9S12DB1281
Table 0-1 Derivative Differences1
Modules
MC9S12DT128E3
MC9S12DT128
SC5158494
SC101161DT5
SC1022056
MC9S12DG128E3
MC9S12DG128
SC5158474
SC101161DG5
SC1022036
MC9S12DJ128E3
MC9S12DJ128
SC5158484
SC101161DJ5
SC1022046
MC9S12A128
# of CANs 3 2 2 0
CAN4 ✓✓ ✓ ✕
CAN1 ✓✕ ✕ ✕
CAN0 ✓✓ ✓ ✕
J1850/BDLC ✕✕ ✓ ✕
IIC ✓✓ ✓ ✓
Byteflight ✕✕ ✕ ✕
Package 112 LQFP 112 LQFP/80 QFP2112 LQFP/80 QFP2112 LQFP/80 QFP2
Package Code PV PV/FU PV/FU PV/FU
Mask set
1L40K3, 3L40K,
0L94R, 4L40K4,
1L59W5, 5L40K6,
2L94R
1L40K3, 3L40K,
0L94R, 4L40K4,
1L59W5, 5L40K6,
2L94R
1L40K3, 3L40K,
0L94R, 4L40K4,
1L59W5, 5L40K6,
2L94R
3L40K, 0L94R,
2L94R
Temp Options M, V, C M, V, C M, V, C C
AEC qualified Yes Yes Yes No
Notes An errata exists
contact Sales Office An errata exists contact Sales Office An errata exists contact Sales Office An errata exists contact Sales Office
Modules MC9S12DB128 SC5158464
SC1022026
MC9S12DB128
SC5158464
SC1022026
# of CANs 2 0
CAN4 ✓✕
CAN1 ✕✕
CAN0 ✓✕
J1850/BDLC ✕✕
IIC ✕✕
Byteflight ✓✓
Package 112 LQFP 80 QFP2

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NOTE:
1. ✓: Available for this device, ✕: Not available for this device.
2. 80 Pin bond-out for MC9S12DG128E, MC9S12DG128, MC9S12DJ128E, MC9S12DJ128, MC9S12A128, SC515847,
SC515848, SC101161DG, SC101161DJ, SC102203, and SC102204 is the same; MC9S12DB128, SC515846, and
SC102202 have a different bond-out.
3. Part numbers MC9S12DT128E, MC9S12DG128E, and MC9S12DJ128E are associated with the mask set 1L40K.
4. Part numbers SC515846, SC515847, SC515848, and SC515849 are associated with the mask set 4L40K.
5. Part numbers SC101161DT, SC101161DG, SC101161DJ are associated with the mask set 1L59W.
6. Part numbers SC102202, SC102203, SC102204, and SC102205 are associated with the mask set 5L40K which is not for
volume production.
The following figure provides an ordering number example for the MC9S12D128 devices.
Figure 0-1 Order Partnumber Example
The following items should be considered when using a derivative.
• Registers
– Do not write or read CAN0 registers (after reset: address range $0140 - $017F), if using a
derivative without CAN0 (see (Table 0-1) and (Table 0-2)).
– Do not write or read CAN1 registers (after reset: address range $0180 - $01BF), if using a
derivative without CAN1 (see (Table 0-1) and (Table 0-2)).
– Do not write or read CAN4 registers (after reset: address range $0280 - $02BF), if using a
derivative without CAN4 (see (Table 0-1) and (Table 0-2)).
– Do not write or read BDLC registers (after reset: address range $00E8 - $00EF), if using a
derivative without BDLC (see (Table 0-1) and (Table 0-2)).
– Do not write or read IIC registers (after reset: address range $00E0 - $00E7), if using a
derivative without IIC (see (Table 0-1) and (Table 0-2)).
Package Code PV/PVE FU
Mask set 3L40K, 0L94R, 4L40K4, 5L40K6,
2L94R
3L40K, 0L94R,
4L40K4, 5L40K6,
2L94R
Temp Options M, V, C/M, V M, V, C
AEC qualified Yes Yes
Notes An errata exists
contact Sales Office An errata exists contact Sales Office
Modules MC9S12DB128 SC5158464
SC1022026
MC9S12DB128
SC5158464
SC1022026
MC9S12 DJ128 C FU
Package Option
Temperature Option
Device Title
Controller Family
Temperature Options
C = -40˚C to 85˚C
V = -40˚C to 105˚C
M = -40˚C to 125˚C
Package Options
FU = 80QFP
PV = 112LQFP
PVE = lead-free 112LQFP