Freescale Semiconductor MPC561 User manual

MPC561/MPC563 Reference Manual
Additional Devices Supported:
MPC562
MPC564
MPC561RM
REV 1.2
08/2005

How to Reach Us:
Home Page:
www.freescale.com
E-mail:
suppor[email protected]
USA/Europe or Locations Not Listed:
Freescale Semiconductor
Technical Information Center, CH370
1300 N. Alma School Road
Chandler, Arizona 85224
[phone] or [phone]
suppor[email protected]
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
[phone] (English)
[phone] (English)
[phone] (German)
[phone] (French)
suppor[email protected]
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064, Japan
0120 191014 or [phone]
suppor[email protected]
Asia/Pacific:
Freescale Semiconductor Hong Kong Ltd.
Technical Information Center
2 Dai King Street
Tai Po Industrial Estate
Tai Po, N.T., Hong Kong
[phone]
suppor[email protected]
For Literature Requests Only:
Freescale Semiconductor Literature Distribution Center
P.O. Box 5405
Denver, Colorado 80217
1-800-441-2447 or 303-675-2140
Fax: [phone]
LDCForFreescaleSemiconduc[email protected]
Information in this document is provided solely to enable system and
software implementers to use Freescale Semiconductor products. There are
no express or implied copyright licenses granted hereunder to design or
fabricate any integrated circuits or integrated circuits based on the
information in this document.
Freescale Semiconductor reserves the right to make changes without further
notice to any products herein. Freescale Semiconductor makes no warranty,
representation or guarantee regarding the suitability of its products for any
particular purpose, nor does Freescale Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or
incidental damages. “Typical” parameters that may be provided in Freescale
Semiconductor data sheets and/or specifications can and do vary in different
applications and actual performance may vary over time. All operating
parameters, including “Typicals”, must be validated for each customer
application by customer’s technical experts. Freescale Semiconductor does
not convey any license under its patent rights nor the rights of others.
Freescale Semiconductor products are not designed, intended, or authorized
for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other
application in which the failure of the Freescale Semiconductor product could
create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended
or unauthorized application, Buyer shall indemnify and hold Freescale
Semiconductor and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized
use, even if such claim alleges that Freescale Semiconductor was negligent
regarding the design or manufacture of the part.
Freescale™ and the Freescale logo are trademarks of Freescale
Semiconductor, Inc. All other product or service names are the property
of their respective owners. The described product is a PowerPC
microprocessor. The PowerPC name is a trademark of IBM Corp. and used
under license
© Freescale Semiconductor, Inc. 2004, 2005. All rights reserved.
MPC561RM
REV 1.2
08/2005

MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor iii
Paragraph
Number Title Page
Number
About This Book lxxvii
Audience ..................................................................................................................... lxxvii
Organization ................................................................................................................ lxxvii
Suggested Reading ........................................................................................................ lxxx
Conventions and Nomenclature .................................................................................... lxxx
Notational Conventions ............................................................................................... lxxxi
Acronyms and Abbreviations ..................................................................................... lxxxii
References .................................................................................................................. lxxxiii
Chapter 1
Overview
1.1 Introduction ..................................................................................................................... 1-1
1.2 Block Diagram ................................................................................................................ 1-2
1.3 Key Features ................................................................................................................... 1-3
1.3.1 High-Performance CPU System ................................................................................. 1-3
1.3.1.1 RISC MCU Central Processing Unit (RCPU) ........................................................ 1-4
1.3.1.2 Unified System Interface Unit (USIU) ................................................................... 1-4
1.3.1.3 Burst Buffer Controller (BBC) Module .................................................................. 1-4
1.3.1.4 Flexible Memory Protection Unit ........................................................................... 1-5
1.3.1.5 Memory Controller ................................................................................................. 1-5
1.3.1.6 512-Kbytes of CDR3 Flash EEPROM Memory (UC3F) –
MPC563/MPC564 Only 1-5
1.3.1.7 32-Kbyte Static RAM (CALRAM) ........................................................................ 1-6
1.3.1.8 General Purpose I/O Support (GPIO) ..................................................................... 1-6
1.3.2 Nexus Debug Port (Class 3) ........................................................................................ 1-6
1.3.3 Integrated I/O System ................................................................................................. 1-6
1.3.3.1 Two Time Processor Units (TPU3) ........................................................................ 1-6
1.3.3.2 22-Channel Modular I/O System (MIOS14) .......................................................... 1-6
1.3.3.3 Two Enhanced Queued Analog-to-Digital Converter Modules (QADC64E) ........ 1-7
1.3.3.4 Three CAN 2.0B Controller (TouCAN) Modules .................................................. 1-7
1.3.3.5 Queued Serial Multi-Channel Module (QSMCM) ................................................. 1-8
1.3.3.6 Peripheral Pin Multiplexing (PPM) ........................................................................ 1-8
1.4 MPC561/MPC563 Optional Features ............................................................................. 1-9
1.5 Comparison of MPC561/MPC563 and MPC555 ........................................................... 1-9
1.6 Additional MPC561/MPC563 Differences ................................................................... 1-10
1.7 SRAM Keep-Alive Power Behavior ............................................................................. 1-11
1.8 MPC561/MPC563 Address Map .................................................................................. 1-11
Contents

MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor iv
Contents
Paragraph
Number Title Page
Number
1.9 Supporting Documentation List .................................................................................... 1-14
Chapter 2
Signal Descriptions
2.1 Signal Groupings ............................................................................................................2-1
2.2 Signal Summary ..............................................................................................................2-3
2.2.1 MPC561/MPC563 Signal Multiplexing ................................................................... 2-20
2.2.2 READI Port Signal Sharing ...................................................................................... 2-21
2.3 Pad Module Configuration Register (PDMCR) ............................................................ 2-22
2.4 Pad Module Configuration Register (PDMCR2) .......................................................... 2-23
2.5 MPC561/MPC563 Development Support Signal Sharing ............................................ 2-28
2.5.1 JTAG Mode Selection .............................................................................................. 2-29
2.5.2 BDM Mode Selection ............................................................................................... 2-30
2.5.3 Nexus Mode Selection .............................................................................................. 2-30
2.6 Reset State ..................................................................................................................... 2-31
2.6.1 Signal Functionality Configuration Out of Reset ..................................................... 2-31
2.6.2 Signal State During Reset ......................................................................................... 2-31
2.6.3 Power-On Reset and Hard Reset .............................................................................. 2-32
2.6.4 Pull-Up/Pull-Down ................................................................................................... 2-32
2.6.4.1 Pull-Up/Pull-Down Enable and Disable for 5-V Only and 2.6-V Only Signals .. 2-32
2.6.4.2 Pull-Down Enable and Disable for 5-V/2.6-V Multiplexed Signals .................... 2-32
2.6.4.3 Special Pull Resistor Disable Control Functionality (SPRDS) ............................ 2-32
2.6.4.4 Pull Device Select (PULL_SEL) .......................................................................... 2-33
2.6.5 Signal Reset States .................................................................................................... 2-33
Chapter 3
Central Processing Unit
3.1 RCPU Block Diagram .................................................................................................... 3-1
3.2 RCPU Key Features ........................................................................................................ 3-3
3.3 Instruction Sequencer ..................................................................................................... 3-3
3.4 Independent Execution Units .......................................................................................... 3-4
3.4.1 Branch Processing Unit (BPU) ................................................................................... 3-5
3.4.2 Integer Unit (IU) .........................................................................................................3-5
3.4.3 Load/Store Unit (LSU) ............................................................................................... 3-6
3.4.4 Floating-Point Unit (FPU) .......................................................................................... 3-6
3.5 Levels of the PowerPC ISA Architecture ....................................................................... 3-6
3.6 RCPU Programming Model ............................................................................................ 3-7

MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor v
Contents
Paragraph
Number Title Page
Number
3.7 User Instruction Set Architecture (UISA)
Register Set ............................................................................................................... 3-12
3.7.1 General-Purpose Registers (GPRs) ........................................................................... 3-12
3.7.2 Floating-Point Registers (FPRs) ............................................................................... 3-12
3.7.3 Floating-Point Status and Control Register (FPSCR) .............................................. 3-13
3.7.4 Condition Register (CR) ........................................................................................... 3-16
3.7.4.1 Condition Register CR0 Field Definition ............................................................. 3-17
3.7.4.2 Condition Register CR1 Field Definition ............................................................. 3-17
3.7.4.3 Condition Register CRn Field — Compare Instruction ....................................... 3-17
3.7.5 Integer Exception Register (XER) ............................................................................ 3-18
3.7.6 Link Register (LR) .................................................................................................... 3-19
3.7.7 Count Register (CTR) ............................................................................................... 3-19
3.8 VEA Register Set — Time Base (TB) .......................................................................... 3-20
3.9 OEA Register Set .......................................................................................................... 3-20
3.9.1 Machine State Register (MSR) ................................................................................. 3-20
3.9.2 DAE/Source Instruction Service Register (DSISR) ................................................. 3-22
3.9.3 Data Address Register (DAR) .................................................................................. 3-23
3.9.4 Time Base Facility (TB) — OEA ............................................................................. 3-23
3.9.5 Decrementer Register (DEC) .................................................................................... 3-23
3.9.6 Machine Status Save/Restore Register 0 (SRR0) ..................................................... 3-23
3.9.7 Machine Status Save/Restore Register 1 (SRR1) ..................................................... 3-23
3.9.8 General SPRs (SPRG0–SPRG3) .............................................................................. 3-24
3.9.9 Processor Version Register (PVR) ........................................................................... 3-25
3.9.10 Implementation-Specific SPRs ................................................................................. 3-25
3.9.10.1 EIE, EID, and NRI Special-Purpose Registers ..................................................... 3-25
3.9.10.2 Floating-Point Exception Cause Register (FPECR) ............................................. 3-26
3.9.10.3 Additional Implementation-Specific Registers ..................................................... 3-27
3.10 Instruction Set ............................................................................................................... 3-27
3.10.1 Instruction Set Summary .......................................................................................... 3-28
3.10.2 Recommended Simplified Mnemonics ..................................................................... 3-33
3.10.3 Calculating Effective Addresses ............................................................................... 3-34
3.11 Exception Model ........................................................................................................... 3-34
3.11.1 Exception Classes ..................................................................................................... 3-35
3.11.2 Ordered Exceptions ................................................................................................... 3-35
3.11.3 Unordered Exceptions ............................................................................................... 3-35
3.11.4 Precise Exceptions .................................................................................................... 3-36
3.11.5 Exception Vector Table ............................................................................................ 3-36
3.12 Instruction Timing ........................................................................................................ 3-37
3.13 User Instruction Set Architecture (UISA) .................................................................... 3-39
3.13.1 Computation Modes .................................................................................................. 3-39
3.13.2 Reserved Fields ......................................................................................................... 3-39

MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor vi
Contents
Paragraph
Number Title Page
Number
3.13.3 Classes of Instructions .............................................................................................. 3-40
3.13.4 Exceptions ................................................................................................................. 3-40
3.13.5 Branch Processor ...................................................................................................... 3-40
3.13.6 Instruction Fetching .................................................................................................. 3-40
3.13.7 Branch Instructions ................................................................................................... 3-40
3.13.7.1 Invalid Branch Instruction Forms ......................................................................... 3-40
3.13.7.2 Branch Prediction ................................................................................................. 3-40
3.13.8 Fixed-Point Processor ............................................................................................... 3-41
3.13.8.1 Fixed-Point Instructions ........................................................................................ 3-41
3.13.9 Floating-Point Processor ........................................................................................... 3-41
3.13.9.1 General .................................................................................................................. 3-41
3.13.9.2 Optional Instructions ............................................................................................ 3-41
3.13.10 Load/Store Processor ................................................................................................ 3-42
3.13.10.1 Fixed-Point Load with Update and Store with Update Instructions ..................... 3-42
3.13.10.2 Fixed-Point Load and Store Multiple Instructions ............................................... 3-42
3.13.10.3 Fixed-Point Load String Instructions .................................................................... 3-42
3.13.10.4 Storage Synchronization Instructions ................................................................... 3-42
3.13.10.5 Floating-Point Load and Store With Update Instructions .................................... 3-42
3.13.10.6 Floating-Point Load Single Instructions ............................................................... 3-42
3.13.10.7 Floating-Point Store Single Instructions ............................................................... 3-42
3.13.10.8 Optional Instructions ............................................................................................ 3-43
3.14 Virtual Environment Architecture (VEA) .................................................................... 3-43
3.14.1 Atomic Update Primitives ........................................................................................ 3-43
3.14.2 Effect of Operand Placement on Performance ......................................................... 3-43
3.14.3 Storage Control Instructions ..................................................................................... 3-43
3.14.4 Instruction Synchronize (isync) Instruction .............................................................. 3-43
3.14.5 Enforce In-Order Execution of I/O (eieio) Instruction ............................................. 3-44
3.14.6 Time Base ................................................................................................................. 3-44
3.15 Operating Environment Architecture (OEA) ................................................................ 3-44
3.15.1 Branch Processor Registers ...................................................................................... 3-44
3.15.1.1 Machine State Register (MSR) ............................................................................. 3-44
3.15.1.2 Branch Processors Instructions ............................................................................. 3-44
3.15.2 Fixed-Point Processor ............................................................................................... 3-44
3.15.2.1 Special Purpose Registers ..................................................................................... 3-44
3.15.3 Storage Control Instructions ..................................................................................... 3-45
3.15.4 Exceptions ................................................................................................................. 3-45
3.15.4.1 System Reset Exception and NMI (0x0100) ........................................................ 3-45
3.15.4.2 Machine Check Exception (0x0200) .................................................................... 3-46
3.15.4.3 Data Storage Exception (0x0300) ......................................................................... 3-48
3.15.4.4 Instruction Storage Exception (0x0400) ............................................................... 3-48
3.15.4.5 External Interrupt (0x0500) .................................................................................. 3-48

MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor vii
Contents
Paragraph
Number Title Page
Number
3.15.4.6 Alignment Exception (0x00600) .......................................................................... 3-49
3.15.4.7 Program Exception (0x0700) ................................................................................ 3-51
3.15.4.8 Floating-Point Unavailable Exception (0x0800) .................................................. 3-52
3.15.4.9 Decrementer Exception (0x0900) ......................................................................... 3-53
3.15.4.10 System Call Exception (0x0C00) ......................................................................... 3-54
3.15.4.11 Trace Exception (0x0D00) ................................................................................... 3-54
3.15.4.12 Floating-Point Assist Exception (0x0E00) ........................................................... 3-55
3.15.4.13 Implementation-Dependent Software Emulation Exception (0x1000) ................ 3-56
3.15.4.14 Implementation-Dependent Instruction Protection Exception (0x1300) .............. 3-57
3.15.4.15 Implementation-Specific Data Protection Error Exception (0x1400) .................. 3-58
3.15.4.16 Implementation-Dependent Debug Exceptions .................................................... 3-59
3.15.5 Partially Executed Instructions ................................................................................. 3-60
3.15.6 Timer Facilities .........................................................................................................3-61
3.15.7 Optional Facilities and Instructions .......................................................................... 3-61
Chapter 4
Burst Buffer Controller 2 Module
4.1 Key Features ................................................................................................................... 4-2
4.1.1 BIU Key Features ....................................................................................................... 4-2
4.1.2 IMPU Key Features .................................................................................................... 4-3
4.1.3 ICDU Key Features .................................................................................................... 4-3
4.1.4 DECRAM Key Features ............................................................................................. 4-4
4.1.5 Branch Target Buffer Key Features ............................................................................ 4-4
4.2 Operation Modes .............................................................................................................4-4
4.2.1 Instruction Fetch .........................................................................................................4-4
4.2.1.1 Decompression Off Mode ....................................................................................... 4-4
4.2.1.2 Decompression On Mode ....................................................................................... 4-5
4.2.2 Burst Operation of the BBC ........................................................................................ 4-5
4.2.3 Access Violation Detection ........................................................................................ 4-5
4.2.4 Slave Operation ...........................................................................................................4-6
4.2.5 Reset Behavior ............................................................................................................4-6
4.2.6 Debug Operation Mode .............................................................................................. 4-7
4.3 Exception Table Relocation (ETR) ................................................................................. 4-7
4.3.1 ETR Operation ............................................................................................................ 4-8
4.3.2 Enhanced External Interrupt Relocation (EEIR) ...................................................... 4-10
4.4 Decompressor RAM (DECRAM) Functionality .......................................................... 4-12
4.4.1 General-Purpose Memory Operation ........................................................................ 4-13
4.4.1.1 Memory Protection Violations ............................................................................. 4-14
4.4.1.2 DECRAM Standby Operation Mode .................................................................... 4-14
4.5 Branch Target Buffer .................................................................................................... 4-14

MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor viii
Contents
Paragraph
Number Title Page
Number
4.5.1 BTB Operation .......................................................................................................... 4-14
4.5.1.1 BTB Invalidation .................................................................................................. 4-16
4.5.1.2 BTB Enabling/Disabling ...................................................................................... 4-16
4.5.1.3 BTB Inhibit Regions ............................................................................................. 4-16
4.6 BBC Programming Model ............................................................................................ 4-17
4.6.1 Address Map ............................................................................................................. 4-17
4.6.1.1 BBC Special Purpose Registers (SPRs) ............................................................... 4-17
4.6.1.2 DECRAM and DCCR Block ................................................................................ 4-18
4.6.2 BBC Register Descriptions ....................................................................................... 4-19
4.6.2.1 BBC Module Configuration Register (BBCMCR) ............................................... 4-19
4.6.2.2 Region Base Address Registers (MI_RBA[0:3]) ................................................. 4-21
4.6.2.3 Region Attribute Registers (MI_RA[0:3]) ............................................................ 4-22
4.6.2.4 Global Region Attribute Register (MI_GRA) ...................................................... 4-23
4.6.2.5 External Interrupt Relocation Table Base Address Register (EIBADR) .............. 4-25
4.6.3 Decompressor Class Configuration Registers .......................................................... 4-25
Chapter 5
Unified System Interface Unit (USIU) Overview
5.1 Memory Map and Registers ............................................................................................ 5-2
5.1.1 USIU Special-Purpose Registers ................................................................................ 5-6
Chapter 6
System Configuration and Protection
6.1 System Configuration and Protection Features .............................................................. 6-3
6.1.1 System Configuration ................................................................................................. 6-3
6.1.1.1 USIU Pin Multiplexing ........................................................................................... 6-4
6.1.1.2 Arbitration Support ................................................................................................. 6-4
6.1.2 External Master Modes ............................................................................................... 6-4
6.1.2.1 Operation in External Master Modes ...................................................................... 6-5
6.1.2.2 Address Decoding for External Accesses ............................................................... 6-6
6.1.3 USIU General-Purpose I/O ......................................................................................... 6-6
6.1.4 Enhanced Interrupt Controller .................................................................................... 6-8
6.1.4.1 Key Features ........................................................................................................... 6-8
6.1.4.2 Interrupt Configuration ........................................................................................... 6-8
6.1.4.3 Regular Interrupt Controller Operation (MPC555/MPC556-Compatible Mode) 6-10
6.1.4.4 Enhanced Interrupt Controller Operation ............................................................. 6-11
6.1.4.4.1 Lower Priority Request Masking ...................................................................... 6-14
6.1.4.4.2 Backward Compatibility with MPC555/MPC556 ............................................ 6-14

MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor ix
Contents
Paragraph
Number Title Page
Number
6.1.4.5 Interrupt Overhead Estimation for Enhanced Interrupt Controller Mode ............ 6-16
6.1.5 Hardware Bus Monitor ............................................................................................. 6-17
6.1.6 Decrementer (DEC) .................................................................................................. 6-18
6.1.7 Time Base (TB) ........................................................................................................ 6-19
6.1.8 Real-Time Clock (RTC) ........................................................................................... 6-19
6.1.9 Periodic Interrupt Timer (PIT) .................................................................................. 6-20
6.1.10 Software Watchdog Timer (SWT) ............................................................................ 6-21
6.1.11 Freeze Operation ....................................................................................................... 6-23
6.1.12 Low Power Stop Operation ....................................................................................... 6-23
6.2 Memory Map and Register Definitions ........................................................................ 6-23
6.2.1 Memory Map ............................................................................................................ 6-23
6.2.2 System Configuration and Protection Registers ....................................................... 6-24
6.2.2.1 System Configuration Registers ........................................................................... 6-24
6.2.2.1.1 SIU Module Configuration Register (SIUMCR) .............................................. 6-25
6.2.2.1.2 Internal Memory Map Register (IMMR) .......................................................... 6-28
6.2.2.1.3 External Master Control Register (EMCR) ...................................................... 6-29
6.2.2.2 SIU Interrupt Controller Registers ........................................................................ 6-31
6.2.2.2.1 SIU Interrupt Pending Register (SIPEND) ....................................................... 6-32
6.2.2.2.2 SIU Interrupt Pending Register 2 (SIPEND2) .................................................. 6-32
6.2.2.2.3 SIU Interrupt Pending Register 3 (SIPEND3) .................................................. 6-33
6.2.2.2.4 SIU Interrupt Mask Register (SIMASK) .......................................................... 6-33
6.2.2.2.5 SIU Interrupt Mask Register 2 (SIMASK2) .................................................... 6-34
6.2.2.2.6 SIU Interrupt Mask Register 3 (SIMASK3) ..................................................... 6-35
6.2.2.2.7 SIU Interrupt Edge Level Register (SIEL) ....................................................... 6-35
6.2.2.2.8 SIU Interrupt Vector Register (SIVEC) ........................................................... 6-35
6.2.2.2.9 Interrupt In-Service Registers (SISR2 and SISR3) .......................................... 6-37
6.2.2.3 System Protection Registers ................................................................................. 6-37
6.2.2.3.1 System Protection Control Register (SYPCR) ................................................. 6-37
6.2.2.3.2 Software Service Register (SWSR) .................................................................. 6-38
6.2.2.3.3 Transfer Error Status Register (TESR) ............................................................. 6-39
6.2.2.4 System Timer Registers ........................................................................................ 6-40
6.2.2.4.1 Decrementer Register (DEC) ............................................................................ 6-40
6.2.2.4.2 Time Base SPRs (TB) ....................................................................................... 6-40
6.2.2.4.3 Time Base Reference Registers (TBREF0 and TBREF1) ................................ 6-41
6.2.2.4.4 Time Base Control and Status Register (TBSCR) ............................................ 6-42
6.2.2.4.5 Real-Time Clock Status and Control Register (RTCSC) ................................. 6-42
6.2.2.4.6 Real-Time Clock Register (RTC) ..................................................................... 6-43
6.2.2.4.7 Real-Time Clock Alarm Register (RTCAL) .................................................... 6-44
6.2.2.4.8 Periodic Interrupt Status and Control Register (PISCR) .................................. 6-44
6.2.2.4.9 Periodic Interrupt Timer Count Register (PITC) .............................................. 6-45
6.2.2.4.10 Periodic Interrupt Timer Register (PITR) ........................................................ 6-45

MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor x
Contents
Paragraph
Number Title Page
Number
6.2.2.5 General-Purpose I/O Registers ............................................................................. 6-46
6.2.2.5.1 SGPIO Data Register 1 (SGPIODT1) ............................................................. 6-46
6.2.2.5.2 SGPIO Data Register 2 (SGPIODT2) ............................................................. 6-47
6.2.2.5.3 SGPIO Control Register (SGPIOCR) .............................................................. 6-48
Chapter 7
Reset
7.1 Reset Operation ............................................................................................................... 7-1
7.1.1 Power-On Reset .......................................................................................................... 7-1
7.1.2 Hard Reset ................................................................................................................... 7-2
7.1.3 Soft Reset .................................................................................................................... 7-2
7.1.4 Loss of PLL Lock ....................................................................................................... 7-2
7.1.5 On-Chip Clock Switch ................................................................................................ 7-3
7.1.6 Software Watchdog Reset ........................................................................................... 7-3
7.1.7 Checkstop Reset .......................................................................................................... 7-3
7.1.8 Debug Port Hard Reset ............................................................................................... 7-3
7.1.9 Debug Port Soft Reset ................................................................................................. 7-3
7.1.10 JTAG Reset ................................................................................................................. 7-3
7.1.11 ILBC Illegal Bit Change ............................................................................................. 7-3
7.2 Reset Actions Summary .................................................................................................. 7-3
7.3 Data Coherency During Reset ........................................................................................ 7-4
7.4 Reset Status Register (RSR) ........................................................................................... 7-5
7.5 Reset Configuration ........................................................................................................ 7-7
7.5.1 Hard Reset Configuration ........................................................................................... 7-7
7.5.2 Hard Reset Configuration Word (RCW) .................................................................. 7-11
7.5.3 Soft Reset Configuration .......................................................................................... 7-13
Chapter 8
Clocks and Power Control
8.1 System Clock Sources .................................................................................................... 8-3
8.2 System PLL ..................................................................................................................... 8-3
8.2.1 Frequency Multiplication ............................................................................................ 8-4
8.2.2 Skew Elimination ........................................................................................................ 8-4
8.2.3 Pre-Divider .................................................................................................................. 8-4
8.2.4 PLL Block Diagram .................................................................................................... 8-4
8.2.5 PLL Pins ..................................................................................................................... 8-5
8.3 System Clock During PLL Loss of Lock ........................................................................ 8-6
8.4 Low-Power Divider ........................................................................................................ 8-6

MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor xi
Contents
Paragraph
Number Title Page
Number
8.5 Internal Clock Signals ..................................................................................................... 8-7
8.5.1 General System Clocks ............................................................................................. 8-10
8.5.2 Clock Out (CLKOUT) .............................................................................................. 8-13
8.5.3 Engineering Clock (ENGCLK) ................................................................................ 8-14
8.6 Clock Source Switching ................................................................................................ 8-14
8.7 Low-Power Modes ........................................................................................................ 8-16
8.7.1 Entering a Low-Power Mode .................................................................................... 8-16
8.7.2 Power Mode Descriptions ......................................................................................... 8-17
8.7.3 Exiting from Low-Power Modes .............................................................................. 8-17
8.7.3.1 Exiting from Normal-Low Mode .......................................................................... 8-18
8.7.3.2 Exiting from Doze Mode ...................................................................................... 8-19
8.7.3.3 Exiting from Deep-Sleep Mode ............................................................................ 8-19
8.7.3.4 Exiting from Power-Down Mode ......................................................................... 8-19
8.7.3.5 Low-Power Modes Flow ...................................................................................... 8-19
8.8 Basic Power Structure ................................................................................................... 8-21
8.8.1 General Power Supply Definitions ........................................................................... 8-21
8.8.2 Chip Power Structure ................................................................................................ 8-22
8.8.2.1 NVDDL ................................................................................................................ 8-22
8.8.2.2 QVDDL ................................................................................................................ 8-22
8.8.2.3 VDD ...................................................................................................................... 8-22
8.8.2.4 VDDSYN, VSSSYN ............................................................................................ 8-22
8.8.2.5 KAPWR ................................................................................................................ 8-22
8.8.2.6 VDDA, VSSA ....................................................................................................... 8-22
8.8.2.7 VFLASH ............................................................................................................... 8-22
8.8.2.8 VDDF, VSSF ........................................................................................................ 8-22
8.8.2.9 VDDH ................................................................................................................... 8-23
8.8.2.10 IRAMSTBY .......................................................................................................... 8-23
8.8.2.11 VSS ....................................................................................................................... 8-23
8.8.3 Keep-Alive Power ..................................................................................................... 8-24
8.8.3.1 Keep-Alive Power Configuration ......................................................................... 8-24
8.8.3.2 Keep-Alive Power Registers Lock Mechanism .................................................... 8-25
8.9 IRAMSTBY Supply Failure Detection ......................................................................... 8-27
8.10 Power-Up/Down Sequencing ....................................................................................... 8-27
8.11 Clocks Unit Programming Model ................................................................................. 8-29
8.11.1 System Clock Control Register (SCCR) ................................................................... 8-29
8.11.2 PLL, Low-Power, and Reset-Control Register (PLPRCR) ...................................... 8-33
8.11.3 Change of Lock Interrupt Register (COLIR) ............................................................ 8-36
8.11.4 IRAMSTBY Control Register (VSRMCR) .............................................................. 8-37

MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor xii
Contents
Paragraph
Number Title Page
Number
Chapter 9
External Bus Interface
9.1 Features ........................................................................................................................... 9-1
9.2 Bus Transfer Signals ....................................................................................................... 9-1
9.3 Bus Control Signals ........................................................................................................ 9-2
9.4 Bus Interface Signal Descriptions ................................................................................... 9-3
9.5 Bus Operations ................................................................................................................ 9-8
9.5.1 Basic Transfer Protocol .............................................................................................. 9-8
9.5.2 Single Beat Transfer ................................................................................................... 9-9
9.5.2.1 Single Beat Read Flow ........................................................................................... 9-9
9.5.2.2 Single Beat Write Flow ........................................................................................ 9-11
9.5.2.3 Single Beat Flow with Small Port Size ................................................................. 9-14
9.5.3 Data Bus Pre-Discharge Mode ................................................................................. 9-15
9.5.3.1 Operating Conditions ............................................................................................ 9-16
9.5.3.2 Initialization Sequence .......................................................................................... 9-16
9.5.4 Burst Transfer ........................................................................................................... 9-17
9.5.5 Burst Mechanism ...................................................................................................... 9-18
9.5.6 Alignment and Packaging of Transfers .................................................................... 9-29
9.5.7 Arbitration Phase ...................................................................................................... 9-32
9.5.7.1 Bus Request .......................................................................................................... 9-33
9.5.7.2 Bus Grant .............................................................................................................. 9-33
9.5.7.3 Bus Busy ............................................................................................................... 9-34
9.5.7.4 Internal Bus Arbiter .............................................................................................. 9-35
9.5.8 Address Transfer Phase Signals ................................................................................ 9-37
9.5.8.1 Transfer Start ........................................................................................................ 9-37
9.5.8.2 Address Bus .......................................................................................................... 9-37
9.5.8.3 Read/Write ............................................................................................................ 9-37
9.5.8.4 Burst Indicator ...................................................................................................... 9-37
9.5.8.5 Transfer Size ......................................................................................................... 9-38
9.5.8.6 Address Types ...................................................................................................... 9-38
9.5.8.7 Burst Data in Progress .......................................................................................... 9-40
9.5.9 Termination Signals .................................................................................................. 9-40
9.5.9.1 Transfer Acknowledge .......................................................................................... 9-40
9.5.9.2 Burst Inhibit .......................................................................................................... 9-40
9.5.9.3 Transfer Error Acknowledge ................................................................................ 9-40
9.5.9.4 Termination Signals Protocol ............................................................................... 9-40
9.5.10 Storage Reservation .................................................................................................. 9-42
9.5.11 Bus Exception Control Cycles .................................................................................. 9-45
9.5.11.1 Retrying a Bus Cycle ............................................................................................ 9-45
9.5.11.2 Termination Signals Protocol Summary ............................................................... 9-49

MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor xiii
Contents
Paragraph
Number Title Page
Number
9.5.12 Bus Operation in External Master Modes ................................................................. 9-49
9.5.13 Contention Resolution on External Bus .................................................................... 9-53
9.5.14 Show Cycle Transactions .......................................................................................... 9-55
Chapter 10
Memory Controller
10.1 Overview ....................................................................................................................... 10-1
10.2 Memory Controller Architecture .................................................................................. 10-3
10.2.1 Associated Registers ................................................................................................. 10-4
10.2.2 Port Size Configuration ............................................................................................ 10-4
10.2.3 Write-Protect Configuration ..................................................................................... 10-5
10.2.4 Address and Address Space Checking ...................................................................... 10-5
10.2.5 Burst Support ............................................................................................................ 10-5
10.2.6 Reduced Data Setup Time ........................................................................................ 10-6
10.2.6.1 Case 1: Normal Setup Time .................................................................................. 10-6
10.2.6.2 Case 2: Short Setup Time ..................................................................................... 10-7
10.2.6.3 Summary of Short Setup Time ............................................................................. 10-8
10.3 Chip-Select Timing ..................................................................................................... 10-10
10.3.1 Memory Devices Interface Example ...................................................................... 10-12
10.3.2 Peripheral Devices Interface Example .................................................................... 10-13
10.3.3 Relaxed Timing Examples ...................................................................................... 10-14
10.3.4 Extended Hold Time on Read Accesses ................................................................. 10-18
10.3.5 Summary of GPCM Timing Options ...................................................................... 10-22
10.4 Write and Byte Enable Signals ................................................................................... 10-24
10.5 Dual Mapping of the Internal Flash EEPROM Array ................................................ 10-24
10.6 Dual Mapping of an External Flash Region ............................................................... 10-26
10.7 Global (Boot) Chip-Select Operation ......................................................................... 10-27
10.8 Memory Controller External Master Support ............................................................. 10-28
10.9 Programming Model ................................................................................................... 10-31
10.9.1 General Memory Controller Programming Notes .................................................. 10-31
10.9.2 Memory Controller Status Registers (MSTAT) ..................................................... 10-32
10.9.3 Memory Controller Base Registers (BR0–BR3) .................................................... 10-32
10.9.4 Memory Controller Option Registers (OR0–OR3) ................................................ 10-34
10.9.5 Dual-Mapping Base Register (DMBR) .................................................................. 10-36
10.9.6 Dual-Mapping Option Register (DMOR) ............................................................... 10-37

MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor xiv
Contents
Paragraph
Number Title Page
Number
Chapter 11
L-Bus to U-Bus Interface (L2U)
11.1 General Features ........................................................................................................... 11-1
11.2 Data Memory Protection Unit Features ........................................................................ 11-1
11.3 L2U Block Diagram ...................................................................................................... 11-2
11.4 Modes Of Operation ..................................................................................................... 11-3
11.4.1 Normal Mode ............................................................................................................ 11-3
11.4.2 Reset Operation ......................................................................................................... 11-4
11.4.3 Peripheral Mode ........................................................................................................ 11-4
11.4.4 Factory Test Mode .................................................................................................... 11-4
11.5 Data Memory Protection ............................................................................................... 11-4
11.5.1 Functional Description .............................................................................................. 11-5
11.5.2 Associated Registers ................................................................................................. 11-6
11.5.3 L-Bus Memory Access Violations ............................................................................ 11-7
11.6 Reservation Support ...................................................................................................... 11-7
11.6.1 Reservation Protocol ................................................................................................. 11-8
11.6.2 L2U Reservation Support ......................................................................................... 11-8
11.6.3 Reserved Location (Bus) and Possible Actions ........................................................ 11-9
11.7 L-Bus Show Cycle Support .......................................................................................... 11-9
11.7.1 Programming Show Cycles .................................................................................... 11-10
11.7.2 Performance Impact ................................................................................................ 11-10
11.7.3 Show Cycle Protocol .............................................................................................. 11-10
11.7.4 L-Bus Write Show Cycle Flow ............................................................................... 11-10
11.7.5 L-Bus Read Show Cycle Flow ................................................................................ 11-11
11.7.6 Show Cycle Support Guidelines ............................................................................. 11-11
11.8 L2U Programming Model ........................................................................................... 11-12
11.8.1 U-Bus Access .......................................................................................................... 11-13
11.8.2 Transaction Size ...................................................................................................... 11-13
11.8.3 L2U Module Configuration Register (L2U_MCR) ................................................ 11-13
11.8.4 Region Base Address Registers (L2U_RBAx) ....................................................... 11-14
11.8.5 Region Attribute Registers (L2U_RAx) ................................................................. 11-15
11.8.6 Global Region Attribute Register (L2U_GRA) ...................................................... 11-16
Chapter 12
U-Bus to IMB3 Bus Interface (UIMB)
12.1 Features ......................................................................................................................... 12-1
12.2 UIMB Block Diagram .................................................................................................. 12-2
12.3 Clock Module ............................................................................................................... 12-2
12.4 Interrupt Operation ....................................................................................................... 12-3

MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor xv
Contents
Paragraph
Number Title Page
Number
12.4.1 Interrupt Sources and Levels on IMB3 ..................................................................... 12-3
12.4.2 IMB3 Interrupt Multiplexing .................................................................................... 12-4
12.4.3 ILBS Sequencing ...................................................................................................... 12-4
12.4.4 Interrupt Synchronizer .............................................................................................. 12-5
12.5 Programming Model ..................................................................................................... 12-6
12.5.1 UIMB Module Configuration Register (UMCR) ..................................................... 12-7
12.5.2 Test Control Register (UTSTCREG) ........................................................................ 12-8
12.5.3 Pending Interrupt Request Register (UIPEND) ........................................................ 12-8
Chapter 13
QADC64E Legacy Mode Operation
13.1 QADC64E Block Diagram ........................................................................................... 13-1
13.2 Key Features and Quick Reference Diagrams .............................................................. 13-2
13.2.1 Features of the QADC64E Legacy Mode Operation ................................................ 13-2
13.2.2 Memory Map ............................................................................................................ 13-3
13.2.3 Legacy and Enhanced Modes of Operation .............................................................. 13-4
13.2.4 Using the Queue and Result Word Table ................................................................. 13-5
13.2.5 External Multiplexing ............................................................................................... 13-5
13.3 Programming the QADC64E Registers ........................................................................ 13-7
13.3.1 QADC64E Module Configuration Register (QADMCR) ........................................ 13-8
13.3.1.1 Low Power Stop Mode ......................................................................................... 13-9
13.3.1.2 Freeze Mode ......................................................................................................... 13-9
13.3.1.3 Switching Between Legacy and Enhanced Modes of Operation ........................ 13-10
13.3.1.4 Supervisor/Unrestricted Address Space ............................................................. 13-10
13.3.2 QADC64E Interrupt Register (QADCINT) ............................................................ 13-12
13.3.3 Port Data Register (PORTQA and PORTQB) ........................................................ 13-13
13.3.4 Port Data Direction Register (DDRQA) ................................................................. 13-14
13.3.5 Control Register 0 (QACR0) .................................................................................. 13-14
13.3.6 Control Register 1 (QACR1) .................................................................................. 13-15
13.3.7 Control Register 2 (QACR2) .................................................................................. 13-17
13.3.8 Status Registers (QASR0 and QASR1) .................................................................. 13-20
13.3.9 Conversion Command Word Table ........................................................................ 13-27
13.3.10 Result Word Table .................................................................................................. 13-32
13.4 Analog Subsystem ...................................................................................................... 13-34
13.4.1 Analog-to-Digital Converter Operation .................................................................. 13-34
13.4.1.1 Conversion Cycle Times ..................................................................................... 13-35
13.4.1.2 Amplifier Bypass Mode Conversion Timing ..................................................... 13-35
13.4.2 Channel Decode and Multiplexer ........................................................................... 13-36
13.4.3 Sample Buffer Amplifier ........................................................................................ 13-36
13.4.4 Digital-to-Analog Converter (DAC) Array ............................................................ 13-36

MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor xvi
Contents
Paragraph
Number Title Page
Number
13.4.5 Comparator ............................................................................................................. 13-37
13.4.6 Bias ......................................................................................................................... 13-37
13.4.7 Successive Approximation Register ...................................................................... 13-37
13.4.8 State Machine ......................................................................................................... 13-37
13.5 Digital Subsystem ....................................................................................................... 13-37
13.5.1 Queue Priority ......................................................................................................... 13-38
13.5.2 Paused Sub-Queues ................................................................................................. 13-38
13.5.3 Boundary Conditions .............................................................................................. 13-40
13.5.4 Scan Modes ............................................................................................................. 13-41
13.5.4.1 Disabled Mode .................................................................................................... 13-41
13.5.4.2 Reserved Mode ................................................................................................... 13-41
13.5.4.3 Single-Scan Modes ............................................................................................. 13-42
13.5.4.3.1 Software Initiated Single-Scan Mode ............................................................. 13-42
13.5.4.3.2 External Trigger Single-Scan Mode ............................................................... 13-43
13.5.4.3.3 External Gated Single-Scan Mode ................................................................. 13-43
13.5.4.3.4 Periodic/Interval Timer Single-Scan Mode .................................................... 13-44
13.5.4.4 Continuous-Scan Modes ..................................................................................... 13-44
13.5.4.4.1 Software Initiated Continuous-Scan Mode ..................................................... 13-45
13.5.4.4.2 External Trigger Continuous-Scan Mode ....................................................... 13-46
13.5.4.4.3 External Gated Continuous-Scan Mode ......................................................... 13-46
13.5.4.4.4 Periodic/Interval Timer Continuous-Scan Mode ............................................ 13-47
13.5.5 QADC64E Clock (QCLK) Generation ................................................................... 13-47
13.5.6 Periodic / Interval Timer ......................................................................................... 13-51
13.5.7 Configuration and Control Using the IMB3 Interface ............................................ 13-51
13.5.7.1 QADC64E Bus Interface Unit ............................................................................ 13-51
13.5.7.2 QADC64E Bus Accessing .................................................................................. 13-52
13.6 Trigger and Queue Interaction Examples ................................................................... 13-54
13.6.1 Queue Priority Schemes .......................................................................................... 13-54
13.6.2 Conversion Timing Schemes .................................................................................. 13-63
13.7 QADC64E Integration Requirements ......................................................................... 13-66
13.7.1 Port Digital Input/Output Signals ........................................................................... 13-66
13.7.2 External Trigger Input Signals ................................................................................ 13-67
13.7.3 Analog Power Signals ............................................................................................. 13-67
13.7.3.1 Analog Supply Filtering and Grounding ............................................................ 13-69
13.7.4 Analog Reference Signals ....................................................................................... 13-71
13.7.5 Analog Input Signals .............................................................................................. 13-71
13.7.5.1 Analog Input Considerations .............................................................................. 13-73
13.7.5.2 Settling Time for the External Circuit ................................................................ 13-75
13.7.5.3 Error Resulting from Leakage ............................................................................ 13-75
13.7.5.4 Accommodating Positive/Negative Stress Conditions ....................................... 13-76

MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor xvii
Contents
Paragraph
Number Title Page
Number
Chapter 14
QADC64E Enhanced Mode Operation
14.1 QADC64E Block Diagram ........................................................................................... 14-1
14.2 Key Features and Quick Reference Diagrams .............................................................. 14-2
14.2.1 Features of the QADC64E Enhanced Mode Operation ............................................ 14-2
14.2.2 Memory Map ............................................................................................................ 14-3
14.2.3 Legacy and Enhanced Modes of Operation .............................................................. 14-4
14.2.4 Using the Queue and Result Word Table ................................................................. 14-5
14.2.5 External Multiplexing ............................................................................................... 14-5
14.3 Programming the QADC64E Registers ........................................................................ 14-7
14.3.1 QADC64E Module Configuration Register ........................................................... 14-8
14.3.1.1 Low Power Stop Mode ......................................................................................... 14-8
14.3.1.2 Freeze Mode ......................................................................................................... 14-9
14.3.1.3 Switching Between Legacy and Enhanced Modes of Operation .......................... 14-9
14.3.1.4 Supervisor/Unrestricted Address Space ............................................................. 14-10
14.3.2 QADC64E Interrupt Register ................................................................................. 14-11
14.3.3 Port Data Register ................................................................................................... 14-12
14.3.4 Port Data Direction Register ................................................................................... 14-13
14.3.5 Control Register 0 ................................................................................................... 14-14
14.3.6 Control Register 1 ................................................................................................... 14-16
14.3.7 Control Register 2 ................................................................................................... 14-18
14.3.8 Status Registers (QASR0 and QASR1) .................................................................. 14-22
14.3.9 Conversion Command Word Table ........................................................................ 14-28
14.3.10 Result Word Table .................................................................................................. 14-34
14.3.10.1 Analog Subsystem .............................................................................................. 14-36
14.3.11 Analog-to-Digital Converter Operation .................................................................. 14-36
14.3.11.1 Conversion Cycle Times ..................................................................................... 14-36
14.3.12 Channel Decode and Multiplexer ........................................................................... 14-37
14.3.13 Sample Buffer Amplifier ........................................................................................ 14-37
14.3.14 Digital to Analog Converter (DAC) Array ............................................................. 14-37
14.3.15 Comparator ............................................................................................................. 14-38
14.3.16 Bias ......................................................................................................................... 14-38
14.3.17 Successive Approximation Register ...................................................................... 14-38
14.3.18 State Machine ......................................................................................................... 14-38
14.4 Digital Subsystem ....................................................................................................... 14-38
14.4.1 Queue Priority ......................................................................................................... 14-39
14.4.2 Sub-Queues That are Paused .................................................................................. 14-39
14.4.3 Boundary Conditions .............................................................................................. 14-41
14.4.4 Scan Modes ............................................................................................................. 14-42
14.4.4.1 Disabled Mode .................................................................................................... 14-42

MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor xviii
Contents
Paragraph
Number Title Page
Number
14.4.4.2 Reserved Mode ................................................................................................... 14-42
14.4.4.3 Single-Scan Modes ............................................................................................. 14-43
14.4.4.3.1 Software Initiated Single-Scan Mode ............................................................. 14-43
14.4.4.3.2 External Trigger Single-Scan Mode ............................................................... 14-44
14.4.4.3.3 External Gated Single-Scan Mode ................................................................. 14-44
14.4.4.3.4 Periodic/Interval Timer Single-Scan Mode .................................................... 14-45
14.4.4.4 Continuous-Scan Modes ..................................................................................... 14-45
14.4.4.4.1 Software Initiated Continuous-Scan Mode ..................................................... 14-46
14.4.4.4.2 External Trigger Continuous-Scan Mode ....................................................... 14-47
14.4.4.4.3 External Gated Continuous-Scan Mode ......................................................... 14-47
14.4.4.4.4 Periodic/Interval Timer Continuous-Scan Mode ............................................ 14-48
14.4.5 QADC64E Clock (QCLK) Generation ................................................................... 14-48
14.4.6 Periodic/Interval Timer ........................................................................................... 14-50
14.4.7 Configuration and Control Using the IMB3 Interface ............................................ 14-51
14.4.7.1 QADC64E Bus Interface Unit ............................................................................ 14-51
14.4.7.2 QADC64E Bus Accessing .................................................................................. 14-51
14.5 Trigger and Queue Interaction Examples ................................................................... 14-53
14.5.1 Queue Priority Schemes .......................................................................................... 14-53
14.5.2 Conversion Timing Schemes .................................................................................. 14-62
14.6 QADC64E Integration Requirements ......................................................................... 14-65
14.6.1 Port Digital Input/Output Signals ........................................................................... 14-65
14.6.2 External Trigger Input Signals ................................................................................ 14-66
14.6.3 Analog Power Signals ............................................................................................. 14-66
14.6.3.1 Analog Supply Filtering and Grounding ............................................................ 14-67
14.6.4 Analog Reference Signals ....................................................................................... 14-69
14.6.5 Analog Input Signals .............................................................................................. 14-70
14.6.5.1 Analog Input Considerations .............................................................................. 14-71
14.6.5.2 Settling Time for the External Circuit ................................................................ 14-73
14.6.5.3 Error Resulting from Leakage ............................................................................ 14-73
14.6.5.4 Accommodating Positive/Negative Stress Conditions ....................................... 14-74
Chapter 15
Queued Serial Multi-Channel Module
15.1 Block Diagram .............................................................................................................. 15-1
15.2 Key Features ................................................................................................................. 15-2
15.2.1 MPC561/MPC563 QSMCM Details ........................................................................ 15-3
15.3 Memory Maps ............................................................................................................... 15-4
15.4 QSMCM Global Registers ............................................................................................ 15-6
15.4.1 Low-Power Stop Operation ...................................................................................... 15-6
15.4.2 Freeze Operation ....................................................................................................... 15-6

MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor xix
Contents
Paragraph
Number Title Page
Number
15.4.3 Access Protection ...................................................................................................... 15-6
15.4.4 QSMCM Interrupts ................................................................................................... 15-7
15.4.5 QSPI Interrupt Generation ........................................................................................ 15-8
15.4.6 QSMCM Configuration Register (QSMCMMCR) .................................................. 15-8
15.4.7 QSMCM Test Register (QTEST) ............................................................................. 15-9
15.4.8 QSMCM Interrupt Level Registers (QDSCI_IL, QSPI_IL) ..................................... 15-9
15.5 QSMCM Pin Control Registers .................................................................................. 15-10
15.5.1 Port QS Data Register (PORTQS) .......................................................................... 15-11
15.5.2 PORTQS Pin Assignment Register (PQSPAR) ..................................................... 15-12
15.5.3 PORTQS Data Direction Register (DDRQS) ......................................................... 15-13
15.6 Queued Serial Peripheral Interface ............................................................................. 15-14
15.6.1 QSPI Registers ....................................................................................................... 15-16
15.6.1.1 QSPI Control Register 0 (SPCR0) ...................................................................... 15-17
15.6.1.2 QSPI Control Register 1 (SPCR1) ...................................................................... 15-19
15.6.1.3 QSPI Control Register 2 (SPCR2) ...................................................................... 15-20
15.6.1.4 QSPI Control Register 3 (SPCR3) ...................................................................... 15-20
15.6.1.5 QSPI Status Register (SPSR) .............................................................................. 15-21
15.6.2 QSPI RAM .............................................................................................................. 15-22
15.6.2.1 Receive RAM ..................................................................................................... 15-23
15.6.2.2 Transmit RAM .................................................................................................... 15-23
15.6.2.3 Command RAM .................................................................................................. 15-23
15.6.3 QSPI Pins ................................................................................................................ 15-24
15.6.4 QSPI Operation ....................................................................................................... 15-25
15.6.4.1 Enabling, Disabling, and Halting the SPI ........................................................... 15-26
15.6.4.2 QSPI Interrupts ................................................................................................... 15-26
15.6.4.3 QSPI Flow .......................................................................................................... 15-27
15.6.5 Master Mode Operation .......................................................................................... 15-34
15.6.5.1 Clock Phase and Polarity .................................................................................... 15-35
15.6.5.2 Baud Rate Selection ............................................................................................ 15-35
15.6.5.3 Delay Before Transfer ........................................................................................ 15-36
15.6.5.4 Delay After Transfer ........................................................................................... 15-36
15.6.5.5 Transfer Length .................................................................................................. 15-37
15.6.5.6 Peripheral Chip Selects ....................................................................................... 15-37
15.6.5.7 Optional Enhanced Peripheral Chip Selects ....................................................... 15-37
15.6.5.8 Master Wraparound Mode .................................................................................. 15-38
15.6.6 Slave Mode ............................................................................................................. 15-39
15.6.6.1 Description of Slave Operation .......................................................................... 15-40
15.6.7 Slave Wraparound Mode ........................................................................................ 15-41
15.6.8 Mode Fault .............................................................................................................. 15-42
15.7 Serial Communication Interface ................................................................................. 15-42
15.7.1 SCI Registers .......................................................................................................... 15-45

MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor xx
Contents
Paragraph
Number Title Page
Number
15.7.2 SCI Control Register 0 (SCCxR0) .......................................................................... 15-46
15.7.3 SCI Control Register 1 (SCCxR1) .......................................................................... 15-47
15.7.4 SCI Status Register (SCxSR) .................................................................................. 15-48
15.7.5 SCI Data Register (SCxDR) ................................................................................... 15-50
15.7.6 SCI Pins .................................................................................................................. 15-51
15.7.7 SCI Operation ......................................................................................................... 15-51
15.7.7.1 Definition of Terms ............................................................................................ 15-51
15.7.7.2 Serial Formats ..................................................................................................... 15-52
15.7.7.3 Baud Clock ......................................................................................................... 15-52
15.7.7.4 Parity Checking .................................................................................................. 15-53
15.7.7.5 Transmitter Operation ......................................................................................... 15-54
15.7.7.6 Receiver Operation ............................................................................................. 15-55
15.7.7.7 Receiver Bit Processor ........................................................................................ 15-55
15.7.7.8 Receiver Functional Operation ........................................................................... 15-57
15.7.7.9 Idle-Line Detection ............................................................................................. 15-58
15.7.7.10 Receiver Wake-Up .............................................................................................. 15-58
15.7.7.11 Internal Loop Mode ............................................................................................ 15-59
15.8 SCI Queue Operation .................................................................................................. 15-59
15.8.1 Queue Operation of SCI1 for Transmit and Receive .............................................. 15-59
15.8.2 Queued SCI1 Status and Control Registers ............................................................ 15-59
15.8.2.1 QSCI1 Control Register (QSCI1CR) .................................................................. 15-60
15.8.2.2 QSCI1 Status Register (QSCI1SR) .................................................................... 15-61
15.8.3 QSCI1 Transmitter Block Diagram ........................................................................ 15-62
15.8.4 QSCI1 Additional Transmit Operation Features .................................................... 15-63
15.8.5 QSCI1 Transmit Flow Chart Implementing the Queue .......................................... 15-65
15.8.6 Example QSCI1 Transmit for 17 Data Bytes ......................................................... 15-67
15.8.7 Example SCI Transmit for 25 Data Bytes .............................................................. 15-68
15.8.8 QSCI1 Receiver Block Diagram ............................................................................. 15-70
15.8.9 QSCI1 Additional Receive Operation Features ...................................................... 15-70
15.8.10 QSCI1 Receive Flow Chart Implementing the Queue ............................................ 15-73
15.8.11 QSCI1 Receive Queue Software Flow Chart ......................................................... 15-74
15.8.12 Example QSCI1 Receive Operation of 17 Data Frames ......................................... 15-75
Chapter 16
CAN 2.0B Controller Module
16.1 Features ......................................................................................................................... 16-1
16.2 External Signals ............................................................................................................ 16-2
16.2.1 TouCAN Signal Sharing ........................................................................................... 16-3
16.3 TouCAN Architecture ................................................................................................... 16-3
16.3.1 Tx/Rx Message Buffer Structure .............................................................................. 16-4