Freescale Semiconductor MC68881 User manual

General Description
Programming Model
Operand Data Formats
Instruction Set
Coprocessor Programming
Exception Processing
Coprocessor Interface
Instruction Executive Timing
Functional Signal Descriptions
Bus Operation
Interfacing Methods
Electrical Specifications
Ordering Information and Mechanical Data
Glossary
Abbreviations and Acronyms
Index

FLOATING - POINT COPROCESSOR
USER'S MANUAL
Second Edition
PRENTICE HALL, Englewood Cliffs, N.J. 07632

Freescale Semiconductor, Inc., 1989
All rights reserved. No part of this book may be
reproduced, in any form or by any means,
without permission in writing from the publisher.
This document contains information on a new product. Specifications and
information herein are subject tochange without notice. Freescale reserves
the right to make changestoany products herein toimprove functioning or
design. Although the information in this document has been carefully re
-
viewedand is believed tobereliable, Freescale does not assume any liabiliy
arisingoutoftheapplication oruseofanyproductorcircuit described herein;
neither does it convey any license under its patent rights nor the rights of
other.
Freescale Semiconductor,Inc.generalpolicy doesnotrecommendtheuseofitscomponents
in life support applications where in a failure or malfunction of the component may directly
threaten lifeor injury. Per FreescaleTermsandConditions ofSale,theuserof IFreescalecomponents
in life support applications assumesall risk of such use and indemnifies Freescaleagainst
all damages.
Printed in the United States of America
I0987654321
ISBN 0-13-5b7009-B
Prentice - Hall International (UK) Limited, London
Prentice
- Hall of Australia Pty. Limited, Sydney
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- Hall of India Private Limited, New Delhi
Prentice - Hall of Japan, Inc., Tokyo
Simon
& Schuster Asia Pte. Ltd., Singapore
Editora Prentice
- Hall do Brasil, Ltda., Rio de Janeiro

TABLE OF CONTENTS
Paragraph Page
Number Title Number
1.1
1-2
1.2.1
1.2.2
1.3
1.3.1
1.3.2
1.3.3
1.3.4
1.4
1.4.1 •
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.5
1.6
Section 1
General Description
The Coprocessor Concept ........................................................... 1-2
Hardware Overview
................................................................... 1-3
Bus Interface Unit
................................................................. 1-6
Coprocessor Interface
........................................................... 1-9
Operand Data Formats ............................................................... 1-10
Integer Data Formats
............................................................. 1-11
Floating-Point Data Formats
................................................... 1-11
Packed Decimal String Real Data Format
.................................. 1-11
Data Format Summary
......................................................... 1-12
Instruction Set
.......................................................................... 1-12
Moves
............................................................................... 1-12
Move Multiple Registers ....................................................... 1-13
Monadic Operations ............................................................. 1-14
Dyadic Operations ............................................................... 1-14
Branch, Set, and Trap-On Condition ........................................ 1-15
Miscellaneous Instructions .................................................... 1-15
Addressing Modes .................................................................... 1-15
MC68882 Programming Considerations ................. ........................ 1-16
2.1
2.2
2.2.1
2.2.2
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.4
3.1
3.2
3.2.1
3.2.2
3.2.3
Section 2
Programming Model
Floating-Point Data Registers ....................................................... 2-1
Floating-Point Control Register .................................................... 2-2
FPCR
Exception Enable Byte ................................................... 2-2
FPCR Mode Control Byte....................................................... 2-3
Floating-Point Status Register............. .
........................................ 2-4
FPSR Floating-Point Condition Code Byte
................................. 2-4
FPSR Quotient Byte
............................................................. 2-6
FPSR Exception Status Byte
................................................... 2-6
FPSR Accrued Exception Byte
................................................ 2-7
Floating-Point Instruction Address Register
..................................... 2-8
Section 3
Operand Data Formats
Integer Data Formats ............................................................ . .... 3-1
Binary Real Data Formats
........................................................... 3-2
Normalized Numbers
........................................................... 3-4
Denormalized Numbers
........................................................ 3-4
Zeros................................................................................. 3-5
MC68881/MC68882 USER'S MANUAL FREESCALE
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Paragraph
Number
3,2.4
3.2.5
3.2.6
3.3
3,4
3.5
3,5.1
3,5.2
3.6
4.1
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.3
4.3.1
4.3.2
4.3.3
4.4
4.4.1
4.4:2
4.4.3
4.5
4.5.1
4.5,2
4.5.3
4.5.4
4.5.4.1
4.5.4.2
4.5.5
4.5.5.1
4.5.5.2
4.6
4.7
4.7.1
4.7.1.1
4.7.1.2
4.7.1.3
4.7.1.4
4.7.1.5
4:7.1.6
4.7.1.7
TABLE OF CONTENTS (Continued)
Page
Title Number
Infinities ............................................................................ 3-5
Not-A-Numbers ................................................................... 3-5
Binary Real Data Summary
.................................................... 3-6
Packed Decimal Real Data Format ................................................ 3-6
Internal Data Format.................................................................. 3~7
Format Conversions .................................................................. 3-8
Conversion to Extended Precision Data Format .......................... 3-8
Conversions to Other Data Formats ......................................... 3-9
Data Format Details................................................................... 3-9
Section 4
Instruction Set
Instruction Description Conventions.............................................. 4-1
Instruction Groups .................................................................... 4-1
Data Movement Operations ................................................... 4-2
Dyadic Operations ,.............................................................. 4-2
Monadic Operations............................................................. 4-3
Program Control Operations .................................................. 4-4
System Control Operations.................................................... 4-5
Computational Accuracy ............................................................. 4-5
Arithmetic Instructions ......................................................... 4-6
Transcendental Instructions ................................................... 4-7
Decimal Conversions............................................................ 4-8
Conditional Test Definitions ........................................................ 4-8
IEEE Nonaware Tests ........................................................... 4-10
IEEE Aware Tests ................................................................ 4-11
Miscellaneous Tests ............................................................. 4-12
Detailed Instruction Descriptions .................................................. 4-12
Addressing Modes............................................................... 4-12
Instruction Description Format
............................................... 4-13
Operation Tables...............
, ................................................. 4-13
NANs
................................................................................ 4-15
Nonsignaling NANs ........................................................ 4-15
Signaling NANs ............................................................. 4-15
Operation Post Processing..................................................... 4-15
Setting Floating-Point Condition Codes............................... 4-I6
Underflow, Round, Overflow ............................................ 4-16
Individual Instruction Descriptions ................................................ 4-17
Instruction Encoding Details ........................................................ 4-125
General Type Coprocessor Instruction Format ........................... 4-125
Register-to-Register Instructions ........................................ 4-127
External Operand-to-Register Instructions............................ 4-127
Move Constant to Floating-Point Data Register Instructions..... 4-129
Move to External Destination Instructions ........................... 4-129
Move System Control Register Instructions ......................... 4-130
Move Multiple Floating-Point Data Registers Instructions ........ 4-131
Undefined, Reserved Command Words .............................. 4-133
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vi MC68881/MC68882 USER'S MANUAL

Paragraph
Number
4.7.2
4.7.3
4.7.4
4.7.5
4.8
4.8.1
4.8.2
4.8.3
4.8.4
4.8.5
4.8.6
4.9
5.1
5.1.1
5.1.1.1
5.1.1.2
5.1.2
5.1.2.1
5.1.2.2
5.1.2.3
5.1.2.4
5.2
5.2.1
5.2.2
5.2.3
5.2.3.1
5.2.3.2
5.2.3.3
5.2.3.4
5.2.3.5
5.2.3.6
5.2.4
6.1
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
TABLE OF CONTENTS (Continued)
Title Page
Number
FDBcc, FScc, and FTRAPcc Instruction Formats .........................
Conditional Branch Instruction Format ....................................
Save Instruction Format: ......................................................
Restore Instruction Format ...................................................
Instruction Format Summary .... ..................................................
Coprocessor ID Field ...........................................................
Effective Address Field ........................................................
Register/Memory Field.........................................................
4-133
4-135
4-137
4-137
4-138
4-138
4-138
4-138
Source Specifier Field
........................................................... 4-138
Destination Register Field...................................................... 4-139
Conditional Predicate Field ...................................................." 4-139
Instruction Format Diagrams ....................................................... 4-141
Section 5
CoprocessorProgramming
Applications Programming..................................... ..................... 5-1
Concurrency ......................................... .............................. 5-1
Concurrent Integer and Floating-Point Computations ............. 5-1
Concurrent Floating-Point Computations ............................. 5-2
Optimization of Code for the MC68882 ..................................... 5-9
Unrolling Loops ............................................................. 5-9
Avoiding Register Conflicts. ............................................. 5-9
Arranging FMOVE Instructions .......................................... 5-9
Performance Improvement Example .................................. 5-10
Systems Programming ............................................................... 5-10
State Frame Sizes
................................................................ 5-10
Exception Handler Code... 5-11
Processing of Special Conditions
................................ ............ 5-12
Interrupts ..................................................................... 5-13
Bus Arbitration .............................................................. 5-13
Context Switching .......................................................... 5-13
Bus Errors .................................................................... 5-14
Exception Processing ...................................................... 5-14
Simultaneous Floating-Point Exception and Task
Switch Interrupt .......................................................... 5-14
Detecting Coprocessor Presence ............................................. 5-15
Section 6
Exception Processing
Coprocessor-Detected Exceptions ................................................. 6-2
Branch/Set on Unordered (BSUN) ........................................... 6-5
Signaling Not-a-Number ........................................................ 6-6
Operand Error ...... ;..: .......................................................... 6-7
Overflow ........................................................................... 6-9
Underflow ......................................................................... 6-11
Divide by Zero .................................................................... 6-14
MC68881/MC68882 USER'S MANUAL FREESCALE
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Paragraph
Number
6.1.7
6.1.8
6.1.9
6.1.10
6.1.11
6.1.12
6.1.13
6.2
6.2.1
6.2,2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.3
6.4
6.4.1
6.4.2
6.4.2.1
6.4.2.2
6.4.2.3
6.4.3
6.4.3.1
6.4.3.2
6.4.3.3
6.4.3.4
6.4.3.5
6.4.4
6.4.5
TABLE OF CONTENTS (Continued)
Page
Title Number
Inexact Result ..................................................................... 6-15
Inexact Result on Decimal Input.............................................. 6-18
Multiple Exceptions ............................................................. 6-19
IEEE Exception and Trap Compatibility..................................... 6-19
Illegal Command Words
....................................................... 6-20
Coprocessor-Detected Protocol Violation .................................. 6-20
Recovery from Exceptions ..................................................... 6-22
Main Processor Detected Exceptions
............................................. 6-24
Trap on Coprocessor Condition Instruction ............................... 6-24
Illegal Instructions ......... :..................................................... 6-24
Main-Processor-Detected Protocol Violations ............................. 6-25
Trace Exceptions ...................................... ........................... 6-25
• Interrupt ............................................................................ 6-26
Address and Bus Errors ................... :.................................... 6-27
Privilege Violations .............................................................. 6-27
Format Error Exceptions ....................................................... 6-28
MC68882 Exception Handlers ...................................................... 6-28
Context Switching ..................................................................... 6-28
FSAVE and FRESTORE Instruction Overviews ............................ 6-29
State Frames ...................................................................... 6-29
Null State Frame............................................................ 6-32
Idle State Frame ............................................................ 6-32
Busy State Frame........................................................... 6-35
FSAVE Protocol................................................................... 6-36
Reset Phase .................................................................. 6-37
Idle Phase .................................................................... 6-38
Initial Phase
.................................................................. 6-38
Middle Phase ................................................................ 6-38
End Phase .................................................................... 6-38
FRESTORE Protocol ............................................................. 6-38
Context Switching Summary .................................................. 6-39
7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
7.2.10
7.2.11
Section 7
Coprocessor Interface
Chip-Select Decode ................................................................... 7-1
Coprocessor Interface Registers ................................................... 7-2
Response CIR ($00) .............................................................. 7-3
Control CIR ($02) ................................................................. 7-4
Save CIR ($04) .................................................................... 7-5
Restore CIR ($06)
................................................................. 7-5
Operation Word CIR ($08) ..................................................... 7-5
Command ClR ($0A)............................................................. 7-5
Condition CIR ($0E) .............................................................. 7-6
Operand CIR ($10)
............................................................... 7-6
Register Select CIR ($14) ....................................................... 7-7
Instruction Address CIR ($18)
................................................. 7-7
Operand Address CIR ($1C) ................................................... 7-8
FREESCALE
viii
MC68881/MC68882 USER'S MANUAL

TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
7.3
7.4
7.4.1
7.4.2
7.4.2.1
7.4.2.2
7.4.2.3
7.4.2.4
7.4.2.5
7.4.2.6
7.4.2.7
7.5
7.5.1
7.5.1.1
7.5.1.2
7.5.1.3
7.5.1.4
7.5.1.5
7.5.2
7.5.3
7.5.3.1
7.5.3.2
7.5.4
7.5.4.1
7.5.4.2
7.514.3
7.5.4.4
7.5.4.5
7.5.4.6
7.5.4.7
!nterprocessor Transfers ....... ,..................................................... 7-8
Coprocessor Instructions ............................................................ 7-8
Instruction Protocol.................................... .......................... 7-9
Response Primitives............................................................. 7-10
Null Primitive ................................................................ 7-11
Evaluate Effective Address and Transfer Data Primitive .......... 7-13
Transfer Single Main Processor Register Primitive ................ 7-14
Transfer Multiple Coprocessor Registers Primitive................. 7-15
Take Pre-lnstruction Exception Primitive ............................. 7-16
Take Mid-Instruction Exception Primitive............................. 7-18
Response Primitive Summary ........................................... 7-19
Instruction Dialogs .................................................................... 7-19
General Instructions ............................................................. 7-21
Register-to-Register (OPCLASS 000)................................... 7-22
External-to-Register (OPCLASS 010) ................................... 7-22
Register-to-External (OPCLASS 011) ................................... 7-24
Move Control Registers (OPCLASS 100 and 101) .................. 7-26
Move Multiple FPn (OPCLASS 110 and 111)......................... 7-27
Conditional Instructions ........................................................ 7-28
Context Switch Instructions ................................................... 7-28
FSAVE ......................................................................... 7-29
FRESTORE............................................... ..................... 7-30
Exception Processing ........................................................... 7-31
Take Pre-lnstruction Exception .......................................... 7-31
Take Mid-Instruction Exception ......................................... 7-32
Mid-Instruction Interrupt .................................................. 7-35
Take BSUN Exception ..................................................... 7-38
F-Line Emulator Exception ............................................... 7-39
Format Exception, FSAVE Instruction ................. ................ 7-39
Format Exception, FRESTORE Instruction .... ........................ 7-40
8.1
8.1.1
8.1.2
8.1.3
8.2
8.3
8.4
8.5
8.5.1
8.5.1.1
8.5.1.2
8.5.1.3
8.5,1.4
Section 8
Instruction Execution Timing
Factors Affecting Execution Times ................................................ 8-1
Instruction Start-Up Phase......... ...........: .................. .............. 8-3
Calculation Phase ............................................... ;............... . 8-3
Round/Store Result Phase ............................... ...................... 8-4
Concurrent Instruction Execution ........................................... . ...... 8-4
Interrupt Latency Times........................................... ................... 8-5
Coprocessor Interface Overhead
................................................... 8-6
Execution Timing Tables ............................................................ 8-10
Timing Tables for Typical Execution
........................................ 8-11
Effective Address Calculations .......................................... 8-12
Arithmetic Operations.. 8-12
MC68882 Concurrent Operations ....................................... 8-13
Move Control Register and FMOVEM Operations .................. 8-17
MC68881/MC68882 USER'S MANUAL FREESCALE
ix

TABLE OF CONTENTS (Continued}
Paragraph Page
Number Title Number
8.5.1.5
8.5.1.6
8.5.2
8.5.2.1
8.5.2.2
8.5.2.3
8.5.2.4
8.5.2.5
8.5.2.6
8.5.2.7
8.5.2.8
8.5.2.9
8.5.2.10
8.6
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
9.11
9.12
9.13
9.14
10.1
10.1.1
10.1.2
10.1.3
10.2
10.3
10.4
10.4.1
10.4.2
10.4.3
10.5
10.6
Conditional Instructions................................................... 8-18
FSAVE and FRESTORE Instructions.................................... 8-18
MC68881 Detail Timing Tables ............................................... 8-19
Instruction Start-Up ........................................................ 8-25
Transfer Operand.............. ............................................. 8-26
Input Operand Conversion............................................... 8-27
Arithmetic Calculation..................................................... 8-27
Output Operand Conversion............................................. 8-33
Rounding and Exception Handling..................................... 8-33
Conditional Termination.................................................. 8-36
Multiple Register Transfer................................................ 8-37
State Frame Transfer ...................................................... 8-38
Exception Processing...................................................... 8-39
Main Processor Instruction Overlap Timing .................................... 8-40
Section 9
Functional Signal Descriptions
Address Bus (A0-A4) ................................................................. 9-1
Data Bus (D0-D31) .................................................................... 9-2
Size (SIZE)............................................................................... 9-2
Address Strobe (AS} .................................................................. 9-3
Chip Select (CS)........................................................................ 9-3
Read/Write (R/W) ...................................................................... 9-3
Data Strobe (DS) 9-3
Data Transfer and Size Acknowledge (DSACK0, DSACK1) .................. 9-3
Reset (RESET) .......................................................................... 9-4
Clock (CLK) .............................................................................. 9-4
Sense Device (SENSE) ............................................................... 9-5
Power (Vcc and GND) ............................................................... 9-5
No Connect (NC)....................................................................... 9-6
Signal Summary....................................................................... 9-6
Section 10
Bus Operation
Basic Transfer Mechanism Overview............................................. 10-1
32-Bit Port Size ................................................................... 10-2
16-Bit Port Size ................................................................... 10-3
8-Bit Port Size..................................................................... 10-4
Reset
Operation ........................................................................ 10-5
Chip Select Timing.................................................................... 10-6
Bus Cycle Functional Descriptions ................................................ 10-7
Synchronous Read Cycles ..................................................... 10-9
Asynchronous Read Cycles.................................................... 10-12
Asynchronous Write Cycles ................................................... 10-13
Inter-Cycle Timing Restrictions..................................................... 10-14
Coprocessor Interface Protocol Restrictions .................................... 10-15
FREESCALE
X
MC68881/MC68882 USER'S MANUAL

TABLE OF CONTENTS (Concluded)
Paragraph Page
Number Title Number
11.1
11.1.1
11.1.2
11.1.3
11.2
11.2.1
11.2.2
11.3
Section 11
Interfacing Methods
FPCP and MPU Interfacing .......................................................... 11-1
32-Bit Data Bus Coprocessor Connection .................................. 11-1
16-Bit Data Bus Coprocessor Connection .................................. 11-2
8-Bit Data Bus Coprocessor Connection.................................... 11-2
Interfacing the FPCP as a Peripheral.............................................. 11-3
16-Bit Data Bus Peripheral Processor Connection ....................... 11-3
8-Bit Data Bus Peripheral Processor Connection ......................... 11-4
Peripheral Processor Operation .................................................... 11-4
12.1
12.2
12.3
12.4
12.5
12.6
Section 12
Electrical Specifications
Maximum Ratings ..................................................................... 12-1
Thermal Characteristics- PGA Package........................................ 12-1
Power Considerations ............ :................................................... 12-1
DC Electrical Characteristics
........................................................ 12-2
AC Electrical Characteristics -- Clock Input ..................................... 12-3
AC Electrical Characteristics =- Read and Write Cycles ...................... 12-4
13.1
13.2
13.3
Section 13
Ordering Information and Mechanical Data
Standard MC68881/MC68882 Order Information .............................. 13-1
Pin Assignments .................... ................................................... 13-2
Package Dimensions
.................................................................. 13-3
Appendix A
Glossary
Appendix B
Abbreviations and Acronyms
Index
MC68881/MC68882 USER'S MANUAL FREESCALE
xi

LIST OF ILLUSTRATIONS
Figure Page
Number Title Number
1-1 MC68881/MC68882 Programming Model...................... ~................. 1-4
1-2 Exception Status/Enable Byte ...................................................... 1-4
1-3 Mode Control Byte .................................................................... 1-5
1-4 Condition Code Byte.................................................................. 1-5
1-5 Quotient Byte........................................................................... 1-5
1-6 Accrued Exception Byte.............................................................. 1-5
1-7 Typical Coprocessor Configuration ............................................... 1-6
1-8 MC68881 Simplified Block Diagram .............................................. 1-7
1-9 MC68882 Simplified Block Diagram ................ :............................. 1-8
1-10 MC68881/MC68882 Data Format Summary..................................... 1-13
2-1 MC68881/MC68882 Programming Model...................... .................. 2-1
2-2 MC68881/MC68882 FPCRException Enable Bye............................... 2-2
2-3 MC68881/MC68882 FPCR Mode Control Byte .................................. 2-3
2-4 MC68881/MC68882 FPSRCondition Code Byte ........................... ..... 2-4
2-5 MC68881/MC68882 FPSR Quotient Byte ......................................... 2-6
2-6 MC68881/MC68882 FPSR Exception Status Byte .............................. 2-6
2-7 MC68881/MC68882 FPSRAccrued Exception Byte ............................ 2-7
3-1 Signed Integer Data Formats....................... ................................ 3-1
3-2 Binary Real Data Formats ........................................................... 3-2
3-3 Format of Normalized Numbers ................................................... 3-4
3-4 Format of De,normalized Numbers ................................................ 3-4
3-5 Format of Zero ......................................................................... 3-5
3-6 Format of Infinity...................................................................... 3-5
3-7 Format of Not-A-Numbers ........... ............................................... 3-6
3-8 Binary Real Data Type Summary.................................................. 3-7
3-9 Packed Decimal Real Data Format ................................................ 3-7
3-10 Intermediate Result Format......................................................... 3-8
3-11 Packed Decimal Real Data Format Detail........................................ 3-13
4-1 Instruction Description Format..................................................... 4-14
4-2 Operation Table Example (FADD Instruction) .................................. 4-15
5-1 MC68881 Concurrency -- FMUL Instruction ......... ........................... 5-2
5-2 MC68881 Concurrency - FMUL Followed by FMUL and FMOVE........... 5-7
5-3 MC68882 Concurrency -- FMUL Followed by FMUL and FMOVE......... 5-8
5-4 Rolled Version of Linpack Loop.................................................... 5-10
5-5 Optimized Linpack Loop ................................... ......... ................. 5-11
5-6 Minimum Exception Handler ....................................................... 5-12
5-7 Idle State Frame Access Example................................................. 5-13
5-8 Simultaneous Task Switch Interrupt and Floating-Point Exception ....... 5-15
5-9 Coprocessor Identification Code................................................... 5-16
MC68881/MC68882 USER'S MANUAL FREESCALE
Xlll

LIST OF ILLUSTRATIONS (Continued)
Figure Page
Number Title Number
6-1
6-2
6-3
6-4
6-5
6-6
6-7
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-12
7-13
7-14
7-15
7-16
7-17
7-18
7-19
7-20
7-21
7-22
7-23
7-24
7-25
7-26
7-27
7-28
7-29
7-30
7-31
7-32
7-33
7-34
EXC and ENABLE Byte Bit Assignments......................................... 6-5
Intermediate Result Format ......................................................... 6-16
Rounding Algorithm ................................................................... 6-17
MC68881 State Frame Formats .................................................... 6-30
MC68882 State Frame Formats .................................................... 6-31
BIU Flag Format ....................................................................... 6-33
Full Context Save/Restore Instruction Sequences ............................. 6-40
MPU Address Bus Encoding for Coprocessor Accesses ..................... 7-1
FPCP Coprocessor Interface Register Map ...................................... 7-2
Control CIR Register .................................................................. 7-4
Operand CIR Data Alignment....................................................... 7-7
Coprocessor Instruction General Format ........................................ 7-9
FPCP Instruction Operation Word ................................................. 7-9
MC68000 Coprocessor Response Primitive General Format ................ 7-10
Null Primitive Format ................................................................. 7-11
Evaluate Effective Address and Transfer Data Primitive Format........... 7-13
Transfer Single Main Processor Register Primitive Format ................. 7-14
Transfer Multiple Coprocessor Registers Primitive Format ................. 7-15
Transfer Multiple Floating-Point Data Register to Stack Example ......... 7-16
Take Pre-lnstruction Exception Primitive Format .............................. 7-17
Pre-lnstruction Exception Stack Frame ........................................... 7-18
Take Mid-Instruction Exception Primitive Format ............................. 7-18
Mid-Instruction Stack Frame ........................................................ 7-19
MC68881 Register-to-Register Instruction Dialog .............................. 7-23
MC68881/MC68882 External-to-Register Instruction Dialog ................. 7-23
MC68882 External-to-Register Instruction Dialog .............................. 7-24
MC68881/MC68882 Register-to-External Instruction Dialog ................. 7-24
MC68882 Register-to-External Instruction Dialog (S,D, and X Formats) 7-26
Move Control Register Instruction Dialog ....................................... 7-26
Move Multiple Floating-Point Data Registers Instruction Dialog.... 7-27
Conditional Instruction Dialog..................................................... 7-28
FSAVE Instruction Dialog ................... ;....................................... 7-29
FRESTORE Instruction Dialog ..................................................... 7-30
Take Pre-lnstruction Exception Dialog -- MC68881 .......................... 7-31
Take Pre-lnstruction Exception Dialog -- MC68882 .......................... 7-33
Take Pre-lnstruction Exception Dialog -- MC68882
with No FSAVE Instruction in the Handler ................................... 7-33
Take Pre-lnstruction Exception Dialog -- MC68882
with No BSET Instruction in the Exception Handler........................ 7-34
Take Mid-Instruction Exception Dialog -- MC68881 .......................... 7-34
Take Mid-Instruction Exception Dialog -- MC68882
General Concurrent Case ......................................................... 7-36
Take Mid-Instruction Exception Dialog -- MC68882
FMOVE Concurrent Case.......................................................... 7-36
Take Mid-Instruction Exception Dialog- MC68882
with No FSAVE Instruction in the Handler ................................... 7-37
FREESCALE
xiv MC68881/MC68882 USER'S MANUAL

LIST OF ILLUSTRATIONS (Concluded)
Figure Page
Number Title Number
7-35 Take Mid-Instruction Exception Dialog -- MC68882
with No BSET Instruction in the Handler ..................................... 7-37
7-36 Mid-Instruction Interrupt Dialog ................................................... 7-38
7-37 Take BSUN Exception Dialog... .................................................... 7-38
7-38 Take F-Line Emulator Exception Dialog .......................................... 7-39
7-39 FSAVE Format Exception Dialog................................................... 7-40
7-40 FRESTORE Format Exception Dialog ............................................. 7-41
8-1 Nonconcurrent Instruction Execution, Interrupts Allowed................... 8-6
8-2 Best-Case Coprocessor Interface Overhead Timing ........................... 8-8
8-3 Worst-Case FPCP Interface Overhead Timing ............ ...................... 8-9
8-4 Instruction Overlap Examples -- FMOVE.X FPm,FPn......................... 8-22
8-5 Instruction Overlap Example -- FMOVES.S (An),FPn......................... 8-23
9-1 MC68881/MC68882 Input/Output Signals
........................................ 9-1
9-2 Sense Device Circuit Example..................... ................................. 9-5
10-1 FPCPData Bus Bit Assignments ................................................... 10-2
10-2 Data Bus Activity vs Port Size and Operand Alignment ..................... 10-2
10-3 FPCPReset Logic Example.......................................................... 10-6
10-4 Example of Early Chip Select Circuits ......................................... ... 10-8
10-5 Example of Late Chip Select Circuit .............................................. 10-9
10-6 Synchronous Read Cycle Timing Diagram ...................................... 10-10
10-7 Asynchronous Read Cycle Timing Diagram .................................... 10-12
10-8 Asynchronous Write Cycle Timing Diagram .................................... 10-13
11-1~ 32-Bit Data Bus Coprocessor Connection
........................................ 11-1
11-2 16-Bit Data Bus Coprocessor Connection......................................... 11-2
11-3 8-Bit Data Bus Coprocessor Connection ......................................... 11-3
11-4 16-Bit Data Bus Peripheral Processor Connection ............................. 11-4
11-5 8-Bit
Data Bus Peripheral Processor Connection .............................. 11-5
12-1 Clock Input Timing Diagram .............. .......................................... 12-3
12-2 Asynchronous Read Cycle Timing Diagram .................................... Foldout 1
12-3 Asynchronous Write Cycle Timing Diagram .................................... Foldout 2
12-4 Synchronous Read Cycle Timing Diagram ...................................... Foldout 3
MC68881/MC68882 USER'S MANUAL FREESCALE
XV

LIST OF TABLES
Table Page
Number Title Number
1-1 Exponent and Mantissa Sizes ...................................................... 1-11
2-! Condition Code versus Result Data Type........................................ 2-5
3-1 Single Precision Binary Real Format.............................................. 3-10
3-2 Double Precision Binary Real Format ............................................ 3-11
3-3 Extended Precision Binary Real Format.......................................... 3-12
3-4 Decimal String Type Definitions................................................... 3-13
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
Data Movement Operations......................................................... 4-2
Dyadic Operation Format............................................................ 4-2
Dyadic Operations..................................................................... 4-3
Monadic Operation Format ......................................................... 4-3
Monadic Operations .................................................................. 4-3
Dual Monadic Operation Format................................................... 4-4
Program Control Operations........................................................ 4-4
Conditional Test Mnemonics ....................................................... 4-4
System Control Operations......................................................... 4-5
Effective Addressing Mode Categories............................... ............ 4-13
General Type Instruction Command Word Fields ............................. 4-126
Register Field Encoding.............................................................. 4-127
Extension Field Encoding for Arithmetic Operations ......................... 4-128
Source Format Field Encoding ..................................................... 4-129
Destination Format Field Encoding ................................................ 4-130
Extension Field Encoding........... ................................................. 4-131
Encoding for Move FPcr Operations............................................ .. 4-132
Encodings for Move Multiple FPn Operations.................................. 4-134
Encodings for the FDBcc, FScc, and FTRAPcc Instuctions................... 4-135
Conditional Predicate Evaluation Responses ................................... 4-136
Effective Address Field Encoding Summary.................................... 4-139
Conditional Predicate Field Encoding Summary............................... 4-140
5-1 Minimum-Concurrency Instructions .............................................. 5-5
5-2 Monadic Instructions ................................................................. 5-5
5-3 Dyadic Operations..................................................................... 5-6
5-4 Partial-Concurrency Instructions................................................... 5-6
5-5 Fully-Concurrent Instructions....................................................... 5-6
5-6 Conditional Instructions.............................................................. 5-7
5-7 FMOVE Instruction Execution Times.............................................. 5-10
5-8 State Frame Sizes ..................................................................... 5-11
MC68881/MC68882 USER'S MANUAL FREESCALE
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LIST OF TABLES (Continued)
Table Page
Number Title Number
6-1 MC68881/MC68882 Exception Vector Assignments........................... 6-4
6-2 Possible Operand Errors ............................................................. 6-8
6-3 Possible Divide-by-Zero Exceptions............................................... 6-14
6-4 BIU Flag Bit Definitions.............................................................. 6-35
6-5 MC68881/MC68882 Responses to Save Command............................ 6-36
6-6 MC68881/MC68882 Format Word Definitions................ ,.................. 6-37
7-1 MPU CPU Space Type Field Encoding ........................................... 7-2
7-2 Coprocessor Interface Register Characteristics................................. 7-3
7-3 Null Primitive Encodings ........... ~................................................ 7-12
7-4 Coprocessor Valid Effective Address Codes .................................... 7-14
7-5 Evaluate Effective Address and Transfer Data Primitive Encoding........ 7-14
7-6 FPCPVector Numbers................................................................ 7-17
7-7 MC68881/MC68882 Primitive Responses ........................................ 7-20
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
8-11
8-12
8-13
8-14
8-15
8-16
8-17
8-18
8-19
8-20
8-21
8-22
8-23
8-24
8-25
Effective Address Calculations..................................................... 8-13
MC68881 Overall Execution Times................................................ 8-14
MC68882 Overall Execution Times................................................ 8-15
Bus Cycle Activity- Arithmetic Operations.................................... 8-16
Timing Calculation Example........................................................ 8-16
Move Control Register and MOVEM Execution Times ....................... 8-17
Conditional Instruction Execution Times ........................................ 8-18
FSAVE and FRESTORE Instruction Execution Times.......................... 8-19
Instruction Start-Up Times .......................................................... 8-25
Null Primitive Time Values.......................................................... 8-26
Operand Transfer Time -- External Operand................................... 8-26
Operand Transfer Time -- Immediate Operand ............................... 8-26
Input Operand Conversion.......................................................... 8-28
Arithmetic Calculation Times -- Dyadic Operations.......................... 8-30
Arithmetic Calculation Times -- Monadic Operations........................ 8-34
Output Operand Conversion........................................................ 8-35
Output Operand Conversion -- Binary Real Formats......................... 8-35
Rounding Operation Time Values ................................................. 8-35
Exception Handling Time Values .................................................. 8-36
Conditional Termination Times Values .......................................... 8-37
Multiple Register Transfer Time Values.......................................... 8-38
State Frame Transfer Time Values................................................ 8-38
Instruction Termination Processing Time Values.............................. 8-38
Exception Processing Time Values................................................ 8-39
Overlap Allowed Times -- Arithmetic Operations............................. 8-40
9-1 Coprocessor Interface Register Selection........................................ 9-2
9-2 System Data Bus Size Configuration ............................................. 9-2
9-3 DSACK Assertions..................................................................... 9-4
9-4 VCC and GND Pin Assignments ................................................... 9-6
9-5 Signal Summary....................................................................... 9-7
FREESCALE
XVIII
MC68881/MC68882 USER'S MANUAL

PREFACE
This manual assumes that the MC68881/MC68882 is connected as a coprocessor
to the MC68020/MC68030 microprocessor. If the MC68881/MC68882 is used in a
system with a main processor other than the MC68020/MC68030, it is expected
that the main processor emulates the M68000 Family coprocessor interface as
required by the MC68881/MC68882.
This manual is divided into two major parts. The first part, sections 2 through 8,
describes the programmer's model of the MC68881/MC68882 and the floating-
point instruction setthat it implements. This part of the manual includes a detailed
description of each instruction and a section on instruction timing that can be
used for program optimization and to predict floating-point arithmetic perform-
ance.
The second part of the manual, sections 9 through 13, describes the hardware
interface of the MC68881/MC68882 to the main processor, and is most pertinent
to system hardware designers. Bus cycle timing diagrams, interface register ad-
dressing, etc., are discussed from the viewpoint of the MC68020/MC68030 hard-
ware conventions. A prior knowledge of the MC68020/MC68030 bus interface,
particularly as it pertains to the M68000 Family coprocessor interface, is quite
helpful in understanding the operation of the MC68881/MC68882 bus interface.
Throughout this manual, M68000 or M68000 Family is used to refer to the family
of devices that support the Freescale68000 Family architecture. A number that is
preceded by MC, such as MC68020, MC68030, MC68881, or MC68882, refers to a
specific part. A reference to MC68881/MC68882 or FPCPapplies to either floating-
point coprocessor, and a reference to MC68020/MC68030 or MPU applies to either
main processor.
The sections and appendices of the manual are:
Section 1. General Description
Section 2. Programming Model
Section 3. Operand Data Formats
Section 4. Instruction Set
Section 5. Coprocessor Programming
Section 6. Exception Processing
Section 7. Coprocessor Interface
Section 8. Instruction Execution Timing
Section 9. Functional Signal Descriptions
Section 10. Bus Operation
Section 11. Interfacing Methods
Section 12. Electrical Specifications
Section 13. Ordering Information and Mechanical Data
Appendix A. Glossary
Appendix B. Abbreviations and Acronyms
MC68881/MC68882 USER'S MANUAL FREESCALE
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