Freescale Semiconductor MPC5565 User manual

© Freescale Semiconductor, Inc., 2012. All rights reserved.
Freescale Semiconductor MPC5565RM
Rev. 1.1, 05/2012
This MPC5565 Reference Manual set consists of the following files:
• MPC5565 Reference Manual Addendum, Rev 1
• MPC5565 Microcontroller Reference Manual, Rev 2
MPC5565 Microcontroller
Reference Manual

© Freescale Semiconductor, Inc., 2009–2012. All rights reserved.
Freescale Semiconductor
Reference Manual Addendum
MPC5565RMAD
Rev. 2, 05/2012
Table of Contents
This errata document describes corrections to the
MPC5565 Preliminary Microcontroller Reference
Manual, order number MPC5565RM. For convenience,
the addenda items are grouped by revision. Please check
our website at
http://www.freescale.com/powerarchitecture for the
latest updates.
The current version available of the MPC5565
Microcontroller Reference Manual is Revision 1.0.
MPC5565 Reference Manual
Addendum
1 Addendum for Revision 1.0. . . . . . . . . . . . . . . . . . 2
2 Revision history. . . . . . . . . . . . . . . . . . . . . . . . . . 15

MPC5565 Reference Manual Addendum, Rev. 2
Addendum for Revision 1.0
Freescale Semiconductor2
1 Addendum for Revision 1.0
Table 1. MPC5565RM Rev 1.0 addendum
Location Description
Section 12.4.2.7/Page 12-42 Change sentence “The bytes indicated as ‘—’ are not driven during that write cycle” to read “The
bytes indicated as ‘—’ are indeterminate and may be driven during that write cycle.”
Table 12-19, “Data Bus
Contents for Write
Cycles”/Page 12-43
Replace table with the one below to correct information about data bus contents for write cycles.
Note that only two columns have changed: under “32-Bit Port Size,” columns “D0:D7” and
“D8:D15.”
Table 9-23, “DMA Request
Summary for eDMA”/Page
9-39
Change one row in the table to correct information about eSCI COMBTX DMA request. Only the
Transmit Data Register Empty and LIN Transmit Data Ready flags drive the DMA request. The
Transmit Complete flag is not used.
Transfer
Size
TSIZ
[0:1]
Address 32-Bit Port Size 16-Bit Port Size1
NOTES:
1Also applies when DBM=1 for 16-bit data bus mode.
A30 A31 D0:D7 D8:D15 D16:D23 D24:D31 D0:D7 D8:D15
Byte 01 0 0 OP0 — — — OP0 —
01 0 1 — OP1 — — — OP1
01 1 0 — — OP2 — OP2 —
01 1 1 — — — OP3 — OP3
16-bit 10 0 0 OP0 OP1 — — OP0 OP1
10 1 0 — — OP2 OP3 OP2 OP3
32-bit 00 0 0 OP0 OP1 OP2 OP3 OP0/
OP22
2This case consists of two 16-bit external transactions, the first writing OP0 and OP1,
the second writing OP2 and OP3.
OP1/OP3
DMA Request Channel Source Description
eSCIA_COMBTX 18 ESCIA.SR[TDRE] ||
ESCIA.SR[TC] ||
ESCIA.SR[TXRDY]
eSCIA combined DMA
request of the Transmit
Data Register Empty
and LIN Transmit Data
Ready DMA requests

Addendum for Revision 1.0
MPC5565 Reference Manual Addendum, Rev. 2
Freescale Semiconductor 3
Table 10-9, “MPC5565
Interrupt Request
Sources”/Page 10-19
Change three rows in the table to correct DSPI_B information. The three interrupt requests were
not assigned to the correct channel numbers.
Figure 5-2, “Master Privilege
Control Registers”/Page 5-5
Change read status for bits 16–31 from zero to reserved.
Table A-1, “Module Base
Addresses”/Page A-1
Correct names of peripheral bridge modules by adding underscore (PBRIDGEA becomes
PBRIDGE_A, PBRIDGEB becomes PBRIDGE_B). Only two rows of the table are changed.
Table 1. MPC5565RM Rev 1.0 addendum (continued)
Location Description
Hardware Vector
Mode Offset
Vector
Number Source Description
0x0850 133 DSPI_BSR[TFFF] DSPI B transfer FIFO fill flag
0x0860 134 DSPI_BSR[TCF] DSPI B transfer complete flag
0x0870 135 DSPI_BSR[RFDF] DSPI B receive FIFO drain flag
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
Reset0 11 1 01110111011 1
Access Field 4
Access Field 5
Access Field 6
Access Field 7
Module Base Address Page
Peripheral Bridge A (PBRIDGE_A) 0xC3F0_0000 Page A-2
Peripheral Bridge B (PBRIDGE_B) 0xFFF0_0000 Page A-31

MPC5565 Reference Manual Addendum, Rev. 2
Addendum for Revision 1.0
Freescale Semiconductor4
Table A-2, “MPC5565
Detailed Register
Map”/Page A-2
Correct names of peripheral bridge A control registers by adding underscore (PBRIDGEA_x
becomes PBRIDGE_A_x).
Table 1. MPC5565RM Rev 1.0 addendum (continued)
Location Description
Register Description Register Name Used
Size Address
Peripheral bridge A master privilege
control register
PBRIDGE_A_MPCR 32-bit Base + 0x0000
Reserved — — Base +
(0x0004-0x001F)
Peripheral bridge A peripheral access
control register 0
PBRIDGE_A_PACR0 32-bit Base + 0x0020
Reserved — — Base +
(0x0024-0x003F)
Peripheral bridge A off-platform
peripheral access control register 0
PBRIDGE_A_OPACR0 32-bit Base + 0x0040
Peripheral bridge A off-platform
peripheral access control register 1
PBRIDGE_A_OPACR1 32-bit Base + 0x0044
Peripheral bridge A off-platform
peripheral access control register 2
PBRIDGE_A_OPACR2 32-bit Base + 0x0048
Reserved — — Base + (0x004C-
0xC3F7_FFFF)

Addendum for Revision 1.0
MPC5565 Reference Manual Addendum, Rev. 2
Freescale Semiconductor 5
Table A-2, “MPC5565
Detailed Register
Map”/Page A-23
Correct names of peripheral bridge B control registers by adding underscore (PBRIDGEB_x
becomes PBRIDGE_B_x).
Table 1. MPC5565RM Rev 1.0 addendum (continued)
Location Description
Register Description Register Name Used
Size Address
Peripheral bridge B master privilege
control register
PBRIDGE_B_MPCR 32-bit Base + 0x0000
Reserved — — Base +
(0x0004-0x001F)
Peripheral bridge B peripheral access
control register 0
PBRIDGE_B_PACR0 32-bit Base + 0x0020
Reserved — — Base +
(0x0024-0x0027)
Peripheral bridge B peripheral access
control register 2
PBRIDGE_B_PACR2 32-bit Base + 0x0028
Reserved — — Base +
(0x002C-0x003F)
Peripheral bridge B off-platform
peripheral access control register 0
PBRIDGE_B_OPACR0 32-bit Base + 0x0040
Peripheral bridge B off-platform
peripheral access control register 1
PBRIDGE_B_OPACR1 32-bit Base + 0x0044
Peripheral bridge B off-platform
peripheral access control register 2
PBRIDGE_B_OPACR2 32-bit Base + 0x0048
Peripheral bridge B off-platform
peripheral access control register 3
PBRIDGE_B_OPACR3 32-bit Base + 0x004C
Reserved — — (Base + 0x0050)-
0xFFF0_3FFF)

MPC5565 Reference Manual Addendum, Rev. 2
Addendum for Revision 1.0
Freescale Semiconductor6
Figure 16-13,” Unified
Channel Block
Diagram”/Page 16-26
Reverse the arrow between the "Programmable Filter" and "Edge Detect".
Table 1. MPC5565RM Rev 1.0 addendum (continued)
Location Description

Addendum for Revision 1.0
MPC5565 Reference Manual Addendum, Rev. 2
Freescale Semiconductor 7
Section13.3/ Page 13-4 Remove cross-reference to Table 13-2. Add the following table and update the cross-reference.
Table 1. MPC5565RM Rev 1.0 addendum (continued)
Location Description

MPC5565 Reference Manual Addendum, Rev. 2
Addendum for Revision 1.0
Freescale Semiconductor8
Table 16-9/ Page 16-15 Bit 7—DMA: Replace the table that shows the eMIOS channels that don’t support DMA with the
following table.
Section 9.3.1, “eDMA
Microarchitecture”/ Page
9-29
In the Memory controller sub-bullet, delete the line "The hooks to a BIST controller for the local
TCD memory are included in this module".
Table 1. MPC5565RM Rev 1.0 addendum (continued)
Location Description
eMIOS Channel DMA = 0 DMA = 1
0Interrupt DMA request
1Interrupt DMA request
2Interrupt DMA request
3Interrupt DMA request
4Interrupt DMA request
5Interrupt Reserved
6Interrupt Reserved
7Interrupt Reserved
8Interrupt DMA request
9Interrupt DMA request
10 Interrupt Reserved
11 Interrupt Reserved
12 Interrupt Reserved
13 Interrupt Reserved
14 Interrupt Reserved
15 Interrupt Reserved
16 Interrupt Reserved
17 Interrupt Reserved
18 Interrupt Reserved
19 Interrupt Reserved
20 Interrupt Reserved
21 Interrupt Reserved
22 Interrupt Reserved
23 Interrupt Reserved

Addendum for Revision 1.0
MPC5565 Reference Manual Addendum, Rev. 2
Freescale Semiconductor 9
Section 9.2.2.13: eDMA
Interrupt Request Register
(EDMA_IRQRL)/ Page 9-17
In the second paragraph, remove the last line "without the need to perform a read-modify-write
sequence to the EDMA_IRQRL".
Section 8.3: Initialization and
Application
Information/Page 8-14
Replace the whole section with the following information:
The Error Correction Code (ECC) is used to verify the contents of the internal SRAM and flash
memories. This is done by generating ECC check bits. Typically ECC check bits are calculated
on writes and then used on reads to detect and correct errors.
• SRAM—Eight ECC check bits for each 64-bit SRAM data doubleword.
• Flash—Eight ECC check bits for each 64-bit flash data doubleword.
After Power on Reset (POR), the contents of internal SRAM is random and the corresponding
ECC check bits are unknown. To prevent generating ECC errors during reads, an initialization
routine must perform 64 bit writes to all SRAM locations. Because the flash module is
non-volatile, the ECC check bits are calculated and stored when the flash is programmed.
Transparent to the application, the ECC uses the check bits to automatically correct single-bit
memory errors. Multi-bit memory errors are not correctable. If the ECC detects a multi-bit error,
an exception is generated. The type of exception generated by a multi-bit error depends on the
settings of the EE and ME in the Machine State Register (MSR), as shown in the following table.
When error reporting is enabled, as long as its priority is 0, an interrupt request is generated to
the interrupt controller (INTC) even though the INTC request is not serviced.
A non-correctable data ECC error executes one of the following actions, regardless of whether
non-correctable reporting is enabled:
Table 1. MPC5565RM Rev 1.0 addendum (continued)
Location Description
MSR[EE] and MSR[ME] Bit Settings
Field Description
EE External interrupt enable.
0 External input interrupts disabled.
1 External interrupts enabled.
ME Machine check enable.
0 Machine check interrupts disabled. Enters machine check.
1 Machine interrupts enabled.
Non-correctable Data ECC States
MSR[EE] MSR[ME] Access Type Result
0 0 Instruction or
data
Enters checkstop state. A reset is
required to resume processing.
0 1 Instruction or
data
Machine check interrupt (IVOR1).
1 X Data Data storage interrupt (IVOR2).
External interrupt must be enabled.
Machine check can be enabled or
disabled.
1 X Instruction Instruction storage interrupt
(IVOR3).

MPC5565 Reference Manual Addendum, Rev. 2
Addendum for Revision 1.0
Freescale Semiconductor10
When the device is in the checkstop state, processing is suspended and cannot resume without
a reset. When a debug request is presented to the core while it is in the checkstop state, the core
temporarily exits the checkstop state and enters debug mode. When debug mode exits, the core
re-enters the checkstop state.
If the external interrupt bit in the MSR is enabled, data or instruction stage interrupts are reported
when the ECC errors are a result of CPU accesses, regardless of whether non-correctable
reporting is enabled.
ECC errors generated by other masters (eDMA, etc.) do not generate data or instruction storage
exceptions, and the ECSM is used to report these errors. You must initialize the ECSM to enable
non-correctable reporting with interrupt generation to detect and report ECC interrupts from the
ECSM.
Error reporting details can be independently enabled for flash memory and SRAM. To enable
non-correctable error reporting and save the error details for:
• SRAM—set the ERNCR bit in the ECSM Error Configuration Register (ECSM_ECR).
• Flash—set the EFNCR bit in ECSM_ECR.
When these bits are set and a non-correctable ECC error occurs, error information is recorded
in other ECSM registers and an interrupt request is generated on vector 9 of the interrupt
controller (INTC).
• CPU data access error—Generates data storage exception (IVOR2).
• CPU instruction access error—Generates instruction storage exception (IVOR3).
• Vector 9 of INTC enabled—Generates an external exception (IVOR4)
Section 11.4.3.3, "FM
Calibration Routine"/ Page
11-29
Correct the equation at the end of the third paragraph: change value of M from 640 to 480.
Table 6-135, “SIU_DISR
Field Descriptions”/ Page
6-108
• Bit 14-15–TRIGSELB: Correct the input select description as follows:
00: Replace the term “Invalid value” with “No Trigger”
01: Replace the term “Invalid value” with “No Trigger”
• Bit 22-23–TRIGSELC: Correct the input select description as follows
00: Replace the term “Invalid value” with “No Trigger”
01: Replace the term “Invalid value” with “No Trigger”
• Bit 30-31–TRIGSELD: Correct the input select description as follows
00: Replace the term “Invalid value” with “No Trigger”
01: Replace the term “Invalid value” with “No Trigger”
Table 1. MPC5565RM Rev 1.0 addendum (continued)
Location Description

Addendum for Revision 1.0
MPC5565 Reference Manual Addendum, Rev. 2
Freescale Semiconductor 11
Figure 11-9, “Synthesizer
Status Register
(FMPLL_SYNSR)”/Page
11-16
Correct the figure to reflect bits 23:28 and bits 30:31 as read-only.
Section 10.5.5.2, “Ensuring
Coherency”/ Page 10-33
Add the following sentence before GetResource source code:
“Processor recognition of interrupts must be enabled before executing the GetResource code
sequence.”
Insert a blank line between the GetResource and ReleaseResource code sequences:
GetResource:
raise PRI
mbar
isync
ReleaseResource:
mbar
lower PRI
Section 10.3.1.3, “INTC
Interrupt Acknowledge
Register
(INTC_IACKR)”/Page 10-11
Remove the first paragraph from the “Note”:
“The INTC_IACKR must not be read speculatively while in software vector mode. Therefore, for
future compatibility, the TLB entry covering the INTC_IACKR must be configured to be guarded.”
Table 10-3. INTC Memory
Map/Page 10-8
Add the following note at the end of this table:
Note:
To ensure compatibility with all PowerPC processors, the TLB entry covering the INTC memory
map must be configured as guarded, both in software and hardware vector modes.
• In software vector mode, the INTC_IACKR must not be read speculatively.
• In hardware vector mode, guarded writes to the INTC_CPR or INTC_EOIR complete before
the interrupt acknowledge signal from the processor asserts.
Table 1. MPC5565RM Rev 1.0 addendum (continued)
Location Description
Addre
ss:
Base + 0x0004 Access: User R/W
012345 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 00 0 000 0 0000
W
Reset0000000 0 000 0 0000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
000000LOLFLOC
MO
DE
PLL
SEL
PLL
REF
LOC
KS
LOC
K
LOC
F
CAL
DO
NE
CAL
PAS
S
Ww1c w1c
Reset000000 0 0 —
1—1—1—1—2000
1Reset state determined during reset configuration.
2Reset state determined during reset.
Note: “w1c” signifies that this bit is cleared by writing a 1 to it.
Synthesizer Status Register (FMPLL_SYNSR)

MPC5565 Reference Manual Addendum, Rev. 2
Addendum for Revision 1.0
Freescale Semiconductor12
Table 10-9. MPC5565
Interrupt Request
Sources/Page 10-23
Note:
Update the note at the end of this table as follows:
The INTC has no spurious vector support. Therefore, if an asserted peripheral or software
settable interrupt request (whose PRI value in INTC_PSRn is higher than the PRI value in
INTC_CPR) negates before the interrupt request to the processor for that peripheral or software
settable interrupt request is acknowledged, the interrupt request to the processor still can assert
or remain asserted for that peripheral or software settable interrupt request. If the interrupt
request to the processor does assert or does remain asserted:
• The interrupt vector will correspond to that peripheral or software settable interrupt request.
• The PRI value in the INTC_CPR will be updated with the corresponding PRI value in
INTC_PSRn.
Furthermore, clearing the peripheral interrupt request's enable bit in the peripheral or,
alternatively, setting its mask bit has the same consequences as clearing its flag bit.Setting its
enable bit or clearing its mask bit while its flag bit is asserted has the same effect on the INTC
as an interrupt event setting the flag bit.
Section 10.4.2.1.4, “Priority
Comparator Submodule”/
Page 10-25
Add the following paragraph to this section: One consequence of the priority comparator design
is that once a higher priority interrupt is captured, it must be acknowledged by the CPU before a
subsequent interrupt request of even higher priority can be captured. For example, if the CPU is
executing a priority level 1 interrupt, and a priority level 2 interrupt request is captured by the
INTC, followed shortly by a priority level 3 interrupt request to the INTC, the level 2 interrupt must
be acknowledged by the CPU before a new level 3 interrupt will be generated.
Section 10.5.5.2, “Ensuring
Coherency”/ Page 10-32
Move the content of this section under a new heading Section 10.5.5.2.1, “Interrupt with Blocked
Priority”.
Add the following paragraph to this section:
Section 10.5.5.2.2: Raised Priority Preserved
Before the instruction after the GetResource system service executes, all pending transactions
have completed. These pending transactions can include an ISR for a peripheral or software
settable interrupt request whose priority was equal to or lower than the raised priority. Also,
during the epilog of the interrupt exception handler for this preempting ISR, the raised priority
has been restored from the LIFO to PRI in INTC_CPR. The shared coherent data block now can
be accessed coherently. Following figure shows the timing diagram for this scenario, and the
table explains the events. The example is for software vector mode, but except for the method of
retrieving the vector and acknowledging the interrupt request to the processor, hardware vector
mode is identical.
Table 1. MPC5565RM Rev 1.0 addendum (continued)
Location Description

Addendum for Revision 1.0
MPC5565 Reference Manual Addendum, Rev. 2
Freescale Semiconductor 13
.
Raised Priority Preserved Timing Diagram
Table 1. MPC5565RM Rev 1.0 addendum (continued)
Location Description
Last In / First Out
Entry in LIFO
Write
INTC_CPR
Clock
Interrupt Request
to Processor
Hardware Vector
Enable
Interrupt
Acknowledge
Interrupt Vector
Read
INTC_IACKR
Write
INTC_EOIR
INTVEC in
INTC_IACKR
PRI in
INTC_CPR
Peripheral Interrupt
Request 100
0
108
1
208
23
Peripheral Interrupt
Request 200
030
3
A
B
C
D
E
F
G
H
I
Raised Priority Preserved Events
Event Description
A Peripheral interrupt request 200 asserts during execution of ISR108 running at
priority 1.
B Interrupt request to processor asserts. INTVEC in INTC_IACKR updates with vector
for that peripheral interrupt request.
C ISR108 writes to INTC_CPR to raise priority to 3 before accessing shared coherent
data block.
D PRI in INTC_CPR now at 3, reflecting the write. This write, just before accessing
data block, is the last instruction the processor executes before being interrupted.
E Interrupt exception handler prolog acknowledges interrupt by reading INTC_IACKR.
F PRI of 3 pushed onto LIFO. PRI in INTC_CPR updates to 2, the priority of ISR208.
G ISR208 clears its flag bit, deasserting its peripheral interrupt request.
H Interrupt exception handler epilog writes to INTC_EOIR.
I LIFO pops 3, restoring the raised priority onto PRI in INTC_CPR. Next value to pop
from LIFO is the priority from before peripheral interrupt request 100 interrupted.
ISR108 now can access data block coherently after interrupt exception handler
executes rfi instruction.

MPC5565 Reference Manual Addendum, Rev. 2
Addendum for Revision 1.0
Freescale Semiconductor14
Section 6.3.1.118 “Pad
Configuration Register 218
(SIU_PCR218)”
• Change PA field from two bits to one bit
• Figure 6-119: Change note 2 to “... set the PA field to 0b0.”
• Table 6-119. PCR218 “PA Field Definition” change as shown below:
0b0 FCK
0b1 AN[15]
Section 11.3.1.1
Synthesizer Control Register
(FMPLL_SYNCR)
Changed the last note in PREDIV field description from
“To use the 8-20 MHz OSC, the PLL predivider must be configured for divide-by-two operation
by tying PLLCFG[2] low (set PREDIV to 0b000).” to
“When using an 8 to 20 MHz reference clock (crystal or external clock), PLLCFG[2] should be
set low for devices that have a PLLCFG[2] pin. This sets the default predivider (PREDIV) to
0b000. To use a crystal or external reference greater than 20 MHz (up to 40 MHz), the PLL
predivider must be configured for divide-by-2 operation by setting PLLCFG[2] high. This sets the
default predivider (PREDIV) to 0b001. After reset, PREDIV must not be configured to a value
less than divide-by-2 (with a 40 MHz crystal/reference).”
Table 1. MPC5565RM Rev 1.0 addendum (continued)
Location Description

Revision history
MPC5565 Reference Manual Addendum, Rev. 2
Freescale Semiconductor 15
2 Revision history
Table 2 provides a revision history for this document.
Table 2. Revision history
Revision Substantive changes Date of release
1.0 • Initial release. Corrected errors in chapter 12, “External Bus Interface (EBI).” 10/2009
2.0 • Corrected error in chapter 9, “Enhanced Direct Memory Access (eDMA).”
• Corrected errors in chapter 10, “Interrupt Controller (INTC).”
• Corrected errors in chapter 5, “Peripheral Bridge (PBRIDGE A and PBRIDGE B).”
• Corrected peripheral bridge name errors in appendix A, “MPC5565 Register Map.”
• Corrected unified channel block diagram in chapter 16, “Enhanced Modular
Input/Output Subsystem (eMIOS).”
• Corrected the table shown in EMIOS_CCRn: DMA bit description.
• Clarified the description in Section 9.4.1, “eDMA Microarchitecture”.
• Clarified the description in Section 9.3.1.13, “eDMA Interrupt Request Registers
(EDMA_IRQRL).
• Corrected the ECSM initialization information in Section 8.3: Initialization and
Application Information.
• Clarified the code sequence in Section 10.5.5.2: Ensuring Coherency.
• Clarified note in the INTC Interrupt Acknowledge Register .
• Added a note in the INTC Memory Map table.
• Clarified note at the end of the MPC5565 Interrupt Request Sources table.
• Added a paragraph to the Section 10.4.2.1.4, “Priority Comparator Submodule”.
• Updated Section 10.5.5.2, “Ensuring Coherency”.
• Corrected table “PCR218 PA Field Definition” and figure “AN[15]_FCK Pad
Configuration Register (SIU_PCR218)” and update note 2.
• Updated the last note in PREDIV field description of Synthesizer Control Register
(FMPLL_SYNCR).
04/2012

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MPC5565RMAD
Rev. 2
05/2012

MPC5565 Microcontroller Reference
Manual
Devices Supported:
MPC5565
MPC5565 RM
Rev. 1.0
09/2007

Information in this document is provided solely to enable system and
software implementers to use Freescale Semiconductor products. There are
no express or implied copyright licenses granted hereunder to design or
fabricate any integrated circuits or integrated circuits based on the
information in this document.
Freescale Semiconductor reserves the right to make changes without further
notice to any products herein. Freescale Semiconductor makes no warranty,
representation or guarantee regarding the suitability of its products for any
particular purpose, nor does Freescale Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or
incidental damages. “Typical” parameters that may be provided in Freescale
Semiconductor data sheets and/or specifications can and do vary in different
applications and actual performance may vary over time. All operating
parameters, including “Typicals”, must be validated for each customer
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MPC5565 RM
Rev. 1.0
09/2007
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MPC5565 Reference Manual, Rev. 1.0
Freescale Semiconductor 1
Chapter 1
Introduction
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.3 MPC5500 Family Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.4 Detailed Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.4.1 e200z6 Core Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
1.4.2 System Bus Crossbar Switch (XBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.4.3 Enhanced Direct Memory Access (eDMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.4.4 Interrupt Controller (INTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
1.4.5 Frequency Modulated Phase-Locking Loop (FMPLL) . . . . . . . . . . . . . . . . . . . . . . 1-13
1.4.6 External Bus Interface (EBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
1.4.7 Calibration Bus Interface (CBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
1.4.8 System Integration Unit (SIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
1.4.9 Error Correction Status Module (ECSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
1.4.10 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
1.4.11 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
1.4.12 Static RAM (SRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
1.4.13 Boot Assist Module (BAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
1.4.14 Enhanced Management Input/Output System (eMIOS) . . . . . . . . . . . . . . . . . . . . . . 1-15
1.4.15 Enhanced Time Processing Unit (eTPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
1.4.16 Enhanced Queued A/D Converter (eQADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
1.4.17 Deserial/Serial Peripheral Interface (DSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
1.4.18 Enhanced Serial Communications Interface (eSCI) . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
1.4.19 Flexible Controller Area Network (FlexCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
1.4.20 Nexus Development Interface (NDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
1.4.21 JTAG Controller (JTAGC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
1.5 MPC5500 Family Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
1.6 Multi-Master Operation Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
1.7 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
Chapter 2
Signal Description
2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.2 External Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.3 Detailed Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.3.1 Reset and Configuration Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.3.2 External Bus Interface (EBI) Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
2.3.3 Nexus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
2.3.4 JTAG Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
2.3.5 Controller Area Network (FlexCAN) Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2.3.6 Serial Communication Interface (eSCI) Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
2.3.7 Deserial/Serial Peripheral Interface (DSPI) Signals . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
2.3.8 Enhanced Queued A/D Controller (eQADC) Signals . . . . . . . . . . . . . . . . . . . . . . . 2-29