Freescale Semiconductor MPC5565 User manual

© Freescale Semiconductor, Inc., 2012. All rights reserved.
Freescale Semiconductor MPC5565RM
Rev. 1.1, 05/2012
This MPC5565 Reference Manual set consists of the following files:
• MPC5565 Reference Manual Addendum, Rev 1
• MPC5565 Microcontroller Reference Manual, Rev 2
MPC5565 Microcontroller
Reference Manual

© Freescale Semiconductor, Inc., 2009–2012. All rights reserved.
Freescale Semiconductor
Reference Manual Addendum
MPC5565RMAD
Rev. 2, 05/2012
Table of Contents
This errata document describes corrections to the
MPC5565 Preliminary Microcontroller Reference
Manual, order number MPC5565RM. For convenience,
the addenda items are grouped by revision. Please check
our website at
http://www.freescale.com/powerarchitecture for the
latest updates.
The current version available of the MPC5565
Microcontroller Reference Manual is Revision 1.0.
MPC5565 Reference Manual
Addendum
1 Addendum for Revision 1.0. . . . . . . . . . . . . . . . . . 2
2 Revision history. . . . . . . . . . . . . . . . . . . . . . . . . . 15

MPC5565 Reference Manual Addendum, Rev. 2
Addendum for Revision 1.0
Freescale Semiconductor2
1 Addendum for Revision 1.0
Table 1. MPC5565RM Rev 1.0 addendum
Location Description
Section 12.4.2.7/Page 12-42 Change sentence “The bytes indicated as ‘—’ are not driven during that write cycle” to read “The
bytes indicated as ‘—’ are indeterminate and may be driven during that write cycle.”
Table 12-19, “Data Bus
Contents for Write
Cycles”/Page 12-43
Replace table with the one below to correct information about data bus contents for write cycles.
Note that only two columns have changed: under “32-Bit Port Size,” columns “D0:D7” and
“D8:D15.”
Table 9-23, “DMA Request
Summary for eDMA”/Page
9-39
Change one row in the table to correct information about eSCI COMBTX DMA request. Only the
Transmit Data Register Empty and LIN Transmit Data Ready flags drive the DMA request. The
Transmit Complete flag is not used.
Transfer
Size
TSIZ
[0:1]
Address 32-Bit Port Size 16-Bit Port Size1
NOTES:
1Also applies when DBM=1 for 16-bit data bus mode.
A30 A31 D0:D7 D8:D15 D16:D23 D24:D31 D0:D7 D8:D15
Byte 01 0 0 OP0 — — — OP0 —
01 0 1 — OP1 — — — OP1
01 1 0 — — OP2 — OP2 —
01 1 1 — — — OP3 — OP3
16-bit 10 0 0 OP0 OP1 — — OP0 OP1
10 1 0 — — OP2 OP3 OP2 OP3
32-bit 00 0 0 OP0 OP1 OP2 OP3 OP0/
OP22
2This case consists of two 16-bit external transactions, the first writing OP0 and OP1,
the second writing OP2 and OP3.
OP1/OP3
DMA Request Channel Source Description
eSCIA_COMBTX 18 ESCIA.SR[TDRE] ||
ESCIA.SR[TC] ||
ESCIA.SR[TXRDY]
eSCIA combined DMA
request of the Transmit
Data Register Empty
and LIN Transmit Data
Ready DMA requests

Addendum for Revision 1.0
MPC5565 Reference Manual Addendum, Rev. 2
Freescale Semiconductor 3
Table 10-9, “MPC5565
Interrupt Request
Sources”/Page 10-19
Change three rows in the table to correct DSPI_B information. The three interrupt requests were
not assigned to the correct channel numbers.
Figure 5-2, “Master Privilege
Control Registers”/Page 5-5
Change read status for bits 16–31 from zero to reserved.
Table A-1, “Module Base
Addresses”/Page A-1
Correct names of peripheral bridge modules by adding underscore (PBRIDGEA becomes
PBRIDGE_A, PBRIDGEB becomes PBRIDGE_B). Only two rows of the table are changed.
Table 1. MPC5565RM Rev 1.0 addendum (continued)
Location Description
Hardware Vector
Mode Offset
Vector
Number Source Description
0x0850 133 DSPI_BSR[TFFF] DSPI B transfer FIFO fill flag
0x0860 134 DSPI_BSR[TCF] DSPI B transfer complete flag
0x0870 135 DSPI_BSR[RFDF] DSPI B receive FIFO drain flag
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
W
Reset0 11 1 01110111011 1
Access Field 4
Access Field 5
Access Field 6
Access Field 7
Module Base Address Page
Peripheral Bridge A (PBRIDGE_A) 0xC3F0_0000 Page A-2
Peripheral Bridge B (PBRIDGE_B) 0xFFF0_0000 Page A-31

MPC5565 Reference Manual Addendum, Rev. 2
Addendum for Revision 1.0
Freescale Semiconductor4
Table A-2, “MPC5565
Detailed Register
Map”/Page A-2
Correct names of peripheral bridge A control registers by adding underscore (PBRIDGEA_x
becomes PBRIDGE_A_x).
Table 1. MPC5565RM Rev 1.0 addendum (continued)
Location Description
Register Description Register Name Used
Size Address
Peripheral bridge A master privilege
control register
PBRIDGE_A_MPCR 32-bit Base + 0x0000
Reserved — — Base +
(0x0004-0x001F)
Peripheral bridge A peripheral access
control register 0
PBRIDGE_A_PACR0 32-bit Base + 0x0020
Reserved — — Base +
(0x0024-0x003F)
Peripheral bridge A off-platform
peripheral access control register 0
PBRIDGE_A_OPACR0 32-bit Base + 0x0040
Peripheral bridge A off-platform
peripheral access control register 1
PBRIDGE_A_OPACR1 32-bit Base + 0x0044
Peripheral bridge A off-platform
peripheral access control register 2
PBRIDGE_A_OPACR2 32-bit Base + 0x0048
Reserved — — Base + (0x004C-
0xC3F7_FFFF)

Addendum for Revision 1.0
MPC5565 Reference Manual Addendum, Rev. 2
Freescale Semiconductor 5
Table A-2, “MPC5565
Detailed Register
Map”/Page A-23
Correct names of peripheral bridge B control registers by adding underscore (PBRIDGEB_x
becomes PBRIDGE_B_x).
Table 1. MPC5565RM Rev 1.0 addendum (continued)
Location Description
Register Description Register Name Used
Size Address
Peripheral bridge B master privilege
control register
PBRIDGE_B_MPCR 32-bit Base + 0x0000
Reserved — — Base +
(0x0004-0x001F)
Peripheral bridge B peripheral access
control register 0
PBRIDGE_B_PACR0 32-bit Base + 0x0020
Reserved — — Base +
(0x0024-0x0027)
Peripheral bridge B peripheral access
control register 2
PBRIDGE_B_PACR2 32-bit Base + 0x0028
Reserved — — Base +
(0x002C-0x003F)
Peripheral bridge B off-platform
peripheral access control register 0
PBRIDGE_B_OPACR0 32-bit Base + 0x0040
Peripheral bridge B off-platform
peripheral access control register 1
PBRIDGE_B_OPACR1 32-bit Base + 0x0044
Peripheral bridge B off-platform
peripheral access control register 2
PBRIDGE_B_OPACR2 32-bit Base + 0x0048
Peripheral bridge B off-platform
peripheral access control register 3
PBRIDGE_B_OPACR3 32-bit Base + 0x004C
Reserved — — (Base + 0x0050)-
0xFFF0_3FFF)

MPC5565 Reference Manual Addendum, Rev. 2
Addendum for Revision 1.0
Freescale Semiconductor6
Figure 16-13,” Unified
Channel Block
Diagram”/Page 16-26
Reverse the arrow between the "Programmable Filter" and "Edge Detect".
Table 1. MPC5565RM Rev 1.0 addendum (continued)
Location Description

Addendum for Revision 1.0
MPC5565 Reference Manual Addendum, Rev. 2
Freescale Semiconductor 7
Section13.3/ Page 13-4 Remove cross-reference to Table 13-2. Add the following table and update the cross-reference.
Table 1. MPC5565RM Rev 1.0 addendum (continued)
Location Description

MPC5565 Reference Manual Addendum, Rev. 2
Addendum for Revision 1.0
Freescale Semiconductor8
Table 16-9/ Page 16-15 Bit 7—DMA: Replace the table that shows the eMIOS channels that don’t support DMA with the
following table.
Section 9.3.1, “eDMA
Microarchitecture”/ Page
9-29
In the Memory controller sub-bullet, delete the line "The hooks to a BIST controller for the local
TCD memory are included in this module".
Table 1. MPC5565RM Rev 1.0 addendum (continued)
Location Description
eMIOS Channel DMA = 0 DMA = 1
0Interrupt DMA request
1Interrupt DMA request
2Interrupt DMA request
3Interrupt DMA request
4Interrupt DMA request
5Interrupt Reserved
6Interrupt Reserved
7Interrupt Reserved
8Interrupt DMA request
9Interrupt DMA request
10 Interrupt Reserved
11 Interrupt Reserved
12 Interrupt Reserved
13 Interrupt Reserved
14 Interrupt Reserved
15 Interrupt Reserved
16 Interrupt Reserved
17 Interrupt Reserved
18 Interrupt Reserved
19 Interrupt Reserved
20 Interrupt Reserved
21 Interrupt Reserved
22 Interrupt Reserved
23 Interrupt Reserved

Addendum for Revision 1.0
MPC5565 Reference Manual Addendum, Rev. 2
Freescale Semiconductor 9
Section 9.2.2.13: eDMA
Interrupt Request Register
(EDMA_IRQRL)/ Page 9-17
In the second paragraph, remove the last line "without the need to perform a read-modify-write
sequence to the EDMA_IRQRL".
Section 8.3: Initialization and
Application
Information/Page 8-14
Replace the whole section with the following information:
The Error Correction Code (ECC) is used to verify the contents of the internal SRAM and flash
memories. This is done by generating ECC check bits. Typically ECC check bits are calculated
on writes and then used on reads to detect and correct errors.
• SRAM—Eight ECC check bits for each 64-bit SRAM data doubleword.
• Flash—Eight ECC check bits for each 64-bit flash data doubleword.
After Power on Reset (POR), the contents of internal SRAM is random and the corresponding
ECC check bits are unknown. To prevent generating ECC errors during reads, an initialization
routine must perform 64 bit writes to all SRAM locations. Because the flash module is
non-volatile, the ECC check bits are calculated and stored when the flash is programmed.
Transparent to the application, the ECC uses the check bits to automatically correct single-bit
memory errors. Multi-bit memory errors are not correctable. If the ECC detects a multi-bit error,
an exception is generated. The type of exception generated by a multi-bit error depends on the
settings of the EE and ME in the Machine State Register (MSR), as shown in the following table.
When error reporting is enabled, as long as its priority is 0, an interrupt request is generated to
the interrupt controller (INTC) even though the INTC request is not serviced.
A non-correctable data ECC error executes one of the following actions, regardless of whether
non-correctable reporting is enabled:
Table 1. MPC5565RM Rev 1.0 addendum (continued)
Location Description
MSR[EE] and MSR[ME] Bit Settings
Field Description
EE External interrupt enable.
0 External input interrupts disabled.
1 External interrupts enabled.
ME Machine check enable.
0 Machine check interrupts disabled. Enters machine check.
1 Machine interrupts enabled.
Non-correctable Data ECC States
MSR[EE] MSR[ME] Access Type Result
0 0 Instruction or
data
Enters checkstop state. A reset is
required to resume processing.
0 1 Instruction or
data
Machine check interrupt (IVOR1).
1 X Data Data storage interrupt (IVOR2).
External interrupt must be enabled.
Machine check can be enabled or
disabled.
1 X Instruction Instruction storage interrupt
(IVOR3).