Fujitsu MB15E07SL User manual

DS04-21358-4E
FUJITSU SEMICONDUCTOR
DATA SHEET
ASSP
Single Serial Input
PLL Frequency Synthesizer
On-chip 2.5 GHz Prescaler
MB15E07SL
■
■■
■DESCRIPTION
TheFujitsuMB15E07SLisaserialinputPhaseLockedLoop(PLL)frequencysynthesizerwitha2.5GHzprescaler.
The 2.5 GHz prescaler has a dual modulus division ratio of 32/33 or 64/65 enabling pulse swallowing operation.
The supply voltage range is between 2.4 V and 3.6 V. The MB15E07SL uses the latest BiCMOS process, as a
resultthesupplycurrentistypically3.5mAat2.7V.Arefinedchargepumpsupplieswell-balancedoutput currents
of 1.5 mA and 6 mA. The charge pump current is selectable by serial data.
MB15E07SL is ideally suited for wireless mobile communications, such as GSM (Global System for Mobile
Communications) and PCS.
■
■■
■FEATURES
• High frequency operation: 2.5 GHz Max
• Low power supply voltage: VCC = 2.4 to 3.6 V
• Ultra Low power supply current: ICC = 3.5 mA Typ (VCC = Vp = 2.7 V, Ta = +25°C, in locking state)
ICC = 4.0 mA Typ (VCC = Vp = 3.0 V, Ta = +25°C, in locking state)
• Direct power saving function: Power supply current in power saving mode
Typ 0.1 µA (VCC = Vp = 3.0 V, Ta = +25°C), Max 10 µA (VCC = Vp = 3.0 V)
(Continued)
■
■■
■PACKAGES 16-pin plastic SSOP
(FPT-16P-M05)
16-pad plastic BCC
(LCC-16P-M06)

MB15E07SL
2
(Continued)
• Dual modulus prescaler: 32/33 or 64/65
• Serial input 14-bit programmable reference divider: R = 3 to 16,383
• Serial input programmable divider consisting of:
- Binary 7-bit swallow counter: 0 to 127
- Binary 11-bit programmable counter: 3 to 2,047
• Software selectable charge pump current
• On-chip phase control for phase comparator
• Operating temperature: Ta = –40 to +85°C
• Pin compatible with MB15E07, MB15E07L
■PIN ASSIGNMENTS
OSCIN
OSCOUT
VP
VCC
DO
GND
Xfin
fin
φR
φP
LD/fout
ZC
PS
LE
Data
Clock
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
OSCOUT
VP
VCC
DO
GND
Xfin
φP
LD/fout
ZC
PS
LE
Data
OSCIN φR
fin Clock
1
2
3
4
5
678 9
10
11
12
13
141516
(FPT-16P-M05) (LCC-16P-M06)
16-pin SSOP 16-pad BCC
Top view Top view

MB15E07SL
3
■PIN DESCRIPTIONS
Pin no. Pin
name I/O Descriptions
SSOP BCC
116OSC
IN I Programmable reference divider input. Connection to a TCXO.
21OSC
OUT O Oscillator output.
32V
P– Power supply voltage input for the charge pump.
43VCC – Power supply voltage input.
54D
OOCharge pump output.
Phase of the charge pump can be selected via programming of the FC bit.
6 5 GND – Ground.
7 6 Xfin I Prescaler complementary input, which should be grounded via a capacitor.
87finI
Prescaler input.
Connection to an external VCO should be done via AC coupling.
98ClockI
Clock input for the 19-bit shift register.
Data is shifted into the shift register on the rising edge of the clock.
(Open is prohibited.)
10 9 Data I Serial data input using binary code.
The last bit of the data is a control bit. (Open is prohibited.)
11 10 LE I Load enable signal input. (Open is prohibited.) When LE is set high, the data in the shift register is transferred to a latch
according to the control bit in the serial data.
12 11 PS I
Power saving mode control. This pin must be set at “L” at Power-ON.
(Open is prohibited.)
PS = “H”; Normal mode
PS = “L”; Power saving mode
13 12 ZC I
Forced high-impedance control for the charge pump (with internal pull up
resistor.)
ZC = “H”; Normal Do output.
ZC = “L”; Do becomes high impedance.
14 13 LD/fout O
Lock detect signal output (LD)/phase comparator monitoring output (fout).
The output signal is selected via programming of the LDS bit.
LDS = “H”; outputs fout (fr/fp monitoring output)
LDS = “L”; outputs LD (“H” at locking, “L” at unlocking.)
15 14 φPO
Phase comparator N-channel open drain output for an external charge
pump. Phase can be selected via programming of the FC bit.
16 15 φRO
Phase comparator CMOS output for an external charge pump. Phase can
be selected via programming of the FC bit.

MB15E07SL
4
■BLOCK DIAGRAM
Clock
Data
fin
LE
OSCOUT
OSCIN
PS
DO
VP
φR
LD/fout
φP
Prescaler
32/33
64/65
Xfin
GND
VCC
MD
ZC
C
N
T
SW FC CS
LDS
fr
fp
. .
. . . . . .
(16)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(15)
(14)
(13)
(12)
(11)
(10)
(9)
(8)
16
15
14
13
12
11
10
98
7
6
5
4
3
2
1Reference
oscillator
circuit
Binary 14-bit
reference counter
Phase
comparator
Lock
detector
LD/fr/fp
selector
Charge pump
Current switch
14-bit latch
7-bit latch Intermittent
mode control
(power save)
11-bit latch
1-bit
control
latch
4-bit latch
19-bit shift register
Binary 7-bit
swallow counter Binary 11-bit
programmable
counter
: SSOP
( ) : BCC

MB15E07SL
5
■ABSOLUTE MAXIMUM RATINGS
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■RECOMMENDED OPERATING CONDITIONS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
Parameter Symbol Condition Rating Unit Remark
Min Max
Power supply voltage VCC ––0.54.0V
VP–VCC 6.0 V
Input voltage VI––0.5VCC +0.5 V
Output voltage VOExcept Do GND VCC V
VODo GND VPV
Storage temperature Tstg – –55 +125 °C
Parameter Symbol Value Unit Remark
Min Typ Max
Power supply voltage VCC 2.4 3.0 3.6 V
VPVCC –5.5V
Input voltage VIGND – VCC V
Operating temperature Ta –40 – +85 °C

MB15E07SL
6
■ELECTRICAL CHARACTERISTICS (VCC = 2.4 to 3.6 V, Ta = –40 to +85°C)
*1 : Conditions; fosc = 12 MHz, Ta = +25°C, in locking state.
*2 : VCC = VP= 3.0 V, fosc = 12.8 MHz, Ta = +25°C, in power saving mode
Parameter Symbol Condition Value Unit
Min Typ Max
Power supply current*1ICC*1 fin = 2500 MHz, VCC = VP= 2.7 V
(VCC = VP= 3.0 V) –3.5
(4.0) –mA
Power saving current IPS ZC = “H” or open – 0.1*2 10 µA
Operating frequency fin fIN – 700 – 2500 MHz
OSCIN OSCIN –3–40MHz
Input sensitivity fin*3 Pfin 50 Ω system
(Refer to the measurement
circuit.) –15 – +2 dBm
OSCIN*3 VOSC –0.5–VCC Vp-p
“H” level input voltage Data,
Clock,
LE,PS,
ZC
VIH –VCC × 0.7 – –
V
“L” level input voltage VIL –––VCC × 0.3
“H” level input current Data,
Clock,
LE, PS
IIH*4 ––1.0–+1.0
µA
“L” level input current IIL*4 ––1.0–+1.0
“H” level input current OSCIN IIH – 0 – +100 µA
“L” level input current IIL*4 ––100–0
“H” level input current ZC IIH*4 ––1.0–+1.0
µA
“L” level input current IIL*4 Pull up input –100 – 0
“L” level output voltage φ
φφ
φPV
OL Open drain output – – 0.4 V
“H” level output voltage φ
φφ
φR,
LD/fout VOH VCC = VP= 3.0 V, IOH = –1 mA VCC – 0.4 – – V
“L” level output voltage VOL VCC = VP= 3.0 V, IOL = 1 mA – – 0.4
“H” level output voltage Do VDOH VCC = VP= 3.0 V, IDOH = –0.5 mA VP– 0.4 – – V
“L” level output voltage VDOL VCC = VP= 3.0 V, IDOL = 0.5 mA – – 0.4
High impedance cutoff
current Do IOFF VCC = VP= 3.0 V,
VOFF = 0.5 V to VP– 0.5 V ––2.5nA
“L” level output current φ
φφ
φPI
OL Open drain output 1.0 – – mA
“H” level output current φ
φφ
φR,
LD/fout IOH ––––1.0
mA
“L” level output current IOL –1.0––
“H” level output current Do IDOH*4 VCC = 3 V,
VP = 3 V,
VDO = VP/2
Ta = +25°C
CS bit = “H” – –6.0 –
mA
CS bit = “L” – –1.5 –
“L” level output current IDOL CS bit = “H” – 6.0 –
CS bit = “L” – 1.5 –
Charge pump current
rate
IDOL/IDOH IDOMT*5 VDO = VP/2 –3–%
vs VDO IDOVD*6 0.5 V ≤VDO ≤VP– 0.5 V – 10 – %
vs Ta IDOTA*7 – 40°C ≤Ta ≤+85°C–10–%

MB15E07SL
7
*3 : AC coupling. 1000 pF capacitor is connected under the condition of Min operating frequency.
*4 : The symbol “–” (minus) means direction of current flow.
*5 : VCC = VP= 3.0 V, Ta = +25°C (|I3| – |I4|) / [(|I3| + |I4|) /2] ×100(%)
*6 : VCC = VP= 3.0 V, Ta = +25°C [(|I2| – |I1|) /2] / [(|I1| + |I2|) /2] ×100(%) (Applied to each IDOL, IDOH)
*7 : VCC = VP= 3.0 V, VDO = VP/2 (|IDO(85°C) – IDO(–40°C)| /2) / (|IDO(85°C) + IDO(–40°C)| /2) ×100(%) (Applied to each IDOL, IDOH)
I1
I1
I3I2
I2I4
IDOL
IDOH
0.5
Charge Pump Output Voltage (V)
Vp/2 Vp Vp −0.5 V

MB15E07SL
8
■FUNCTIONAL DESCRIPTION
1. Pulse Swallow Function
The divide ratio can be calculated using the following equation:
fVCO = [(M ×N) + A] ×fOSC ÷R (A < N)
fVCO : Output frequency of external voltage controlled oscillator (VCO)
N : Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
A : Preset divide ratio of binary 7-bit swallow counter (0 ≤A ≤127)
fOSC : Output frequency of the reference frequency oscillator
R : Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
M : Preset divide ratio of modulus prescaler (32 or 64)
2. Serial Data Input
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference
divider and the programmable divider separately.
Binary serial data is entered through the Data pin.
One bit of data is shifted into the shift register on the rising edge of the Clock. When the LE signal pin is taken
high, stored data is latched according to the control bit data as follows:
Table 1. Control Bit
(1) Shift Register Configuration
Control bit (CNT) Destination of serial data
H For the programmable reference divider
L For the programmable divider
12345678910111213141516171819
C
N
T
R
1R 2R 3R 4R 5R 6R 7R 8R 9R 10 R 11 R 12 R 13 R 14 SW FC LDS CS
Programmable Reference Counter
MSB
Data Flow
CNT : Control bit [Table 1]
R1 to R14 : Divide ratio setting bit for the programmable reference counter (3 to 16,383) [Table 2]
SW : Divide ratio setting bit for the prescaler (32/33 or 64/65) [Table 5]
FC : Phase control bit for the phase comparator [Table 8]
LDS : LD/fOUT signal select bit [Table 7]
CS : Charge pump current select bit [Table 6]
Note: Start data input with MSB first.
LSB

MB15E07SL
9
Table 2. Binary 14-bit Programmable Reference Counter Data Setting
Note : Divide ratio less than 3 is prohibited.
Table 3. Binary 11-bit Programmable Counter Data Setting
Note : Divide ratio less than 3 is prohibited.
Table 4. Binary 7-bit Swallow Counter Data Setting
Divideratio(R) R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1
3 00000000000011
4 00000000000100
⋅ ⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅
16383 11111111111111
Divideratio(N)N11N10N9N8N7N6N5N4N3N2N1
3 00000000011
4 00000000100
⋅ ⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅
2047 11111111111
Divideratio(A) A7A6A5A4A3A2A1
0 0000000
1 0000001
⋅ ⋅⋅⋅⋅⋅⋅⋅
127 1111111
12345678910111213141516171819
C
N
T
A
1A 2A 3A 4A 5A 6A 7N 1N 2N 3N 4N 5N 6N 7N 8N 9N 10 N 11
Programmable Counter
LSB MSB
Data Flow
CNT : Control bit [Table 1]
N1 to N11 : Divide ratio setting bits for the programmable counter (3 to 2,047) [Table 3]
A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127) [Table 4]
Note: Data input with MSB first.

MB15E07SL
10
Table 5. Prescaler Data Setting
Table 6. Charge Pump Current Setting
Table 7. LD/fout Output Select Data Setting
(2) Relation between the FC Input and Phase Characteristics
The FC bit changes the phase characteristics of the phase comparator. Both the internal charge pump output
level (DO) and the phase comparator output (φR, φP) are reversed according to the FC bit. Also, the monitor pin
(fOUT) output is controlled by the FC bit. The relationship between the FC bit and each of DO, φR, and φP is shown
below.
Table 8. FC Bit Data Setting (LDS = “H”)
* : High-Z
SW Prescaler divide ratio
H32/33
L64/65
CS Current value
H±6.0 mA
L±1.5 mA
LDS LD/fOUT output signal
H fout signal
L LD signal
FC = High FC = Low
DOφ
φφ
φRφ
φφ
φPLD/foutD Oφ
φφ
φRφ
φφ
φPLD/fout
fr > fPHLL
fout = fr
LHZ*
fout = fpfr < fPLHZ* HLL
fr = fPZ* L Z* Z* L Z*

MB15E07SL
11
When designing a synthesizer, the FC pin setting depends on the VCO and LPF characteristics.
3. Do Output Control
Table 9. ZC Pin Setting
4. Power Saving Mode (Intermittent Mode Control Circuit)
Table 10. PS Pin Setting
The intermittent mode control circuit reduces the PLL power consumption.
By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See
the Electrical Characteristics chart for the specific value.
The phase detector output, Do, becomes high impedance.
For the signal PLL, the lock detector, LD, remains high, indicating a locked condition.
Setting the PS pin high, releases the power saving mode, and the device works normally.
Theintermittentmodecontrolcircuitalso ensures a smooth startup when the devicereturns to normaloperation.
When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is
because
of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can
cause a major change in the comparator output, resulting in a VCO frequency jump and an increase in lockup
time.
To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error
signal from the phase detector when it returns to normal operation.
When power (VCC) is first applied, the device must be in standby mode, PS = Low, for at least 1 µs.
ZC pin Do output
H Normal output
L High impedance
PS pin Status
H Normal mode
L Power saving mode
(1)
(2)
* : When the LPF and VCO characteristics are similar
to (1), set FC bit high.
* : When the VCO characteristics are similar to (2), set
FC bit low.
VCO
Output
Frequency
LPF Output Voltage
PLL LPF VCO

MB15E07SL
12
Note : PS pin must be set “L” for Power-ON .
ONOFF
VCC
Clock
Data
LE
PS
(1) (2) (3)
tV≥1 µs
tPS ≥100 ns
(1) PS = L (power saving mode) at Power ON
(2) Set serial data 1 µs later after power supply remains stable (VCC >2.2 V).
(3) Release power saving mode (PS: L →H) 100 ns later after setting serial data.

MB15E07SL
13
■SERIAL DATA INPUT TIMING
1st data 2nd data
Control bit Invalid data
Data
Clock
LE
MSB LSB
t1t2t3
t6
t5t4
t7
∼
∼
∼
∼
Note : LE should be “L” when the data is transferred into the shift register.
Parameter Min Typ Max Unit
t120 – – ns
t220 – – ns
t330 – – ns
t430 – – ns
Parameter Min Typ Max Unit
t5100 – – ns
t620 – – ns
t7100 – – ns
On the rising edge of the clock, one bit of data is transferred into the shift register.

MB15E07SL
14
■PHASE COMPARATOR OUTPUT WAVEFORM
fr
fp
LD
DO
DO
tWU tWL
Notes : •Phase error detection range: –2πto +2π
•Pulses on Do signal during locked state are output to prevent dead zone.
•LDoutputbecomeslowwhenphaseistWU ormore.LD output becomeshighwhenphaseerror
is tWL or less and continues to be so for three cycles or more.
•t
WU and tWL depend on OSCIN input frequency.
tWU >2/fosc (s) (e. g. tWU > 156.3 ns, fosc = 12.8 MHz)
tWU <4/fosc (s) (e. g. tWL < 312.5 ns, fosc = 12.8 MHz)
•LD becomes high during the power saving mode (PS = “L”).
[FC = “H”]
[FC = “L”]

MB15E07SL
15
■MEASURMENT CIRCUIT (for Measuring Input Sensitivity fin/OSCIN)
S • G
50 Ω
1000 pF S • G
50 Ω
1000 pF
0.1 µF
0.1 µF
86431
9101112 14
75 2
13 15 16
1000 pF
VCC
fin Xfin GND DOVCC VPOSCOUT OSCIN
Clock Data LE PS ZC LD/fout φPφR
Controller (setting divide ratio) Oscilloscope
Note: SSOP-16

MB15E07SL
16
■TYPICAL CHARACTERISTICS
1. fin input sensitivity
Input sensitivity −Input frequency (Prescaler: 64/65)
Input frequency fin (MHz)
Input sensitivity Pfin (dBm)
Input sensitivity −Input frequency (Prescaler: 32/33)
Input sensitivity Pfin (dBm)
Input frequency fin (MHz)
10
0
−10
−20
−30
−40
−50 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000
VCC = 2.4 V
VCC = 3.0 V
VCC = 3.6 V
Ta = +25 °C
10
0
−10
−20
−30
−40
−50 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
Ta = +25 °C
SPEC
SPEC

MB15E07SL
17
2. OSCIN input sensitivity
Input sensitivity −Input frequency
Input frequency fOSC (MHz)
Input sensitivity VOSC (dBm)
10
0
−10
−20
−30
−40
−50
−60 0 50 100 150 200
VCC = 2.4 V
VCC = 3.0 V
VCC = 3.6 V
Ta = +25 °C
SPEC

MB15E07SL
18
3. Do output current
VDO - IDO
VDO - IDO
Charge pump output voltage VDO (V)
Charge pump output current IDO (mA)
Charge pump output voltage VDO (V)
Charge pump output current IDO (mA)
10.00
–10.00 0.6000/div 4.800
2.000
/div
0
Ta = +25°C
VCC = 3.0 V
Vp = 3.0 V
IDOH
IDOL
10.00
–10.00 0.6000/div 4.800
2.000
/div
0
Ta = +25°C
VCC = 3.0 V
Vp = 3.0 V
IDOH
IDOL
1.5 mA mode
6.0 mA mode

MB15E07SL
19
4. fin input impedance
5. OSCIN input impedance
12.646 Ω
–57.156 Ω
1 GHz
22.156 Ω
–12.136 Ω
1.5 GHz
33.805 Ω
11.869 Ω
2 GHz
1:
2:
3:
4: 23.715 Ω
8.9629 Ω
2.5 GHz
1
4
3
2
START 500.000 000 MHz STOP 2 500.000 000 MHz
9.917 Ω
–3.643 Ω
3 MHz
3.7903 Ω
–4.812 Ω
10 MHz
1.574 Ω
–3.4046 Ω
20 MHz
1:
2:
3:
4: 453.12 Ω
–1.9213 Ω
40 MHz
1
2
3
4
START 1.000 000 MHz STOP 50.000 000 MHz

MB15E07SL
20
■REFERENCE INFORMATION
(Continued)
S.G
Spectrum
Analyzer
OSCIN
fin Do LPF
VCO
Test Circuit fVCO = 810.45 MHz
KV= 17 MHz/V
fr = 25 kHz
fOSC = 14.4 MHz
VCC =VP= 3.0 V
VVCO = 2.3 V
Ta = +25 °C
CP : 6 mA mode
9.1 kΩ
4.2 kΩ
0.047 µF1500 pF
4700 pF
LPF
REF –5.0 dBm ATT 10 dB
10 dB/
RBW
1 kHz
SAMPLE
VBW
1 kHz
MKR 25.0 kHz
–78.0 dB
CENTER 810.000 MHz
SPAN 200 kHz
SWP 1.0 s
REF –5.0 dBm ATT 10 dB
10 dB/
RBW
100 Hz
SAMPLE
VBW
100 Hz
MKR 2.28 kHz
–53.1 dB
CENTER 810.000 MHz
SPAN 20.0 kHz
SWP 10 s
PLL Reference Leakage
PLL Phase Noise