Fujitsu MB15F74UL User manual

DS04-21374-1E
FUJITSU SEMICONDUCTOR
DATA SHEET
ASSP
Dual Serial Input
PLL Frequency Synthesizer
MB15F74UL
■DESCRIPTION
The Fujitsu MB15F74UL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 4000 MHz and
a 2000 MHz prescalers. A 64/65 or a 128/129 for the 4000 MHz prescaler, and a 32/33 or a 64/65 for the
2000 MHz prescaler can be selected for the prescaler that enables pulse swallow operation.
The BiCMOS process is used, as a result a supply current is typically 9.0 mA at 3.0 V. The supply voltage range
is from 2.7 V to 3.6 V. A refined charge pump supplies well-balanced output current with 1.5 mA and 6 mA
selectablebyserial date.Thepinassignmentsarethe sameas MB15F78UL.Fast lockingis achieved for adopting
the new circuit.
The new package (BCC20) decreases a mount area of MB15F74UL more than 30%comparing with the former
BCC16 (for dual PLL) .
■FEATURES
• High frequency operation : RF synthesizer : 4000 MHz Max
: IF synthesizer : 2000 MHz Max
• Low power supply voltage : VCC =2.7 to 3.6 V
• Ultra low power supply current : ICC =9.0 mA Typ
(VCC =Vp =3.0 V, Ta =+25 °C, SWIF =SWRF =0 in IF/RF locking state)
(Continued)
■PACKAGE
20-pad plastic BCC
(LCC-20P-M05)

MB15F74UL
2
(Continued)
• Direct power saving function : Power supply current in power saving mode
Typ 0.1 µA (VCC =Vp =3.0 V, Ta =+25 °C)
Max 10 µA (VCC =Vp =3.0 V)
• Software selectable charge pump current : 1.5 mA/6.0 mA Typ
• Dual modulus prescaler : 4000 MHz prescaler (64/65 or128/129) /2000 MHz prescaler (32/33 or 64/65)
• 23 bit shift register
• Serial input binary 14-bit programmable reference divider : R =3 to 16,383
• Serial input programmable divider consisting of:
- Binary 7-bit swallow counter : 0 to 127
- Binary 11-bit programmable counter : 3 to 2,047
• Built-in high-speed tuning, low-noise phase comparator, current-switching type constant current circuit
• On-chip phase control for phase comparator
• On-chip phase comparator for fast lock and low noise
• Built-in digital locking detector circuit to detect PLL locking and unlocking
• Operating temperature : Ta =−40 °C to +85 °C
■PIN ASSIGNMENTS
(BCC-20)
TOP VIEW
(LCC-20P-M05)
finIF
XfinIF
GNDIF
VCCIF
PSIF
VpIF
1
2
3
4
5
6
16
15
14
13
12
11
LE
finRF
XfinRF
GNDRF
VCCRF
PSRF
78910
20 19 18 17
DoIF DoRF
LD/fout VpRF
GND
OSCIN Data
Clock

MB15F74UL
3
■PIN DESCRIPTION
Pin no. Pin
name I/O Descriptions
1fin
IF IPrescaler input pin for the IF-PLL.
Connection to an external VCO should be AC coupling.
2Xfin
IF IPrescaler complimentary input for the IF-PLL section.
This pin should be grounded via a capacitor.
3GND
IF Ground pin for the IF-PLL section.
4VCCIF Power supply voltage input pin for the IF-PLL section (except for the charge pump
circuit) , the shift register and the oscillator input buffer.
5PS
IF I
Power saving mode control pin for the IF-PLL section. This pin must be set at “L” when
the power supply is started up. (Open is prohibited.)
PSIF =“H” ; Normal mode/PSIF =“L” ; Power saving mode
6Vp
IF Power supply voltage input pin for the IF-PLL charge pump.
7DoIF O Charge pump output for the IF-PLL section.
8 LD/fout O Lock detect signal output (LD) /phase comparator monitoring output (fout) pin. The output signal is selected by LDS bit in a serial data.
LDS bit =“H” ; outputs fout signal/LDS bit =“L” ; outputs LD signal
9Do
RF O Charge pump output for the RF-PLL section.
10 VpRF Power supply voltage input pin for the RF-PLL charge pump.
11 PSRF IPower saving mode control for the RF-PLL section. This pin must be set at “L” when the
power supply is started up. (Open is prohibited. )
PSRF =“H” ; Normal mode/PSRF =“L” ; Power saving mode
12 VCCRF Power supply voltage input pin for the RF-PLL section (except for the charge pump
circuit)
13 GNDRF Ground pin for the RF-PLL section
14 XfinRF IPrescaler complimentary input pin for the RF-PLL section.
This pin should be grounded via a capacitor.
15 finRF IPrescaler input pin for the RF-PLL.
Connection to an external VCO should be via AC coupling.
16 LE I Load enable signal input pin (with the schmitt trigger circuit) When LE is set “H”, data in the shift register is transferred to the corresponding latch
according to the control bit in a serial data.
17 Data I Serial data input pin (with the schmitt trigger circuit) Data is transferred to the corresponding latch (IF-ref. counter, IF-prog. counter, RF-ref.
counter, RF-prog. counter) according to the control bit in a serial data.
18 Clock I Clock input pin for the 23-bit shift register (with the schmitt trigger circuit)
One bit data is shifted into the shift register on a rising edge of the clock.
19 OSCIN IThe programmable reference divider input pin. TCXO should be connected with an AC
coupling capacitor.
20 GND Ground pin for OSC input buffer and the shift register circuit.

MB15F74UL
4
■BLOCK DIAGRAM
(9)
Clock
Data
LE
PSRF
XfinRF
finRF
OSCIN
finIF
PSIF
VCCIF GNDIF
fpIF
DoIF
LDIF
T1 T2
T1 T2
FCRF
SWRF
LDS
DoRF
OR LD/
fout
LD
frIF
frRF
fpIF
fpRF
frIF
frRF
fpRF
C
N
1
C
N
2
AND
VCCRF GNDRF VpRF
(19)
( )
(11)
(17)
(18)
(12) (13) (10)
(8)
(7)
(3)
(4)
(1)
(5)
(15)
GND
(20)
(16)
14
XfinIF (2)
VpIF
(6)
Intermittent
mode control
(IF-PLL)
Prescaler
(IF-PLL)
(32/33, 64/65)
7 bit latch 11 bit latch
Binary 7-bit
swallow counter
(IF-PLL)
Binary 11-bit
programmable
counter (IF-PLL)
Phase
comp.
(IF-PLL)
Charge
pump
(IF-PLL) Current
Switch
2 bit latch 14 bit latch 1 bit latch
Binary 14-bit pro-
grammable ref.
counter(IF-PLL) C/P setting
counter
Lock Det.
(IF-PLL)
2 bit latch 14 bit latch 1 bit latch
Binary 14-bit pro-
grammable ref.
counter (RF-PLL)) C/P setting
counter
Selector
Prescaler
(RF-PLL)
(64/65, 128/129) Lock Det.
(RF-PLL)
Intermittent
mode control
(RF-PLL) 3 bit latch
FCIF
SWIF
LDS
3 bit latch
7 bit latch 11 bit latch
Binary 7-bit
swallow counter
(RF-PLL)
Binary 11-bit
programmable
counter (RF-PLL)
Phase
comp.
(RF-PLL)
Fast lock
Tuning
Charge
pump
(RF-PLL)
Current
Switch
Schmitt
circuit Latch selector
Schmitt
circuit
Schmitt
circuit 23-bit shift register
Fast
lock
Tuning
LDRF
fpRF

MB15F74UL
5
■ABSOLUTE MAXIMUM RATINGS
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■RECOMMENDED OPERATING CONDITIONS
Note : •VCCRF, VpRF, VCCIF and VpIF must supply equal voltage.
EvenifeitherRF-PLLorIF-PLLisnotused,powermustbesuppliedtoVCCRF,VpRF, VCCIF andVpIF tokeep
them equal.
It is recommended that the non-use PLL is controlled by power saving function.
•Although this device contains an anti-static element to prevent electrostatic breakdown and the circuitry
hasbeenimprovedinelectrostatic protection,observethefollowingprecautions whenhandlingthe device.
•When storing and transporting the device, put it in a conductive case.
•Beforehandlingthedevice,confirmthe (jigsand)toolstobeusedhavebeenuncharged(grounded)as
well as yourself. Use a conductive sheet on working bench.
•Before fitting the device into or removing it from the socket, turn the power supply off.
•When handling (such as transporting) the device mounted board, protect the leads with a conductive
sheet.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
Parameter Symbol Rating Unit
Min Max
Power supply voltage VCC −0.5 4.0 V
Vp VCC 4.0 V
Input voltage VI−0.5 VCC +0.5 V
Output voltage LD/fout VOGND VCC V
DoIF, DoRF VDO GND Vp V
Storage temperature Tstg −55 +125 °C
Parameter Symbol Value Unit Remarks
Min Typ Max
Power supply voltage VCC 2.7 3.0 3.6 V VCCRF =VCCIF
Vp VCC 3.0 3.6 V
Input voltage VIGND VCC V
Operating temperature Ta −40 +85 °C

MB15F74UL
6
*
■ELECTRICAL CHARACTERISTICS (VCC =2.7 V to 3.6 V, Ta =−40 °C to +85 °C)
(Continued)
Parameter Symbol Condition Value Unit
Min Typ Max
Power supply current ICCIF *1 finIF =2000 MHz
VCCIF =VpIF =3.0 V 2.1 2.5 3.2 mA
ICCRF *1 finRF =2500 MHz
VCCRF =VpRF =3.0 V 5.7 6.5 8.4 mA
Power saving current IPSIF PSIF =PSRF =“L” 0.1*2 10 µA
IPSRF PSIF =PSRF =“L” 0.1*2 10 µA
Operating frequency
finIF *3 finIF IF PLL 200 2000 MHz
finRF *3 finRF RF PLL 2000 4000 MHz
OSCIN fOSC 340 MHz
Input sensitivity finIF PfinIF IF PLL, 50 Ωsystem −15 +2dBm
finRF PfinRF RF PLL, 50 Ωsystem −10 +2dBm
Input available voltage OSCIN VOSC 0.5 VCC VP−P
“H” level input voltage Data
LE
Clock
VIH Schmitt trigger input 0.7 VCC
+0.4 V
“L” level input voltage VIL Schmitt trigger input 
0.3 VCC
−0.4 V
“H” level input voltage PSIF
PSRF
VIH 0.7 VCC V
“L” level input voltage VIL 0.3 VCC V
“H” level input current Data
LE
Clock
PS
IIH *4 −1.0 +1.0 µA
“L” level input current IIL *4 −1.0 +1.0 µA
“H” level input current OSCIN IIH 0+100 µA
“L” level input current IIL *4 −100 0µA
“H”leveloutputvoltage LD/
fout VOH VCC =Vp =3.0 V, IOH =−1 mA VCC −0.4 V
“L” level output voltage VOL VCC =Vp =3.0 V, IOL =1 mA 0.4 V
“H”leveloutputvoltage DoIF
DoRF
VDOH VCC =Vp =3.0 V, IDOH =−0.5 mA Vp −0.4 V
“L” level output voltage VDOL VCC =Vp =3.0 V, IDOL =0.5 mA 0.4 V
High impedance cutoff
current DoIF
DoRF IOFF VCC =Vp =3.0 V
VOFF =0.5 V to Vp −0.5 V 2.5 nA
“H” level output current LD/
fout IOH *4 VCC =Vp =3.0 V −1.0 mA
“L” level output current IOL VCC =Vp =3.0 V 1.0 mA

MB15F74UL
7
(Continued)
(VCC =2.7 V to 3.6 V, Ta =−40 °C to +85 °C)
*1 : Conditions ; fosc =12.8 MHz, Ta =+25 °C, SW =“L” in locking state.
*2 : VCCIF =VpIF =VCCRF =VpRF =3.0 V, fosc =12.8 MHz, Ta =+25 °C, in power saving mode.
PSIF =PSRF =GND
VIH =VCC, VIL =GND (at CLK, Data, LE)
*3 : AC coupling. 1000 pF capacitor is connected under the condition of Min operating frequency.
*4 : The symbol “–” (minus) means the direction of current flow.
*5 : VCC =Vp =3.0 V, Ta =+25 °C (||I3| −|I4||) /[ (|I3| +|I4|) /2] ×100 (%)
*6 : VCC =Vp =3.0 V, Ta =+25 °C [ (||I2| −|I1||) /2] /[ (|I1| +|I2|) /2] ×100 (%) (Applied to both lDOL and lDOH)
*7 : VCC =Vp =3.0 V, [||IDO (+85 °C) | −|IDO (–40 °C) || /2] /[|IDO (+85 °C) | +|IDO (–40 °C) | /2] ×100 (%) (Applied to both
IDOL and IDOH)
*8 : When Charge pump current is measured, set LDS =“L” , T1 =“L” and T2 =“H”.
Parameter Symbol Condition Value Unit
Min Typ Max
“H” level output
current DoIF *8
DoRF IDOH *4 VCC =Vp =3.0 V,
VDOH =Vp /2,
Ta =+25 °C
CS bit =“H” −8.2 −6.0 −4.1 mA
CS bit =“L” −2.2 −1.5 −0.8 mA
“L” level output
current DoIF *8
DoRF IDOL VCC =Vp =3.0 V,
VDOL =Vp /2,
Ta =+25 °C
CS bit =“H” 4.1 6.0 8.2 mA
CS bit =“L” 0.8 1.5 2.2 mA
Charge pump
current rate
IDOL/IDOH IDOMT *5 VDO =Vp /2 310%
vs VDO IDOVD *6 0.5 V ≤VDO ≤Vp −0.5 V 10 15 %
vs Ta IDOTA *7 −40 °C ≤Ta ≤85 °C,
VDO =Vp /2 510%
IDOL
I1I3I2
I1
I4
I2
0.5 Vp/2 Vp −0.5 Vp
IDOH
Charge pump output voltage (V)

MB15F74UL
8
■FUNCTIONAL DESCRIPTION
1. Pulse swallow function
fVCO =[ (P ×N) +A] ×fOSC ÷R
fVCO : Output frequency of external voltage controlled oscillator (VCO)
P : Preset divide ratio of dual modulus prescaler (32 or 64 for IF-PLL, 64or 128 for RF-PLL)
N : Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
A : Preset divide ratio of binary 7-bit swallow counter (0 ≤A ≤127, A < N)
fOSC : Reference oscillation frequency (OSCIN input frequency)
R : Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
2. Serial Data Input
The serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF-
PLL sections, programmable reference dividers of IF/RF-PLL sections are controlled individually.
The serial data of binary data is entered through Data pin.
On rising edge of Clock, one bit of the serial data is transferred into the shift register. On a rising edge of load
enable signal, the data stored in the shift register is transferred to one of latches depending upon the control bit
data setting.
(1) Shift Register Configuration
The programmable
reference counter
for the IF-PLL
The programmable
reference counter
for the RF-PLL
The programmable
counter and the swallow
counter for the IF-PLL
The programmable
counter and the swallow
counter for the RF-PLL
CN1 0 1 0 1
CN2 0 0 1 1
•Programmable Reference Counter
CS : Charge pump current select bit
R1 to R14 : Divide ratio setting bits for the programmable reference counter (3 to 16,383)
T1, 2 : LD/fout output setting bit
CN1, 2 : Control bit
X : Dummy bits (Set “0” or “1”)
Note : Data input with MSB first.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CN1 CN2 T1 T2 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 CS X X X X
(LSB) (MSB)Data Flow

MB15F74UL
9
(2) Data setting
•Binary 14-bit Programmable Reference Counter Data Setting
Note : Divide ratio less than 3 is prohibited.
•Binary 11-bit Programmable Counter Data Setting
Note : Divide ratio less than 3 is prohibited
•Binary 7-bit Swallow Counter Data Setting
DivideratioR14R13R12R11R10R9R8R7R6R5R4R3R2R1
3 00000000000011
4
•
•
•
16383
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
1
•
•
•
1
0
•
•
•
1
0
•
•
•
1
DivideratioN11N10N9N8N7N6N5N4N3N2N1
3 00000000011
4
•
•
•
2047
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
1
•
•
•
1
0
•
•
•
1
0
•
•
•
1
DivideratioA7A6A5A4A3A2A1
0 0000000
1
•
•
•
127
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
0
•
•
•
1
1
•
•
•
1
• Programmable Counter
A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127)
N1 to N11 : Divide ratio setting bits for the programmable counter (3 to 2,047)
LDS : LD/fout signal select bit
SWIF/RF : Divide ratio setting bit for the prescaler (IF : SWIF, RF : SWRF)
FCIF/RF : Phase control bit for the phase detector (IF : FCIF, RF : FCRF)
CN1, 2 : Control bit
Note : Data input with MSB first.
1 2 3 4 5 6 7 8 9 101112131415161718192021 22 23
CN1 CN2 LDS SWIF/
RF FCIF/ RF A1 A2 A3 A4 A5 A6 A7 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11
(LSB) (MSB) Data Flow

MB15F74UL
10
•Prescaler Data Setting
• Charge Pump Current Setting
•LD/fout output Selectable Bit Setting
•Phase Comparator Phase Switching Data Setting
Z: High-impedance
Depending upon the VCO and LPF polarity, FC bit should be set.
Divide ratio SW =
==
=“H” SW =
==
=“L”
Prescaler divide ratio IF-PLL 32/33 64/65
Prescaler divide ratio RF-PLL 64/65 128/129
Current value CS
±6.0 mA 1
±1.5 mA 0
LD/fout pin state LDS T1 T2
LD output
000
010
011
fout
output
frIF 100
frRF 110
fpIF 101
fpRF 111
Phase comparator input FCIF, RF =
==
=“H” FCIF, RF =
==
=“L”
DoIF, RF DoIF, RF
fr >fp H L
fr <fp L H
fr =fp Z Z
(1)
(2)
(1) VCO polarity FC =“H”
(2) VCO polarity FC =“L”
Note : Give attention to the polarity for using active type LPF.
VCO Output
Frequency
High
LPF Output voltage Max

MB15F74UL
11
3. Power Saving Mode (Intermittent Mode Control Circuit)
The intermittent mode control circuit reduces the PLL power consumption.
By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See
the Electrical Characteristics chart for the specific value.
The phase detector output, Do, becomes high impedance.
For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table.
Setting the PS pin high, releases the power saving mode, and the device works normally.
Theintermittent modecontrolcircuit alsoensures asmooth startupwhen thedevicereturns tonormal operation.
When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is
because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr)
which can cause a major change in the comparaor output, resulting in a VCO frequency jump and an increase
in lockup time.
To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error
signal from the phase detector when it returns to normal operation.
Notes : •When power (VCC) is first applied, the device must be in standby mode.
•PS pin must be set “L” at Power-ON.
Status PS pin
Normal mode H
Power saving mode L
ONOFF
VCC
Clock
Data
LE
PS
(1) (2) (3)
tPS ≥ 100 ns
tV≥ 1 µs
(1) PS =L (power saving mode) at Power-ON
(2) Set serial data at least 1 µs after the power supply becomes stable (VCC ≥2.2 V) .
(3) Release power saving mode (PSIF, PSRF : “L” →“H”) at least 100 ns later after setting serial data.

MB15F74UL
12
4. Serial Data Data Input Timing
Divide ratio is performed through a serial interface using the Data pin, Clock pin, and LE pin.
Setting data is read into the shift register at the rise of the Clock signal, and transferred to a latch at the rise of
the LE signal. The following diagram shows the data input timing.
LSBMSB
Clock
Data
LE
t7
t1t2t3
t4t5
t6
1st data 2nd data
Control bit Invalid data
Note : LE should be “L” when the data is transferred into the shift register.
Parameter Min Typ Max Unit Parameter Min Typ Max Unit
t120  ns t5100  ns
t220  ns t620  ns
t330  ns t7100  ns
t430  ns

MB15F74UL
13
■PHASE COMPARATOR OUTPUT WAVEFORM
• LD Output Logic
Notes : •Phase error detection range =−2πto +2π
• Pulses on DoIF/RF signals during locking state are output to prevent dead zone.
• LD output becomes low when phase error is tWU or more.
• LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more.
• tWU and tWL depend on OSCIN input frequency as follows.
t
WU ≥2/fosc : e.g. tWU ≥156.3 ns when fosc =12.8 MHz
t
WU ≤4/fosc : e.g. tWL ≤312.5 ns when fosc =12.8 MHz
IF-PLL section RF-PLL section LD output
Locking state/Power saving state Locking state/Power saving state H
Locking state/Power saving state Unlocking state L
Unlocking state Locking state/Power saving state L
Unlocking state Unlocking state L
frIF/RF
fpIF/RF
LD
DoIF/RF
tWU tWL
DoIF/RF
H
L
L
H
Z
Z
(FC bit =High)
(FC bit =Low)

MB15F74UL
14
■TEST CIRCUIT (for Measuring Input Sensitivity fin/OSCIN)
1000 pF
1000 pF
1000 pF
1000 pF
0.1 µFVpRF
VCCRF
50 Ω
50 Ω
50 Ω
S.G.
S.G.
S.G.
VpIF
VCCIF
0.1 µF
0.1 µF
0.1 µF
1000 pF
Controller
(Divide ratio setting)
Oscilloscope
GND OSCIN DataClock
PSRF
VCCRF
GNDRF
XfinRF
LE
finRF
109
8
7
6
5
4
3
2
1
11
12
13
14
15
16
17
18
19
20
LD/foutDoIF DoRF VpRF
VpIF
PSIF
VCCIF
GNDIF
XfinIF
finIF
MB15F74UL

MB15F74UL
15
■TYPICAL CHARACTERISTICS
1. fin input sensitivity
10
1000 1500 2000 2500 3000 3500 4000 4500 5000 5500 6000
VCC =2.7 V
VCC =3.0 V
VCC =3.6 V
SPEC
0
−10
−20
−30
−40
−50
PfinRF [dBm]
finRF [MHz]
SPEC
10
0 500 1000 1500 2000 2500 3000 3500
VCC =3.6 V
VCC =2.7 V
VCC =3.0 V
SPEC
finIF [MHz]
PfinIF [dBm]
0
−10
−20
−30
−40
−50
SPEC
RF-PLL input sensitivity vs. Input frequency
IF-PLL input sensitivity vs. Input frequency

MB15F74UL
16
2. OSCIN input sensitivity
VCC =2.7 V
VCC =3.0 V
VCC =3.6 V
SPEC
0 50 100 150 200 250 300
0
−10
−20
−30
−40
−50
10
SPEC
Input sensitivity vs. Input frequency
Input frequency fOSC (MHz)
Input sensitivity VOSC (dBm)

MB15F74UL
17
3. RF-PLL Do output current
• 1.5 mA mode
• 6.0 mA mode
VCC =Vp =3.0 V
10.0
0
−10.0
1.0 3.00.0 2.0
Charge pump output current IDO (mA)
IDO −VDO
Charge pump output voltage VDO (V)
IDO −VDO
Charge pump output current IDO (mA)
Charge pump output voltage VDO (V)
VCC =Vp =3.0 V
10.0
0
−10.0
1.0 3.0
0.0 2.0

MB15F74UL
18
4. IF-PLL Do output current
• 1.5 mA mode
• 6.0 mA mode
IDO −VDO
Charge pump output current IDO (mA)
Charge pump output voltage VDO (V)
10.0
0
−10.0
1.0 3.0
VCC =Vp =3.0 V
0.0 2.0
IDO −VDO
Charge pump output current IDO (mA)
Charge pump output voltage VDO (V)
VCC =Vp =3.0 V
10.0
0
−10.0
1.0 3.0
0.0 2.0

MB15F74UL
19
5. fin input impedance
866.25 Ω
−916.31 Ω
100 MHz
76.5 Ω
−319.2 Ω
500 MHz
31.078 Ω
−152.46 Ω
1 GHz
1:
2:
3:
START 100.000 000 MHz STOP 2 000.000 000 MHz
4 :16.453 Ω−46.539 Ω
2 000.000 000 MHz
1
3
2
4
35 336 Ω
−151.85 Ω
1 GHz
17.436 Ω
−52.191 Ω
2 GHz
20.211 Ω
−743.16 mΩ
3 GHz
1:
2:
3:
START 1 000.000 000 MHz STOP 4 000.000 000 MHz
4 :25.791 Ω34.824 Ω
4 000.000 000 MHz
1
3
2
4
finIF input impedance
finRF input impedance

MB15F74UL
20
6. OSCIN input impedance
OSCIN input impedance
15.882 kΩ
−11.652 kΩ
3 MHz
3.924 kΩ
−8.942 kΩ
10 MHz
286 Ω
−2.5913 kΩ
40 MHz
1:
2:
3:
START 3.000 000 MHz STOP 100.000 000 MHz
4 :049.5 Ω−1.0414 kΩ
100.000 000 MHz
1
2
3
4