Gan Systems GS66508T-EVBHB User manual

GS66508T-EVBHB 650V
GaN E-HEMT Half Bridge Evaluation Board
User’s Guide
_____________________________________________________________________________________________________________________
GS66508T-EVBHB UG rev. 150917 © 2015 GaN Systems Inc. www.gansystems.com 1
Please refer to the Evaluation Board/Kit Important Notice on page 21
GS66508T-EVBHB 650V GaN E-HEMT Half
Bridge Evaluation Board
User’s Guide
Visit www.gansystems.com for the latest version of this user’s guide.
DANGER!
Electrical Shock Hazard -Hazardous high voltage may be present on the
board during the test and even brief contact during operation may result
in severe injury or death. Follow all locally approved safety procedures
when working around high voltage.
Never leave the board operating unattended. After it is de-energized,
always wait until all capacitors are discharged before touching the board.
This board should be handled by qualified personnel ONLY.
CAUTION:
This product contains parts that are susceptible to damage by electrostatic
discharge (ESD). Always follow ESD prevention procedures when
handling the product.

GS66508T-EVBHB 650V
GaN E-HEMT Half Bridge Evaluation Board
User’s Guide
_____________________________________________________________________________________________________________________
GS66508T-EVBHB UG rev. 150917 © 2015 GaN Systems Inc. www.gansystems.com 2
Please refer to the Evaluation Board/Kit Important Notice on page 21
Introduction
The GS66508T-EVBHB evaluation board (EVB) is designed to demonstrate the performance of GaN
Systems’ 650V GaN enhancement mode high electron mobility transistor (E-HEMT) devices. The EVB is a
fully functional half bridge power stage consisting of two 650V GaN E-HEMTs (top side cooled
GS66508T, 30A/55mΩ), gate drive power supply, half bridge gate drivers and heatsink. To evaluate the
performance of GaN E-HEMT devices in real power circuits, the EVB can be easily configured into any
half bridge based topology.The EVB and this USER’s Guide serve as a reference design for the gate
driver circuit, half bridge PCB layout and thermal management.
Functional Overview
Please refer to the circuit schematic in appendix for all signal names, circuit nodes and test points.
The block diagram of the GS66508T-EVBHB can be seen in Figure 1. All components are mounted on the
top side except for E-HEMTs, Q1 and Q2, which are mounted on the bottom side of the EVB. A heatsink
is mounted from the bottom side as well, in order provide cooling for the two GaN E-HEMTs. The board
includes all necessary components for building a half bridge power stage and provides footprints for
output power inductors and capacitors to allow users to configure the board into different operational
modes.
Figure 1 - GS66508T-EVBHB Evaluation Board Block Diagram
D
S
D
S
VSW
Q1
GS66508T
VBUS+
HS Gate
Driver
LS Gate
Driver
G
G
Q2
GS66508T
VBUS-
VOUT
VDS
VGL
VGH
External Mount Power
Inductor (not included)
Optional Output
Capacitor
9-12V
INPUT
Dead-time
generation
circuit
PWML
PWMH
N/I
TR1 TR2
Optional Deadtime
Adjustment Trimpot
N/I N/I
N/I – NOT INSTALLED
J3
J1
J2
J5
High side
PWM Select
N/I

GS66508T-EVBHB 650V
GaN E-HEMT Half Bridge Evaluation Board
User’s Guide
_____________________________________________________________________________________________________________________
GS66508T-EVBHB UG rev. 150917 © 2015 GaN Systems Inc. www.gansystems.com 3
Please refer to the Evaluation Board/Kit Important Notice on page 21
Figure 2 - Board overhead view
Figure 3 - Board bottom view –showing 2x GS66508T with heatsink removed

GS66508T-EVBHB 650V
GaN E-HEMT Half Bridge Evaluation Board
User’s Guide
_____________________________________________________________________________________________________________________
GS66508T-EVBHB UG rev. 150917 © 2015 GaN Systems Inc. www.gansystems.com 4
Please refer to the Evaluation Board/Kit Important Notice on page 21
Power input (J1)
Figure 4 - Power Input (J1)
The board can be powered by 9-12VDC on J1. The
supply voltage absolute maximum is 15V. On-board
voltage regulators create +5V for the logic circuit and
+6.5V for the gate driver.
Gate input (J2/J5)
Figure 5 - Gate signal input (J2/J5)
Set signal generator output level to 5V with 50Ω impedance for the gate PWM signal input on connector
J5. The high side gate drive signal can be configured by jumper J3. By default, J3 is set to the INT position
(internal, created by an on-board circuit). The on-board logic circuit inverts the PWM input on J5 to create
a complementary signal for the high side gate drive with dead time. To implement independent control
of the high side gate set J3 to EXT position (external, supplied by user on J2). Remove R13/R14 (R5/R6 for
J2) if high impedance input is required (e.g. from the logic output of a microcontroller).

GS66508T-EVBHB 650V
GaN E-HEMT Half Bridge Evaluation Board
User’s Guide
_____________________________________________________________________________________________________________________
GS66508T-EVBHB UG rev. 150917 © 2015 GaN Systems Inc. www.gansystems.com 5
Please refer to the Evaluation Board/Kit Important Notice on page 21
Dead time control
Figure 6 - Dead time control circuit
Dead time is controlled by two RC delay circuits, R16/C15 and R22/C19. By default, 100ns dead time is
used. Additionally two potentiometers locations are provided (TR1/TR2, not included) to allow fine
adjustment of the dead time if needed.

GS66508T-EVBHB 650V
GaN E-HEMT Half Bridge Evaluation Board
User’s Guide
_____________________________________________________________________________________________________________________
GS66508T-EVBHB UG rev. 150917 © 2015 GaN Systems Inc. www.gansystems.com 6
Please refer to the Evaluation Board/Kit Important Notice on page 21
Gate driver circuit
Figure 7 - Half bridge gate driver circuit
Gate drive power supply
A low side adjustable LDO (U5) steps down the input 9-12V to 6.5V for optimal gate drive. Bootstrap
diode (D1) and capacitor (C4) are used to create a floating gate drive power supply for the high side gate
drive circuit. The bootstrap voltage on C4 is then regulated by LDO (U2) to create a nominal 6.5V for
optimal gate drive.
Gate resistance
Turn-on gate resistors, R7/R18, are populated with 24.9Ωresistors. These resistors can be adjusted to
control the turn-on slew rate. Generally it is recommended to select turn-on gate resistance between 15-
25Ω for optimal performance. Smaller turn-on gate resistor values may create fast switching speeds
causing unnecessary Miller turn-on and oscillation. For turn-off it is recommended to use a small value
of less than 2Ωfor the turn-off gate resistors R10/R21. This will provide a strong pull-down during turn-
off and reduce the Miller voltage effects.
6.5V Gate Drive
VIN
600V 1A
P/N: ES1J
SMA
D1
0V
C4
1uF
0VGDH
R1
1R IN
GND
OUT
MIC5225YM5
VDRVH
0VGDH
ADJ
EN
R2
42K2
R3
10K
0VGDH
TP2
TP4
D
G
S
24R9
VDD
ANODE VO1
VO2
GND
R7
0R
R10
SI8261BAC
0VGDH
C5
2.2uF
CATH
N/C2
332R
N/C1
D2
0VGDH
FB1
15R@100MHz
0V
PMEG2010
0VGDH
U2
R8
TP8
GOH
R11
10K
TP7
VDDH
TP6
INH
TP11
HIGH SIDE FLOATING
GROUND
TP10
0VH TP12
0VGDH
J4
VGH
VSSH GNDH
U3
D
G
S
G
VIN
0V
C14
1uF
IN
GND
OUT
MIC5225YM5
VDRVL
0V
ADJ
EN
R15
42K2
R17
10K
24R9
VDD
ANODE VO1
VO2
GND
R18
0R
R21
SI8261BAC
0V
C16
2.2uF
CATH
N/C2
332R
N/C1
D3
0V
FB2
15R @100MHz
0V
PMEG2010
0V
U5
R19
TP18
GOL
R23
10K
TP17
VDDL
TP16
INL
TP21
TP20
0VL TP22
0V
J7
U6 VGL
VSSL GNDL
G
DZ4 (C18)
SOD323
6.8V 200mW
DZ3 (C11)
SOD323
6.8V 200mW

GS66508T-EVBHB 650V
GaN E-HEMT Half Bridge Evaluation Board
User’s Guide
_____________________________________________________________________________________________________________________
GS66508T-EVBHB UG rev. 150917 © 2015 GaN Systems Inc. www.gansystems.com 7
Please refer to the Evaluation Board/Kit Important Notice on page 21
Gate capacitor and clamping Clamping diode
An additional gate capacitor per drive circuit (C11/C18) is used to help shunt the Miller current and
reduce the Miller effect. The recommended value is between 100-220pF.
A clamping diode is placed close to thebetween the gate and source of each E-HEMT (DZ31/DZ42, on the
location of C11 and C18) for clamping negative gate voltage spikes induced by negative dv/dt on the
drain. It should be a fast Schottky diode or a zener diode (6.8V, 200mW, P/N: MMSZ5235BS-7-F). Added
Zener or schottky diode may contribute to gate oscillation combined with the parasitic inductance so it is
recommended to insert a ferrite bead in between clamping diode and the gate if to suppress any
unwanted gate oscillation is observed.
Ferrite bead
Ferrite bead on the gate helps to damp the gate ringing and reduce the risk of gate oscillation. On the
other hand adding ferrite bead increases the gate inductance and risk of miller turn-on. A small surface
mount device (SMD) EMI suppression ferrite bead with impedance of 10-20Ω @100MHz is sufficient for
suppressing gate oscillation while having minimal impact on the gate miller voltage. On this board a
ferrite bead is used on the gate for each devicehigh side only, FB1/FB2, (15Ω @100MHz, 0.5A, Wurth
Electronics P/N: 74279268) to stabilize the gate driver and suppress the gate ringing.
Testing your own gate driver
Figure 8 - Layout of testing pads for gate driver
Six square pads are provided around the gate driver as testing points as well as providing connection
pads for a user designed add-on gate driver board. The pads are on a 0.1” grid to allow users to
experiment with their own gate driver circuit. In this case the existing gate drive circuit(s) should be de-
populated from the EVB.
GATEVDD
IN+
VSSIN-
ISOLATION
VSS
0.3 [7.62]
0.2 [5.08]
0.3 [7.62]
Inch [mm]
GATE
INPUT GATE
OUTPUT

GS66508T-EVBHB 650V
GaN E-HEMT Half Bridge Evaluation Board
User’s Guide
_____________________________________________________________________________________________________________________
GS66508T-EVBHB UG rev. 150917 © 2015 GaN Systems Inc. www.gansystems.com 8
Please refer to the Evaluation Board/Kit Important Notice on page 21
Measurements
Drain voltage (VDS, J8)
Use a probe tip-to-BNC adapter and high voltage probe
for low side drain voltage VDS (switching node)
measurements. Avoid using a long ground lead for best
accuracy.
Gate drive signal (VGL, VGH)
The board includes two SMA connectors, J4 (high side
VGH) and J7 (low side VGL), for gate drive signal
measurements.
WARNING!
ALWAYS use high voltage differential or isolated probes for measuring high
side floating signals.
Attaching probe to high side gate signal may affect the switching behaviors
due to the added parasitic and coupling capacitance introduced by the
probe. To obtain best switching performance it is recommended to only
measure VGH for verifying gate driver operation at low voltage and remove
the probe during operation.
Measuring device temperature
Q1 and Q2 are located on the bottom side, as previously
indicated. Two PCB holes are aligned at the center of
package for measuring the device package temperature.
Use a thermal camera or attach thermocouples through
the two PCB holes for monitoring the device
temperature.

GS66508T-EVBHB 650V
GaN E-HEMT Half Bridge Evaluation Board
User’s Guide
_____________________________________________________________________________________________________________________
GS66508T-EVBHB UG rev. 150917 © 2015 GaN Systems Inc. www.gansystems.com 9
Please refer to the Evaluation Board/Kit Important Notice on page 21
Cooling
Figure 9 - Board thermal management
The board includes a customized heatsink attached to the PCB from the bottom side via 4 push pins. The
heatsink has a central pedestal copper block (20mmx20mm, 3mm height) that makes contact with the
thermal pads of two top side cooled GaN devices (GS66508T). A layer of thermal interface material (TIM,
Bergquist® Hi-Flow phase change 300P) is applied between heatsink and device thermal pad to provide
the required electrical insulation. Note that each thermal pad is connected to the substrate of the E-
HEMTs and is also internally electrically connected to the Source of the device.
Forced air cooling is recommended for power testing. The airflow direction should be controlled from
the left side as shown in Figure 9for best cooling performance.
CAUTION:
Device temperature must be closely monitored during the test. Never
operate the board with device temperature exceeding TJ_MAX (150°C)
Power Stage Setup
Power connections (CON1-6)
CON1-CON6 mounting pads are designed to be compatible with:
•#10-32 Screw mount,
•Banana Jack PCB mount (Keystone P/N: 575-4), or
•PC Mount Screw Terminal (Keystone P/N: 8191)
Output passives (L and C17)
An external power inductor (not included) can be connected between VSW (CON3) and VOUT (CON4)
or VBUS- (CON5/6), depending on the operation mode (see below). Users can choose their inductor size
to meet the test requirement. Generally it is recommended to use toroid power inductor with low inter-
winding capacitance to obtain best switching performance. For pulse testing we used 2x 60uH/40Amp
inductor (CWS, P/N: HF467-600M-40AV) in series.
GS66508T TIM
Heatsink central
block 20x20mm
Cross section view
FAN
Airflow direction

GS66508T-EVBHB 650V
GaN E-HEMT Half Bridge Evaluation Board
User’s Guide
_____________________________________________________________________________________________________________________
GS66508T-EVBHB UG rev. 150917 © 2015 GaN Systems Inc. www.gansystems.com 10
Please refer to the Evaluation Board/Kit Important Notice on page 21
C17 is designed to accommodate a film capacitor as output filter (not included). It has a universal
footprint that is compatible with Vishay MKP1848 series film capacitor 700V 1 to 35uF (P1=27.5-37.5mm,
P2=0-10.2mm, 2 or 4pins).
Operation mode
The board can be configured to any half bridge based topology and used as the building block for real
power conversion circuits. There are generally three operation modes:
Pulse test mode
Figure 10 - Pulse test mode and waveforms
Similar to a standard double pulse testing circuit, the user can test half bridge inductive switching
performance by connecting the inductor from VSW to VBUS-. In this mode, the high side device Q1 is
hard switching (control) and low side Q2 is used as free-wheeling device (sync), which is driven
synchronously.
Figure 10 shows an example of the PWM input signal and pulse test switching waveforms for the pulse
test mode. Since a bootstrap circuit is used to create the high side gate voltage, the low side device Q2
must be turned on first before the first testing pulse to ensure that the high side gate driver is powered
up. This can be implemented by setting the signal generator output to “Inverse” mode on the signal so
the PWML is always high before and after the testing pulses. It is recommended to use a single trigger
burst mode and manually trigger the signal generator for each test to avoid any heating of the devices.
The maximum switching current for pulse test can be calculated by:
IL_MAX = TON * N * VDS / L, (Eq.1)
Where TON is the turn-on time per cycle, N is the total number of testing pulses and L is the inductance.
Set N = 3-5 to test the switching performance at different current ranges. Choose the inductance value
between 50 to 200uH and use the inductor with a current rating higher than your switching test current to
avoid saturation.
Trigger
+5V
0V
PWML
INPUT ...
N Cycles
VDS
IL
IL_MAX
T
ON
D
S
D
S
CON3
Q1
GS66508T
CON1
G
Q2
GS66508T
VBUS-
CON4
G
CON2
L
400V
+
VBUS+
CON6
CON5
VSW
IL
VDS
VGH