Hitachi H8S/2338 Series User manual

H8S/2338 Series, H8S/2328 Series,
H8S/2318 Series
Hardware Manual
— Specifications Common to All Series —
ADE-602-171
Rev. 1.0
3/1/99
Hitachi, Ltd.

Cautions
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have received the latest product standards or specifications before final design, purchase or
use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.
However, contact Hitachi’s sales office before using the product in an application that
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power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of
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semiconductor products.

Organization of H8S/2338 Series, H8S/2328 Series,
H8S/2318 Series Hardware Manual
The H8S/2338 Series, H8S/2328 Series, H8S/2318 Series Hardware Manual describes the
operation of on-chip functions common to the H8S/2338 Series, H8S/2328 Series, and H8S/2318
Series, in particular, and gives a detailed description of the related registers. Information specific
to individual products, including pin arrangement, I/O ports, MCU operating modes (memory
maps), interrupt vectors, bus control, and electrical characteristics, can be found in the Reference
Manual for the relevant product.
Overview
Pin arrangement diagram
Block diagrams of function modules
Pin functions
Electrical characteristics
For product
evaluation
information, or
comparative
specification
information
for current
users of Hitachi
products
1.1 Overview
1.3 Pin Arrangement
Section 6 Peripheral Block Diagrams
1.5 Pin Functions
Section 7 Electrical Characteristics
I/O port information
Interrupts and exception handling
Pin functions
For detailed
information
on functions Section 5 I/O Ports
Section 3 Exception Handling and
Interrupt Controller
1.5 Pin Functions
List
Detailed descriptions
1.4 Pin Functions in Each Operating
Mode
Section 2 MCU Operating Modes
List
To find a register from its address
To find register information by function
For use as design
material Section 8 registers
8.1 List of Registers (Address Order)
8.2 List of Registers (By Module)
List
Operation description and notes
Program examples
H8S/2600 Series, H8S/2000 Series
Programming Manual
For H8S/2338 Series, H8S/2328 Series, H8S/2318 Series specifications
For details of the operation of individual modules
For information on operating modes
For information on registers
For information on instructions

Preface
The H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series are series of high-performance
microcontrollers with a 32-bit H8S/2000 CPU core, and a set of on-chip supporting functions
required for system configuration.
The H8S/2000 CPU can execute basic instructions in one state, and is provided with sixteen 16-bit
general registers with a 32-bit internal configuration, and a concise and optimized instruction set.
The CPU can handle a 16-Mbyte linear address space (architecturally 4 Gbytes). Programs based
on the high-level language C can also be run efficiently.
The address space is divided into eight areas. The data bus width and access states can be selected
for each of these areas, and various kinds of memory can be connected fast and easily.
Single-power-supply flash memory (F-ZTAT™) and mask ROM versions are available, providing
a quick and flexible response to conditions from ramp-up through full-scale volume production,
even for applications with frequently changing specifications.
On-chip supporting functions include a 16-bit timer pulse unit (TPU), programmable pulse
generator (PPG), 8-bit timer, watchdog timer (WDT), serial communication interface (SCI), A/D
converter, D/A converter, and I/O ports.
In addition, an on-chip DMA controller (DMAC) and data transfer controller (DTC) are provided,
enabling high-speed data transfer without CPU intervention.
Use of the H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series enables easy implementation
of compact, high-performance systems capable of processing large volumes of data.
This manual describes the hardware of the H8S/2338 Series, H8S/2328 Series, and H8S/2318
Series, covering features, specifications, registers and operation. It should be used in conjunction
with the H8S/2338 Series Reference Manual, H8S/2328 Series Reference Manual, and H8S/2318
Series Reference Manual which contain information relating to the H8S/2338 Series and
H8S/2328 Series hardware—including specifications and register descriptions—required for
system design.
Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a detailed description of
the instruction set and programming-related information.

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Contents
Section 1 Overview........................................................................................................... 1
1.1 Overview............................................................................................................................ 1
Section 2 Exception Handling........................................................................................ 7
2.1 Overview............................................................................................................................ 7
2.1.1 Exception Handling Types and Priority............................................................... 7
2.1.2 Exception Handling Operation............................................................................. 8
2.1.3 Exception Vector Table........................................................................................ 8
2.2 Reset.................................................................................................................................. 10
2.2.1 Overview.............................................................................................................. 10
2.2.2 Reset Sequence..................................................................................................... 10
2.2.3 Interrupts after Reset............................................................................................ 11
2.2.4 State of On-Chip Supporting Modules after Reset Release ................................. 11
2.3 Traces ................................................................................................................................ 12
2.4 Interrupts............................................................................................................................ 13
2.5 Trap Instruction ................................................................................................................. 14
2.6 Stack Status after Exception Handling.............................................................................. 14
2.7 Notes on Use of the Stack.................................................................................................. 15
Section 3 Interrupt Controller........................................................................................ 17
3.1 Overview............................................................................................................................ 17
3.1.1 Features..................................................................................................................... 17
3.1.2 Block Diagram.......................................................................................................... 18
3.1.3 Pin Configuration...................................................................................................... 19
3.1.4 Register Configuration.............................................................................................. 19
3.2 Register Descriptions......................................................................................................... 20
3.2.1 System Control Register (SYSCR) ...................................................................... 20
3.2.2 Interrupt Priority Registers A to K (IPRA to IPRK)............................................ 21
3.2.3 IRQ Enable Register (IER) .................................................................................. 22
3.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 23
3.2.5 IRQ Status Register (ISR).................................................................................... 24
3.3 Interrupt Sources................................................................................................................ 25
3.3.1 External Interrupts................................................................................................ 25
3.3.2 Internal Interrupts................................................................................................. 26
3.3.3 Interrupt Exception Vector Table......................................................................... 26
3.4 Interrupt Operation............................................................................................................ 30
3.4.1 Interrupt Control Modes and Interrupt Operation................................................ 30
3.4.2 Interrupt Control Mode 0...................................................................................... 33
3.4.3 Interrupt Control Mode 2...................................................................................... 35

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3.4.4 Interrupt Exception Handling Sequence .............................................................. 37
3.4.5 Interrupt Response Times..................................................................................... 39
3.5 Usage Notes....................................................................................................................... 40
3.5.1 Contention between Interrupt Generation and Disabling..................................... 40
3.5.2 Instructions that Disable Interrupts ...................................................................... 41
3.5.3 Times when Interrupts are Disabled..................................................................... 41
3.5.4 Interrupts during Execution of EEPMOV Instruction.......................................... 41
3.6 DTC and DMAC Activation by Interrupt.......................................................................... 42
3.6.1 Overview.............................................................................................................. 42
3.6.2 Block Diagram...................................................................................................... 42
3.6.3 Operation.............................................................................................................. 43
Section 4 Bus Controller.................................................................................................. 45
4.1 Overview............................................................................................................................ 45
4.1.1 Features ................................................................................................................ 45
4.1.2 Block Diagram...................................................................................................... 47
4.1.3 Pin Configuration ................................................................................................. 48
4.1.4 Register Configuration ......................................................................................... 49
4.2 Register Descriptions......................................................................................................... 50
4.2.1 Bus Width Control Register (ABWCR)............................................................... 50
4.2.2 Access State Control Register (ASTCR).............................................................. 51
4.2.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 52
4.2.4 Bus Control Register H (BCRH).......................................................................... 55
4.2.5 Bus Control Register L (BCRL)........................................................................... 57
4.2.6 Memory Control Register (MCR)........................................................................ 60
4.2.7 DRAM Control Register (DRAMCR).................................................................. 62
4.2.8 Refresh Timer Counter (RTCNT)........................................................................ 64
4.2.9 Refresh Time Constant Register (RTCOR).......................................................... 64
4.3 Overview of Bus Control................................................................................................... 65
4.3.1 Area Partitioning .................................................................................................. 65
4.3.2 Bus Specifications................................................................................................ 66
4.3.3 Memory Interfaces................................................................................................ 67
4.3.4 Advanced Mode.................................................................................................... 68
4.3.5 Chip Select Signals............................................................................................... 69
4.4 Basic Bus Interface............................................................................................................ 70
4.4.1 Overview.............................................................................................................. 70
4.4.2 Data Size and Data Alignment............................................................................. 70
4.4.3 Valid Strobes........................................................................................................ 72
4.4.4 Basic Timing ........................................................................................................ 73
4.4.5 Wait Control......................................................................................................... 81
4.5 DRAM Interface................................................................................................................ 83
4.5.1 Overview.............................................................................................................. 83
4.5.2 Setting DRAM Space........................................................................................... 83

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4.5.3 Address Multiplexing........................................................................................... 83
4.5.4 Data Bus ............................................................................................................... 84
4.5.5 Pins Used for DRAM Interface............................................................................ 84
4.5.6 Basic Timing ........................................................................................................ 85
4.5.7 Precharge State Control........................................................................................ 86
4.5.8 Wait Control......................................................................................................... 87
4.5.9 Byte Access Control............................................................................................. 89
4.5.10 Burst Operation .................................................................................................... 91
4.5.11 Refresh Control .................................................................................................... 94
4.6 DMAC Single Address Mode and DRAM Interface ........................................................ 97
4.6.1 When DDS = 1 ..................................................................................................... 97
4.6.2 When DDS = 0 ..................................................................................................... 98
4.7 Burst ROM Interface .........................................................................................................99
4.7.1 Overview.............................................................................................................. 99
4.7.2 Basic Timing ........................................................................................................ 99
4.7.3 Wait Control......................................................................................................... 101
4.8 Idle Cycle........................................................................................................................... 102
4.8.1 Operation.............................................................................................................. 102
4.8.2 Pin States in Idle Cycle ........................................................................................ 106
4.9 Write Data Buffer Function............................................................................................... 107
4.10 Bus Release........................................................................................................................ 108
4.10.1 Overview.............................................................................................................. 108
4.10.2 Operation.............................................................................................................. 108
4.10.3 Pin States in External Bus Released State............................................................ 109
4.10.4 Transition Timing................................................................................................. 110
4.10.5 Usage Note ........................................................................................................... 111
4.11 Bus Arbitration.................................................................................................................. 111
4.11.1 Overview.............................................................................................................. 111
4.11.2 Operation.............................................................................................................. 111
4.11.3 Bus Transfer Timing ............................................................................................ 112
4.11.4 External Bus Release Usage Note........................................................................ 112
4.12 Resets and the Bus Controller............................................................................................ 112
Section 5 DMA Controller.............................................................................................. 113
5.1 Overview................................................................................................................................ 113
5.1.1 Features ................................................................................................................ 113
5.1.2 Block Diagram...................................................................................................... 114
5.1.3 Overview of Functions......................................................................................... 115
5.1.4 Pin Configuration ................................................................................................. 117
5.1.5 Register Configuration ......................................................................................... 118
5.2 Register Descriptions (1) (Short Address Mode).............................................................. 119
5.2.1 Memory Address Registers (MAR)...................................................................... 120
5.2.2 I/O Address Register (IOAR)............................................................................... 121

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5.2.3 Execute Transfer Count Register (ETCR)............................................................ 121
5.2.4 DMA Control Register (DMACR)....................................................................... 122
5.2.5 DMA Band Control Register (DMABCR)........................................................... 126
5.3 Register Descriptions (2) (Full Address Mode) ................................................................ 131
5.3.1 Memory Address Register (MAR)....................................................................... 131
5.3.2 I/O Address Register (IOAR)............................................................................... 131
5.3.3 Execute Transfer Count Register (ETCR)............................................................ 132
5.3.4 DMA Control Register (DMACR)....................................................................... 133
5.3.5 DMA Band Control Register (DMABCR)........................................................... 137
5.4 Register Descriptions (3)................................................................................................... 142
5.4.1 DMA Write Enable Register (DMAWER).......................................................... 142
5.4.2 DMA Terminal Control Register (DMATCR)..................................................... 144
5.4.3 Module Stop Control Register (MSTPCR).......................................................... 145
5.5 Operation ........................................................................................................................... 146
5.5.1 Transfer Modes .................................................................................................... 146
5.5.2 Sequential Mode................................................................................................... 148
5.5.3 Idle Mode.............................................................................................................. 151
5.5.4 Repeat Mode ........................................................................................................ 154
5.5.5 Single Address Mode ........................................................................................... 158
5.5.6 Normal Mode........................................................................................................ 161
5.5.7 Block Transfer Mode............................................................................................ 164
5.5.8 DMAC Activation Sources .................................................................................. 170
5.5.9 Basic DMAC Bus Cycles..................................................................................... 173
5.5.10 DMAC Bus Cycles (Dual Address Mode)........................................................... 174
5.5.11 DMAC Bus Cycles (Single Address Mode) ........................................................ 182
5.5.12 Write Data Buffer Function.................................................................................. 188
5.5.13 DMAC Multi-Channel Operation ........................................................................ 189
5.5.14 Relation Between the DMAC and External Bus Requests, Refresh Cycles,
and the DTC ......................................................................................................... 190
5.5.15 NMI Interrupts and DMAC.................................................................................. 191
5.5.16 Forced Termination of DMAC Operation............................................................ 192
5.5.17 Clearing Full Address Mode ................................................................................ 193
5.6 Interrupts............................................................................................................................ 194
5.7 Usage Notes....................................................................................................................... 195
Section 6 Data Transfer Controller .............................................................................. 199
6.1 Overview............................................................................................................................ 199
6.1.1 Features ................................................................................................................ 199
6.1.2 Block Diagram...................................................................................................... 200
6.1.3 Register Configuration ......................................................................................... 201
6.2 Register Descriptions......................................................................................................... 202
6.2.1 DTC Mode Register A (MRA)............................................................................. 202
6.2.2 DTC Mode Register B (MRB)............................................................................. 204

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6.2.3 DTC Source Address Register (SAR).................................................................. 205
6.2.4 DTC Destination Address Register (DAR).......................................................... 205
6.2.5 DTC Transfer Count Register A (CRA) .............................................................. 205
6.2.6 DTC Transfer Count Register B (CRB)............................................................... 206
6.2.7 DTC Enable Registers (DTCER) ......................................................................... 206
6.2.8 DTC Vector Register (DTVECR)........................................................................ 207
6.2.9 Module Stop Control Register (MSTPCR).......................................................... 208
6.3 Operation ........................................................................................................................... 209
6.3.1 Overview.............................................................................................................. 209
6.3.2 Activation Sources................................................................................................ 213
6.3.3 DTC Vector Table................................................................................................ 214
6.3.4 Location of Register Information in Address Space............................................ 217
6.3.5 Normal Mode........................................................................................................ 218
6.3.6 Repeat Mode ........................................................................................................ 219
6.3.7 Block Transfer Mode............................................................................................ 220
6.3.8 Chain Transfer...................................................................................................... 222
6.3.9 Operation Timing ................................................................................................. 223
6.3.10 Number of DTC Execution States........................................................................ 224
6.3.11 Procedures for Using DTC................................................................................... 226
6.3.12 Examples of Use of the DTC................................................................................ 227
6.4 Interrupts............................................................................................................................ 232
6.5 Usage Notes....................................................................................................................... 232
Section 7 16-Bit Timer Pulse Unit (TPU).................................................................. 233
7.1 Overview............................................................................................................................ 233
7.1.1 Features ................................................................................................................ 233
7.1.2 Block Diagram...................................................................................................... 237
7.1.3 Pin Configuration ................................................................................................. 238
7.1.4 Register Configuration ......................................................................................... 240
7.2 Register Descriptions......................................................................................................... 242
7.2.1 Timer Control Registers (TCR)............................................................................ 242
7.2.2 Timer Mode Registers (TMDR)........................................................................... 247
7.2.3 Timer I/O Control Registers (TIOR).................................................................... 249
7.2.4 Timer Interrupt Enable Registers (TIER)............................................................. 262
7.2.5 Timer Status Registers (TSR) .............................................................................. 264
7.2.6 Timer Counters (TCNT)....................................................................................... 268
7.2.7 Timer General Registers (TGR)........................................................................... 268
7.2.8 Timer Start Register (TSTR)................................................................................ 269
7.2.9 Timer Synchro Register (TSYR).......................................................................... 269
7.2.10 Module Stop Control Register (MSTPCR).......................................................... 270
7.3 Interface to Bus Master...................................................................................................... 271
7.3.1 16-Bit Registers.................................................................................................... 271
7.3.2 8-Bit Registers...................................................................................................... 271

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7.4 Operation ........................................................................................................................... 273
7.4.1 Overview.............................................................................................................. 273
7.4.2 Basic Functions .................................................................................................... 274
7.4.3 Synchronous Operation........................................................................................ 280
7.4.4 Buffer Operation .................................................................................................. 282
7.4.5 Cascaded Operation.............................................................................................. 286
7.4.6 PWM Modes ........................................................................................................ 288
7.4.7 Phase Counting Mode .......................................................................................... 293
7.5 Interrupts............................................................................................................................ 300
7.5.1 Interrupt Sources and Priorities............................................................................ 300
7.5.2 DTC/DMAC Activation....................................................................................... 302
7.5.3 A/D Converter Activation.................................................................................... 302
7.6 Operation Timing .............................................................................................................. 303
7.6.1 Input/Output Timing ............................................................................................ 303
7.6.2 Interrupt Signal Timing........................................................................................ 307
7.7 Usage Notes....................................................................................................................... 311
Section 8 Programmable Pulse Generator (PPG) .................................................... 321
8.1 Overview............................................................................................................................ 321
8.1.1 Features ................................................................................................................ 321
8.1.2 Block Diagram...................................................................................................... 322
8.1.3 Pin Configuration ................................................................................................. 323
8.1.4 Registers............................................................................................................... 324
8.2 Register Descriptions......................................................................................................... 325
8.2.1 Next Data Enable Registers H and L (NDERH, NDERL)................................... 325
8.2.2 Output Data Registers H and L (PODRH, PODRL)............................................ 326
8.2.3 Next Data Registers H and L (NDRH, NDRL).................................................... 327
8.2.4 Notes on NDR Access.......................................................................................... 327
8.2.5 PPG Output Control Register (PCR).................................................................... 329
8.2.6 PPG Output Mode Register (PMR)...................................................................... 331
8.2.7 Port 1 Data Direction Register (P1DDR)............................................................. 333
8.2.8 Port 2 Data Direction Register (P2DDR)............................................................. 334
8.2.9 Module Stop Control Register (MSTPCR).......................................................... 334
8.3 Operation ........................................................................................................................... 335
8.3.1 Overview.............................................................................................................. 335
8.3.2 Output Timing...................................................................................................... 336
8.3.3 Normal Pulse Output............................................................................................ 337
8.3.4 Non-Overlapping Pulse Output............................................................................ 339
8.3.5 Inverted Pulse Output........................................................................................... 342
8.3.6 Pulse Output Triggered by Input Capture ............................................................ 343
8.4 Usage Notes....................................................................................................................... 344
8.4.1 Operation of Pulse Output Pins............................................................................ 344
8.4.2 Note on Non-Overlapping Output........................................................................ 344