Hitachi H8S/2338 Series User manual

H8S/2338 Series, H8S/2328 Series,
H8S/2318 Series
Hardware Manual
— Specifications Common to All Series —
ADE-602-171
Rev. 1.0
3/1/99
Hitachi, Ltd.

Cautions
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have received the latest product standards or specifications before final design, purchase or
use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.
However, contact Hitachi’s sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
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power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
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semiconductor products.

Organization of H8S/2338 Series, H8S/2328 Series,
H8S/2318 Series Hardware Manual
The H8S/2338 Series, H8S/2328 Series, H8S/2318 Series Hardware Manual describes the
operation of on-chip functions common to the H8S/2338 Series, H8S/2328 Series, and H8S/2318
Series, in particular, and gives a detailed description of the related registers. Information specific
to individual products, including pin arrangement, I/O ports, MCU operating modes (memory
maps), interrupt vectors, bus control, and electrical characteristics, can be found in the Reference
Manual for the relevant product.
Overview
Pin arrangement diagram
Block diagrams of function modules
Pin functions
Electrical characteristics
For product
evaluation
information, or
comparative
specification
information
for current
users of Hitachi
products
1.1 Overview
1.3 Pin Arrangement
Section 6 Peripheral Block Diagrams
1.5 Pin Functions
Section 7 Electrical Characteristics
I/O port information
Interrupts and exception handling
Pin functions
For detailed
information
on functions Section 5 I/O Ports
Section 3 Exception Handling and
Interrupt Controller
1.5 Pin Functions
List
Detailed descriptions
1.4 Pin Functions in Each Operating
Mode
Section 2 MCU Operating Modes
List
To find a register from its address
To find register information by function
For use as design
material Section 8 registers
8.1 List of Registers (Address Order)
8.2 List of Registers (By Module)
List
Operation description and notes
Program examples
H8S/2600 Series, H8S/2000 Series
Programming Manual
For H8S/2338 Series, H8S/2328 Series, H8S/2318 Series specifications
For details of the operation of individual modules
For information on operating modes
For information on registers
For information on instructions

Preface
The H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series are series of high-performance
microcontrollers with a 32-bit H8S/2000 CPU core, and a set of on-chip supporting functions
required for system configuration.
The H8S/2000 CPU can execute basic instructions in one state, and is provided with sixteen 16-bit
general registers with a 32-bit internal configuration, and a concise and optimized instruction set.
The CPU can handle a 16-Mbyte linear address space (architecturally 4 Gbytes). Programs based
on the high-level language C can also be run efficiently.
The address space is divided into eight areas. The data bus width and access states can be selected
for each of these areas, and various kinds of memory can be connected fast and easily.
Single-power-supply flash memory (F-ZTAT™) and mask ROM versions are available, providing
a quick and flexible response to conditions from ramp-up through full-scale volume production,
even for applications with frequently changing specifications.
On-chip supporting functions include a 16-bit timer pulse unit (TPU), programmable pulse
generator (PPG), 8-bit timer, watchdog timer (WDT), serial communication interface (SCI), A/D
converter, D/A converter, and I/O ports.
In addition, an on-chip DMA controller (DMAC) and data transfer controller (DTC) are provided,
enabling high-speed data transfer without CPU intervention.
Use of the H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series enables easy implementation
of compact, high-performance systems capable of processing large volumes of data.
This manual describes the hardware of the H8S/2338 Series, H8S/2328 Series, and H8S/2318
Series, covering features, specifications, registers and operation. It should be used in conjunction
with the H8S/2338 Series Reference Manual, H8S/2328 Series Reference Manual, and H8S/2318
Series Reference Manual which contain information relating to the H8S/2338 Series and
H8S/2328 Series hardware—including specifications and register descriptions—required for
system design.
Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a detailed description of
the instruction set and programming-related information.

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Contents
Section 1 Overview........................................................................................................... 1
1.1 Overview............................................................................................................................ 1
Section 2 Exception Handling........................................................................................ 7
2.1 Overview............................................................................................................................ 7
2.1.1 Exception Handling Types and Priority............................................................... 7
2.1.2 Exception Handling Operation............................................................................. 8
2.1.3 Exception Vector Table........................................................................................ 8
2.2 Reset.................................................................................................................................. 10
2.2.1 Overview.............................................................................................................. 10
2.2.2 Reset Sequence..................................................................................................... 10
2.2.3 Interrupts after Reset............................................................................................ 11
2.2.4 State of On-Chip Supporting Modules after Reset Release ................................. 11
2.3 Traces ................................................................................................................................ 12
2.4 Interrupts............................................................................................................................ 13
2.5 Trap Instruction ................................................................................................................. 14
2.6 Stack Status after Exception Handling.............................................................................. 14
2.7 Notes on Use of the Stack.................................................................................................. 15
Section 3 Interrupt Controller........................................................................................ 17
3.1 Overview............................................................................................................................ 17
3.1.1 Features..................................................................................................................... 17
3.1.2 Block Diagram.......................................................................................................... 18
3.1.3 Pin Configuration...................................................................................................... 19
3.1.4 Register Configuration.............................................................................................. 19
3.2 Register Descriptions......................................................................................................... 20
3.2.1 System Control Register (SYSCR) ...................................................................... 20
3.2.2 Interrupt Priority Registers A to K (IPRA to IPRK)............................................ 21
3.2.3 IRQ Enable Register (IER) .................................................................................. 22
3.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 23
3.2.5 IRQ Status Register (ISR).................................................................................... 24
3.3 Interrupt Sources................................................................................................................ 25
3.3.1 External Interrupts................................................................................................ 25
3.3.2 Internal Interrupts................................................................................................. 26
3.3.3 Interrupt Exception Vector Table......................................................................... 26
3.4 Interrupt Operation............................................................................................................ 30
3.4.1 Interrupt Control Modes and Interrupt Operation................................................ 30
3.4.2 Interrupt Control Mode 0...................................................................................... 33
3.4.3 Interrupt Control Mode 2...................................................................................... 35

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3.4.4 Interrupt Exception Handling Sequence .............................................................. 37
3.4.5 Interrupt Response Times..................................................................................... 39
3.5 Usage Notes....................................................................................................................... 40
3.5.1 Contention between Interrupt Generation and Disabling..................................... 40
3.5.2 Instructions that Disable Interrupts ...................................................................... 41
3.5.3 Times when Interrupts are Disabled..................................................................... 41
3.5.4 Interrupts during Execution of EEPMOV Instruction.......................................... 41
3.6 DTC and DMAC Activation by Interrupt.......................................................................... 42
3.6.1 Overview.............................................................................................................. 42
3.6.2 Block Diagram...................................................................................................... 42
3.6.3 Operation.............................................................................................................. 43
Section 4 Bus Controller.................................................................................................. 45
4.1 Overview............................................................................................................................ 45
4.1.1 Features ................................................................................................................ 45
4.1.2 Block Diagram...................................................................................................... 47
4.1.3 Pin Configuration ................................................................................................. 48
4.1.4 Register Configuration ......................................................................................... 49
4.2 Register Descriptions......................................................................................................... 50
4.2.1 Bus Width Control Register (ABWCR)............................................................... 50
4.2.2 Access State Control Register (ASTCR).............................................................. 51
4.2.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 52
4.2.4 Bus Control Register H (BCRH).......................................................................... 55
4.2.5 Bus Control Register L (BCRL)........................................................................... 57
4.2.6 Memory Control Register (MCR)........................................................................ 60
4.2.7 DRAM Control Register (DRAMCR).................................................................. 62
4.2.8 Refresh Timer Counter (RTCNT)........................................................................ 64
4.2.9 Refresh Time Constant Register (RTCOR).......................................................... 64
4.3 Overview of Bus Control................................................................................................... 65
4.3.1 Area Partitioning .................................................................................................. 65
4.3.2 Bus Specifications................................................................................................ 66
4.3.3 Memory Interfaces................................................................................................ 67
4.3.4 Advanced Mode.................................................................................................... 68
4.3.5 Chip Select Signals............................................................................................... 69
4.4 Basic Bus Interface............................................................................................................ 70
4.4.1 Overview.............................................................................................................. 70
4.4.2 Data Size and Data Alignment............................................................................. 70
4.4.3 Valid Strobes........................................................................................................ 72
4.4.4 Basic Timing ........................................................................................................ 73
4.4.5 Wait Control......................................................................................................... 81
4.5 DRAM Interface................................................................................................................ 83
4.5.1 Overview.............................................................................................................. 83
4.5.2 Setting DRAM Space........................................................................................... 83

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4.5.3 Address Multiplexing........................................................................................... 83
4.5.4 Data Bus ............................................................................................................... 84
4.5.5 Pins Used for DRAM Interface............................................................................ 84
4.5.6 Basic Timing ........................................................................................................ 85
4.5.7 Precharge State Control........................................................................................ 86
4.5.8 Wait Control......................................................................................................... 87
4.5.9 Byte Access Control............................................................................................. 89
4.5.10 Burst Operation .................................................................................................... 91
4.5.11 Refresh Control .................................................................................................... 94
4.6 DMAC Single Address Mode and DRAM Interface ........................................................ 97
4.6.1 When DDS = 1 ..................................................................................................... 97
4.6.2 When DDS = 0 ..................................................................................................... 98
4.7 Burst ROM Interface .........................................................................................................99
4.7.1 Overview.............................................................................................................. 99
4.7.2 Basic Timing ........................................................................................................ 99
4.7.3 Wait Control......................................................................................................... 101
4.8 Idle Cycle........................................................................................................................... 102
4.8.1 Operation.............................................................................................................. 102
4.8.2 Pin States in Idle Cycle ........................................................................................ 106
4.9 Write Data Buffer Function............................................................................................... 107
4.10 Bus Release........................................................................................................................ 108
4.10.1 Overview.............................................................................................................. 108
4.10.2 Operation.............................................................................................................. 108
4.10.3 Pin States in External Bus Released State............................................................ 109
4.10.4 Transition Timing................................................................................................. 110
4.10.5 Usage Note ........................................................................................................... 111
4.11 Bus Arbitration.................................................................................................................. 111
4.11.1 Overview.............................................................................................................. 111
4.11.2 Operation.............................................................................................................. 111
4.11.3 Bus Transfer Timing ............................................................................................ 112
4.11.4 External Bus Release Usage Note........................................................................ 112
4.12 Resets and the Bus Controller............................................................................................ 112
Section 5 DMA Controller.............................................................................................. 113
5.1 Overview................................................................................................................................ 113
5.1.1 Features ................................................................................................................ 113
5.1.2 Block Diagram...................................................................................................... 114
5.1.3 Overview of Functions......................................................................................... 115
5.1.4 Pin Configuration ................................................................................................. 117
5.1.5 Register Configuration ......................................................................................... 118
5.2 Register Descriptions (1) (Short Address Mode).............................................................. 119
5.2.1 Memory Address Registers (MAR)...................................................................... 120
5.2.2 I/O Address Register (IOAR)............................................................................... 121

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5.2.3 Execute Transfer Count Register (ETCR)............................................................ 121
5.2.4 DMA Control Register (DMACR)....................................................................... 122
5.2.5 DMA Band Control Register (DMABCR)........................................................... 126
5.3 Register Descriptions (2) (Full Address Mode) ................................................................ 131
5.3.1 Memory Address Register (MAR)....................................................................... 131
5.3.2 I/O Address Register (IOAR)............................................................................... 131
5.3.3 Execute Transfer Count Register (ETCR)............................................................ 132
5.3.4 DMA Control Register (DMACR)....................................................................... 133
5.3.5 DMA Band Control Register (DMABCR)........................................................... 137
5.4 Register Descriptions (3)................................................................................................... 142
5.4.1 DMA Write Enable Register (DMAWER).......................................................... 142
5.4.2 DMA Terminal Control Register (DMATCR)..................................................... 144
5.4.3 Module Stop Control Register (MSTPCR).......................................................... 145
5.5 Operation ........................................................................................................................... 146
5.5.1 Transfer Modes .................................................................................................... 146
5.5.2 Sequential Mode................................................................................................... 148
5.5.3 Idle Mode.............................................................................................................. 151
5.5.4 Repeat Mode ........................................................................................................ 154
5.5.5 Single Address Mode ........................................................................................... 158
5.5.6 Normal Mode........................................................................................................ 161
5.5.7 Block Transfer Mode............................................................................................ 164
5.5.8 DMAC Activation Sources .................................................................................. 170
5.5.9 Basic DMAC Bus Cycles..................................................................................... 173
5.5.10 DMAC Bus Cycles (Dual Address Mode)........................................................... 174
5.5.11 DMAC Bus Cycles (Single Address Mode) ........................................................ 182
5.5.12 Write Data Buffer Function.................................................................................. 188
5.5.13 DMAC Multi-Channel Operation ........................................................................ 189
5.5.14 Relation Between the DMAC and External Bus Requests, Refresh Cycles,
and the DTC ......................................................................................................... 190
5.5.15 NMI Interrupts and DMAC.................................................................................. 191
5.5.16 Forced Termination of DMAC Operation............................................................ 192
5.5.17 Clearing Full Address Mode ................................................................................ 193
5.6 Interrupts............................................................................................................................ 194
5.7 Usage Notes....................................................................................................................... 195
Section 6 Data Transfer Controller .............................................................................. 199
6.1 Overview............................................................................................................................ 199
6.1.1 Features ................................................................................................................ 199
6.1.2 Block Diagram...................................................................................................... 200
6.1.3 Register Configuration ......................................................................................... 201
6.2 Register Descriptions......................................................................................................... 202
6.2.1 DTC Mode Register A (MRA)............................................................................. 202
6.2.2 DTC Mode Register B (MRB)............................................................................. 204

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6.2.3 DTC Source Address Register (SAR).................................................................. 205
6.2.4 DTC Destination Address Register (DAR).......................................................... 205
6.2.5 DTC Transfer Count Register A (CRA) .............................................................. 205
6.2.6 DTC Transfer Count Register B (CRB)............................................................... 206
6.2.7 DTC Enable Registers (DTCER) ......................................................................... 206
6.2.8 DTC Vector Register (DTVECR)........................................................................ 207
6.2.9 Module Stop Control Register (MSTPCR).......................................................... 208
6.3 Operation ........................................................................................................................... 209
6.3.1 Overview.............................................................................................................. 209
6.3.2 Activation Sources................................................................................................ 213
6.3.3 DTC Vector Table................................................................................................ 214
6.3.4 Location of Register Information in Address Space............................................ 217
6.3.5 Normal Mode........................................................................................................ 218
6.3.6 Repeat Mode ........................................................................................................ 219
6.3.7 Block Transfer Mode............................................................................................ 220
6.3.8 Chain Transfer...................................................................................................... 222
6.3.9 Operation Timing ................................................................................................. 223
6.3.10 Number of DTC Execution States........................................................................ 224
6.3.11 Procedures for Using DTC................................................................................... 226
6.3.12 Examples of Use of the DTC................................................................................ 227
6.4 Interrupts............................................................................................................................ 232
6.5 Usage Notes....................................................................................................................... 232
Section 7 16-Bit Timer Pulse Unit (TPU).................................................................. 233
7.1 Overview............................................................................................................................ 233
7.1.1 Features ................................................................................................................ 233
7.1.2 Block Diagram...................................................................................................... 237
7.1.3 Pin Configuration ................................................................................................. 238
7.1.4 Register Configuration ......................................................................................... 240
7.2 Register Descriptions......................................................................................................... 242
7.2.1 Timer Control Registers (TCR)............................................................................ 242
7.2.2 Timer Mode Registers (TMDR)........................................................................... 247
7.2.3 Timer I/O Control Registers (TIOR).................................................................... 249
7.2.4 Timer Interrupt Enable Registers (TIER)............................................................. 262
7.2.5 Timer Status Registers (TSR) .............................................................................. 264
7.2.6 Timer Counters (TCNT)....................................................................................... 268
7.2.7 Timer General Registers (TGR)........................................................................... 268
7.2.8 Timer Start Register (TSTR)................................................................................ 269
7.2.9 Timer Synchro Register (TSYR).......................................................................... 269
7.2.10 Module Stop Control Register (MSTPCR).......................................................... 270
7.3 Interface to Bus Master...................................................................................................... 271
7.3.1 16-Bit Registers.................................................................................................... 271
7.3.2 8-Bit Registers...................................................................................................... 271

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7.4 Operation ........................................................................................................................... 273
7.4.1 Overview.............................................................................................................. 273
7.4.2 Basic Functions .................................................................................................... 274
7.4.3 Synchronous Operation........................................................................................ 280
7.4.4 Buffer Operation .................................................................................................. 282
7.4.5 Cascaded Operation.............................................................................................. 286
7.4.6 PWM Modes ........................................................................................................ 288
7.4.7 Phase Counting Mode .......................................................................................... 293
7.5 Interrupts............................................................................................................................ 300
7.5.1 Interrupt Sources and Priorities............................................................................ 300
7.5.2 DTC/DMAC Activation....................................................................................... 302
7.5.3 A/D Converter Activation.................................................................................... 302
7.6 Operation Timing .............................................................................................................. 303
7.6.1 Input/Output Timing ............................................................................................ 303
7.6.2 Interrupt Signal Timing........................................................................................ 307
7.7 Usage Notes....................................................................................................................... 311
Section 8 Programmable Pulse Generator (PPG) .................................................... 321
8.1 Overview............................................................................................................................ 321
8.1.1 Features ................................................................................................................ 321
8.1.2 Block Diagram...................................................................................................... 322
8.1.3 Pin Configuration ................................................................................................. 323
8.1.4 Registers............................................................................................................... 324
8.2 Register Descriptions......................................................................................................... 325
8.2.1 Next Data Enable Registers H and L (NDERH, NDERL)................................... 325
8.2.2 Output Data Registers H and L (PODRH, PODRL)............................................ 326
8.2.3 Next Data Registers H and L (NDRH, NDRL).................................................... 327
8.2.4 Notes on NDR Access.......................................................................................... 327
8.2.5 PPG Output Control Register (PCR).................................................................... 329
8.2.6 PPG Output Mode Register (PMR)...................................................................... 331
8.2.7 Port 1 Data Direction Register (P1DDR)............................................................. 333
8.2.8 Port 2 Data Direction Register (P2DDR)............................................................. 334
8.2.9 Module Stop Control Register (MSTPCR).......................................................... 334
8.3 Operation ........................................................................................................................... 335
8.3.1 Overview.............................................................................................................. 335
8.3.2 Output Timing...................................................................................................... 336
8.3.3 Normal Pulse Output............................................................................................ 337
8.3.4 Non-Overlapping Pulse Output............................................................................ 339
8.3.5 Inverted Pulse Output........................................................................................... 342
8.3.6 Pulse Output Triggered by Input Capture ............................................................ 343
8.4 Usage Notes....................................................................................................................... 344
8.4.1 Operation of Pulse Output Pins............................................................................ 344
8.4.2 Note on Non-Overlapping Output........................................................................ 344

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Section 9 8-Bit Timers ..................................................................................................... 347
9.1 Overview............................................................................................................................ 347
9.1.1 Features ................................................................................................................ 347
9.1.2 Block Diagram...................................................................................................... 348
9.1.3 Pin Configuration ................................................................................................. 349
9.1.4 Register Configuration ......................................................................................... 349
9.2 Register Descriptions......................................................................................................... 350
9.2.1 Timer Counters 0 and 1 (TCNT0, TCNT1).......................................................... 350
9.2.2 Time Constant Registers A0 and A1 (TCORA0, TCORA1)............................... 350
9.2.3 Time Constant Registers B0 and B1 (TCORB0, TCORB1)................................ 351
9.2.4 Time Control Registers 0 and 1 (TCR0, TCR1) .................................................. 351
9.2.5 Timer Control/Status Registers 0 and 1 (TCSR0, TCSR1).................................. 353
9.2.6 Module Stop Control Register (MSTPCR).......................................................... 356
9.3 Operation ........................................................................................................................... 357
9.3.1 TCNT Incrementation Timing.............................................................................. 357
9.3.2 Compare Match Timing ....................................................................................... 358
9.3.3 Timing of TCNT External Reset.......................................................................... 360
9.3.4 Timing of Overflow Flag (OVF) Setting.............................................................. 360
9.3.5 Operation with Cascaded Connection.................................................................. 361
9.4 Interrupts............................................................................................................................ 362
9.4.1 Interrupt Sources and DTC Activation................................................................. 362
9.4.2 A/D Converter Activation.................................................................................... 362
9.5 Sample Application ........................................................................................................... 363
9.6 Usage Notes....................................................................................................................... 364
9.6.1 Contention between TCNT Write and Clear........................................................ 364
9.6.2 Contention between TCNT Write and Increment ................................................ 365
9.6.3 Contention between TCOR Write and Compare Match ...................................... 366
9.6.4 Contention between Compare Matches A and B ................................................. 367
9.6.5 Switching of Internal Clocks and TCNT Operation............................................. 367
9.6.6 Interrupts and Module Stop Mode........................................................................ 369
Section 10 Watchdog Timer ............................................................................................. 371
10.1 Overview............................................................................................................................ 371
10.1.1 Features ................................................................................................................ 371
10.1.2 Block Diagram...................................................................................................... 372
10.1.3 Pin Configuration ................................................................................................. 373
10.1.4 Register Configuration ......................................................................................... 373
10.2 Register Descriptions......................................................................................................... 374
10.2.1 Timer Counter (TCNT)........................................................................................ 374
10.2.2 Timer Control/Status Register (TCSR)................................................................ 374
10.2.3 Reset Control/Status Register (RSTCSR)............................................................ 376
10.2.4 Notes on Register Access..................................................................................... 377
10.3 Operation ........................................................................................................................... 379

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10.3.1 Operation in Watchdog Timer Mode ................................................................... 379
10.3.2 Operation in Interval Timer Mode ....................................................................... 381
10.3.3 Timing of Overflow Flag (OVF) Setting.............................................................. 381
10.3.4 Timing of Watchdog Timer Overflow Flag (WOVF) Setting.............................. 382
10.4 Interrupts............................................................................................................................ 382
10.5 Usage Notes....................................................................................................................... 382
10.5.1 Contention between Timer Counter (TCNT) Write and Increment..................... 382
10.5.2 Changing Value of CKS2 to CKS0...................................................................... 383
10.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 383
10.5.4 System Reset by WDTOVF Signal*.................................................................... 384
10.5.5 Internal Reset in Watchdog Timer Mode............................................................. 384
Section 11 Serial Communication Interface (SCI) .................................................... 385
11.1 Overview............................................................................................................................ 385
11.1.1 Features ................................................................................................................ 385
11.1.2 Block Diagram...................................................................................................... 387
11.1.3 Pin Configuration ................................................................................................. 388
11.1.4 Register Configuration ......................................................................................... 389
11.2 Register Descriptions......................................................................................................... 390
11.2.1 Receive Shift Register (RSR)............................................................................... 390
11.2.2 Receive Data Register (RDR) .............................................................................. 390
11.2.3 Transmit Shift Register (TSR).............................................................................. 391
11.2.4 Transmit Data Register (TDR)............................................................................. 391
11.2.5 Serial Mode Register (SMR)................................................................................ 392
11.2.6 Serial Control Register (SCR).............................................................................. 395
11.2.7 Serial Status Register (SSR)................................................................................. 399
11.2.8 Bit Rate Register (BRR)....................................................................................... 402
11.2.9 Smart Card Mode Register (SCMR).................................................................... 410
11.2.10 Module Stop Control Register (MSTPCR).......................................................... 412
11.3 Operation ........................................................................................................................... 413
11.3.1 Overview.............................................................................................................. 413
11.3.2 Operation in Asynchronous Mode........................................................................ 415
11.3.3 Multiprocessor Communication Function............................................................ 426
11.3.4 Operation in Synchronous Mode.......................................................................... 434
11.4 SCI Interrupts .................................................................................................................... 443
11.5 Usage Notes....................................................................................................................... 445
Section 12 Smart Card Interface...................................................................................... 453
12.1 Overview............................................................................................................................ 453
12.1.1 Features ................................................................................................................ 453
12.1.2 Block Diagram...................................................................................................... 454
12.1.3 Pin Configuration ................................................................................................. 455
12.1.4 Register Configuration ......................................................................................... 456

ix
12.2 Register Descriptions......................................................................................................... 457
12.2.1 Smart Card Mode Register (SCMR).................................................................... 457
12.2.2 Serial Status Register (SSR)................................................................................. 458
12.2.3 Serial Mode Register (SMR)................................................................................ 459
12.2.4 Serial Control Register (SCR).............................................................................. 461
12.3 Operation ........................................................................................................................... 462
12.3.1 Overview.............................................................................................................. 462
12.3.2 Pin Connections.................................................................................................... 462
12.3.3 Data Format.......................................................................................................... 464
12.3.4 Register Settings................................................................................................... 466
12.3.5 Clock .................................................................................................................... 468
12.3.6 Data Transfer Operations ..................................................................................... 470
12.3.7 Operation in GSM Mode...................................................................................... 477
12.3.8 Operation in Block Transfer Mode ...................................................................... 478
12.4 Usage Notes....................................................................................................................... 479
Section 13 A/D Converter (8 Analog Input Channel Version).............................. 483
13.1 Overview............................................................................................................................ 483
13.1.1 Features ................................................................................................................ 483
13.1.2 Block Diagram...................................................................................................... 485
13.1.3 Pin Configuration ................................................................................................. 486
13.1.4 Register Configuration ......................................................................................... 487
13.2 Register Descriptions......................................................................................................... 488
13.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 488
13.2.2 A/D Control/Status Register (ADCSR)................................................................ 489
13.2.3 A/D Control Register (ADCR)............................................................................. 491
13.2.4 Module Stop Control Register (MSTPCR).......................................................... 492
13.3 Interface to Bus Master...................................................................................................... 493
13.4 Operation ........................................................................................................................... 494
13.4.1 Single Mode (SCAN = 0)..................................................................................... 494
13.4.2 Scan Mode (SCAN = 1) ....................................................................................... 496
13.4.3 Input Sampling and A/D Conversion Time.......................................................... 498
13.4.4 External Trigger Input Timing ............................................................................. 499
13.5 Interrupts............................................................................................................................ 500
13.6 Usage Notes....................................................................................................................... 501
Section 14 A/D Converter (12 Analog Input Channel Version)............................ 507
14.1 Overview............................................................................................................................ 507
14.1.1 Features ................................................................................................................ 507
14.1.2 Block Diagram...................................................................................................... 509
14.1.3 Pin Configuration ................................................................................................. 510
14.1.4 Register Configuration ......................................................................................... 511
14.2 Register Descriptions......................................................................................................... 512

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14.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 512
14.2.2 A/D Control/Status Register (ADCSR)................................................................ 513
14.2.3 A/D Control Register (ADCR)............................................................................. 515
14.2.4 Module Stop Control Register (MSTPCR).......................................................... 516
14.3 Interface to Bus Master...................................................................................................... 517
14.4 Operation ........................................................................................................................... 518
14.4.1 Single Mode (SCAN = 0)..................................................................................... 518
14.4.2 Scan Mode (SCAN = 1)........................................................................................ 520
14.4.3 Input Sampling and A/D Conversion Time.......................................................... 522
14.4.4 External Trigger Input Timing ............................................................................. 523
14.5 Interrupts............................................................................................................................ 524
14.6 Usage Notes....................................................................................................................... 525
Section 15 D/A Converter ................................................................................................. 527
15.1 Overview............................................................................................................................ 527
15.1.1 Features ................................................................................................................ 527
15.1.2 Block Diagram...................................................................................................... 528
15.1.3 Pin Configuration ................................................................................................. 529
15.1.4 Register Configuration ......................................................................................... 529
15.2 Register Descriptions......................................................................................................... 530
15.2.1 D/A Data Registers 0 to 3 (DADR0 to DADR3)................................................. 530
15.2.2 D/A Control Registers 01 and 23 (DACR01, DACR23) ..................................... 530
15.2.3 Module Stop Control Register (MSTPCR).......................................................... 532
15.3 Operation ........................................................................................................................... 533
Section 16 RAM................................................................................................................... 535
16.1 Overview............................................................................................................................ 535
16.1.1 Block Diagram...................................................................................................... 535
16.1.2 Register Configuration ......................................................................................... 536
16.2 Register Descriptions......................................................................................................... 536
16.2.1 System Control Register (SYSCR) ...................................................................... 536
16.3 Operation ........................................................................................................................... 537
16.4 Usage Note ........................................................................................................................ 537
Section 17 ROM................................................................................................................... 539
17.1 Overview............................................................................................................................ 539
17.1.1 Block Diagram...................................................................................................... 539
17.1.2 Register Configuration ......................................................................................... 540
17.2 Register Descriptions......................................................................................................... 540
17.2.1 Mode Control Register (MDCR).......................................................................... 540
17.2.2 Bus Control Register L (BCRL)........................................................................... 541
17.3 Operation ........................................................................................................................... 541
17.4 Overview of Flash Memory............................................................................................... 544

xi
17.4.1 Features ................................................................................................................ 544
17.4.2 Overview.............................................................................................................. 545
17.4.3 Flash Memory Operating Modes.......................................................................... 546
17.4.4 On-Board Programming Modes........................................................................... 547
17.4.5 Flash Memory Emulation in RAM....................................................................... 549
17.4.6 Differences between Boot Mode and User Program Mode.................................. 550
17.4.7 Block Configuration............................................................................................. 551
17.4.8 Pin Configuration ................................................................................................. 552
17.4.9 Register Configuration ......................................................................................... 553
17.5 Register Descriptions......................................................................................................... 554
17.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 554
17.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 557
17.5.3 Erase Block Register 1 (EBR1)............................................................................ 558
17.5.4 Erase Block Registers 2 (EBR2).......................................................................... 558
17.5.5 System Control Register 2 (SYSCR2) ................................................................. 559
17.5.6 RAM Emulation Register (RAMER)................................................................... 560
17.6 On-Board Programming Modes........................................................................................ 561
17.6.1 Boot Mode............................................................................................................ 562
17.6.2 User Program Mode ............................................................................................. 566
17.7 Programming/Erasing Flash Memory................................................................................ 568
17.7.1 Program Mode...................................................................................................... 568
17.7.2 Program-Verify Mode.......................................................................................... 569
17.7.3 Erase Mode........................................................................................................... 571
17.7.4 Erase-Verify Mode............................................................................................... 571
17.8 Flash Memory Protection.................................................................................................. 573
17.8.1 Hardware Protection............................................................................................. 573
17.8.2 Software Protection.............................................................................................. 573
17.8.3 Error Protection.................................................................................................... 574
17.9 Flash Memory Emulation in RAM.................................................................................... 576
17.9.1 Emulation in RAM............................................................................................... 576
17.9.2 RAM Overlap....................................................................................................... 577
17.10 Interrupt Handling when Programming/Erasing Flash Memory....................................... 578
17.11 Flash Memory PROM Mode............................................................................................. 579
17.11.1 PROM Mode Setting............................................................................................ 579
17.11.2 Socket Adapters and Memory Map...................................................................... 580
17.11.3 PROM Mode Operation ....................................................................................... 583
17.11.4 Memory Read Mode............................................................................................. 584
17.11.5 Auto-Program Mode ............................................................................................ 587
17.11.6 Auto-Erase Mode.................................................................................................. 589
17.11.7 Status Read Mode................................................................................................. 590
17.11.8 Status Polling........................................................................................................ 591
17.11.9 PROM Mode Transition Time.............................................................................. 592
17.11.10 Notes On Memory Programming....................................................................... 592

xii
17.12 Flash Memory Programming and Erasing Precautions..................................................... 593
Section 18 Clock Pulse Generator .................................................................................. 599
18.1 Overview............................................................................................................................ 599
18.1.1 Block Diagram...................................................................................................... 599
18.1.2 Register Configuration ......................................................................................... 600
18.2 Register Descriptions......................................................................................................... 600
18.2.1 System Clock Control Register (SCKCR) ........................................................... 600
18.3 Oscillator............................................................................................................................ 602
18.3.1 Connecting a Crystal Resonator........................................................................... 602
18.3.2 External Clock Input ............................................................................................ 604
18.4 Duty Adjustment Circuit.................................................................................................... 606
18.5 Medium-Speed Clock Divider........................................................................................... 606
18.6 Bus Master Clock Selection Circuit.................................................................................. 606
Section 19 Power-Down Modes...................................................................................... 607
19.1 Overview............................................................................................................................ 607
19.1.1 Register Configuration ......................................................................................... 608
19.2 Register Descriptions......................................................................................................... 609
19.2.1 Standby Control Register (SBYCR) .................................................................... 609
19.2.2 System Clock Control Register (SCKCR) ........................................................... 611
19.2.3 Module Stop Control Register (MSTPCR).......................................................... 613
19.3 Medium-Speed Mode........................................................................................................ 614
19.4 Sleep Mode........................................................................................................................ 615
19.5 Module Stop Mode............................................................................................................ 615
19.5.1 Module Stop Mode............................................................................................... 615
19.5.2 Usage Notes.......................................................................................................... 616
19.6 Software Standby Mode.................................................................................................... 617
19.6.1 Software Standby Mode....................................................................................... 617
19.6.2 Clearing Software Standby Mode ........................................................................ 617
19.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode .. 618
19.6.4 Software Standby Mode Application Example.................................................... 618
19.6.5 Usage Notes.......................................................................................................... 619
19.7 Hardware Standby Mode................................................................................................... 620
19.7.1 Hardware Standby Mode...................................................................................... 620
19.7.2 Hardware Standby Mode Timing......................................................................... 620
19.8 ø Clock Output Disabling Function................................................................................... 621
Appendix A Instruction Set.............................................................................................. 623
A.1 Instruction List................................................................................................................... 623
A.2 Instruction Codes............................................................................................................... 647
A.3 Operation Code Map.......................................................................................................... 662
A.4 Number of States Required for Instruction Execution ...................................................... 666

xiii
A.5 Bus States During Instruction Execution .......................................................................... 680
A.6 Condition Code Modification............................................................................................ 694
Appendix B Internal I/O Registers................................................................................ 700
B.1 Addresses........................................................................................................................... 700

1
Section 1 Overview
1.1 Overview
The H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series are series of microcomputers
(MCUs: microcomputer units), built around the H8S/2000 CPU, employing Hitachi's proprietary
architecture, and equipped with supporting functions on-chip.
The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general
registers and a concise, optimized instruction set designed for high-speed operation, and can
address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300
and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300,
H8/300L, or H8/300H Series.
On-chip supporting functions required for system configuration include DMA controller (DMAC)
and data transfer controller (DTC) bus masters, ROM and RAM memory, a 16-bit timer-pulse unit
(TPU), programmable pulse generator (PPG), 8-bit timer, watchdog timer (WDT), serial
communication interface (SCI), A/D converter, D/A converter, and I/O ports.
A high-functionality bus controller is also provided, enabling fast and easy connection of DRAM
and other kinds of memory.
Single-power-supply flash memory (F-ZTAT™*) and mask ROM versions are available,
providing a quick and flexible response to conditions from ramp-up through full-scale volume
production, even for applications with frequently changing specifications. ROM is connected to
the CPU via a 16-bit data bus, enabling both byte and word data to be accessed in one state.
Instruction fetching is thus speeded up, and processing speed increased.
The features of the H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series are shown in table
1-1.
Note: * F-ZTAT is a trademark of Hitachi, Ltd.

2
Table 1-1 Overview
Item Specification
CPU • General-register machine
 Sixteen 16-bit general registers (also usable as sixteen 8-bit registers
or eight 32-bit registers)
• High-speed operation suitable for realtime control
 Maximum clock rate: 20 MHz (25 MHz version in planning stage)
 High-speed arithmetic operations
8/16/32-bit register-register add/subtract: 50 ns (at 20 MHz operation)
16 ×16-bit register-register multiply: 1000 ns (at 20 MHz operation)
32 ÷16-bit register-register divide: 1000 ns (at 20 MHz operation)
• Instruction set suitable for high-speed operation
 Sixty-five basic instructions
 8/16/32-bit move/arithmetic and logic instructions
 Unsigned/signed multiply and divide instructions
 Powerful bit-manipulation instructions
• CPU operating mode
 Advanced mode: 16-Mbyte address space
Bus controller • Address space divided into 8 areas, with bus specifications settable
independently for each area
• Chip select output possible for each area
• Choice of 8-bit or 16-bit access space for each area
• 2-state or 3-state access space can be designated for each area
• Number of program wait states can be set for each area
• Burst ROM directly connectable
• Maximum 8-Mbyte DRAM directly connectable (or use of interval timer
possible)
• External bus release function
DMA controller
(DMAC) • Choice of short address mode or full address mode
• 4 channels in short address mode
• 2 channels in full address mode
• Transfer possible in repeat mode, block transfer mode, etc.
• Single address mode transfer possible
• Can be activated by internal interrupt
Data transfer
controller (DTC) • Can be activated by internal interrupt or software
• Multiple transfers or multiple types of transfer possible for one activation
source
• Transfer possible in repeat mode, block transfer mode, etc.
• Request can be sent to CPU for interrupt that activated DTC

3
Table 1-1 Overview (cont)
Item Specification
16-bit timer-pulse
unit (TPU) • 6-channel 16-bit timer
• Pulse I/O processing capability for up to 16 pins
• Automatic 2-phase encoder count capability
Programmable
pulse generator
(PPG)
• Maximum 16-bit pulse output possible with TPU as time base
• Output trigger selectable in 4-bit groups
• Non-overlap margin can be set
• Direct output or inverse output setting possible
8-bit timer,
2 channels • 8-bit up-counter (external event count capability)
• Two time constant registers
• Two-channel connection possible
Watchdog timer • Watchdog timer or interval timer selectable
Serial
communication
interface (SCI),
3 channels
• Asynchronous mode or synchronous mode selectable
• Multiprocessor communication function
• Smart card interface function
A/D converter • Resolution: 10 bits
• Input: 8 or 12 channels
• High-speed conversion: 6.7 µs minimum conversion time
(at 20 MHz operation)
• Single or scan mode selectable
• Sample-and-hold circuit
• A/D conversion can be activated by external trigger or timer trigger
D/A converter • Resolution: 8 bits
• Output: 2 to 4 channels
Memory • Flash memory, mask ROM
• High-speed static RAM
Interrupt controller • Eight priority levels settable
Power-down state • Medium-speed mode
• Sleep mode
• Module stop mode
• Software standby mode
• Hardware standby mode
• Variable clock division ratio