Hitachi H8/3035 Series User manual

Hitachi Single-Chip Microcomputer
H8/3035 Series
H8/3035, H8/3034, H8/3033
Hardware Manual

Notice
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the
whole or part of this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from
accidents or any other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the
characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no
responsibility for any intellectual property claims or other problems that may result from
applications based on the examples described herein.
5. No license is granted by implication or otherwise under any patents or other rights of any
third party or Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales
company. Such use includes, but is not limited to, use in life support systems. Buyers of
Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to
use the products in MEDICAL APPLICATIONS.

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Contents
Contents..... .....................................................................................................i
Preface....... .....................................................................................................1
Section 1 Overview........................................................................................3
1.1 Overview ........................................................................................................................3
1.2 Block Diagram................................................................................................................7
1.3 Pin Description ...............................................................................................................8
1.3.1 Pin Arrangement................................................................................................8
1.3.2 Pin Functions.....................................................................................................9
1.4 Pin Functions..................................................................................................................12
Section 2 CPU................................................................................................17
2.1 Overview ........................................................................................................................17
2.1.1 Features.............................................................................................................17
2.1.2 Differences from H8/300 CPU...........................................................................18
2.2 CPU Operating Modes....................................................................................................18
2.3 Address Space.................................................................................................................19
2.4 Register Configuration....................................................................................................20
2.4.1 Overview...........................................................................................................20
2.4.2 General Registers...............................................................................................21
2.4.3 Control Registers...............................................................................................22
2.4.4 Initial CPU Register Values...............................................................................23
2.5 Data Formats...................................................................................................................23
2.5.1 General Register Data Formats ..........................................................................24
2.5.2 Memory Data Formats.......................................................................................26
2.6 Instruction Set.................................................................................................................27
2.6.1 Instruction Set Overview....................................................................................27
2.6.2 Instructions and Addressing Modes....................................................................28
2.6.3 Tables of Instructions Classified by Function.....................................................29
2.6.4 Basic Instruction Formats ..................................................................................38
2.6.5 Notes on Use of Bit Manipulation Instructions...................................................39
2.7 Addressing Modes and Effective Address Calculation.....................................................39
2.7.1 Addressing Modes .............................................................................................39
2.7.2 Effective Address Calculation............................................................................42
2.8 Processing States.............................................................................................................46
2.8.1 Overview...........................................................................................................46
2.8.2 Program Execution State....................................................................................47
2.8.3 Exception-Handling State ..................................................................................47

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2.8.4 Exception-Handling Sequences..........................................................................48
2.8.5 Reset State.........................................................................................................49
2.8.6 Power-Down State.............................................................................................49
2.9 Basic Operational Timing............................................................................................... 50
2.9.1 Overview...........................................................................................................50
2.9.2 On-Chip Memory Access Timing ......................................................................50
2.9.3 On-Chip Supporting Module Access Timing...................................................... 51
2.9.4 Access to External Address Space......................................................................52
Section 3 MCU Operating Modes ..................................................................53
3.1 Overview........................................................................................................................ 53
3.1.1 Operating Mode Selection .................................................................................53
3.1.2 Register Configuration.......................................................................................53
3.2 Mode Control Register (MDCR).....................................................................................54
3.3 System Control Register (SYSCR).................................................................................. 55
3.4 Operating Mode Descriptions..........................................................................................57
3.4.1 Mode 1 .............................................................................................................. 57
3.4.2 Mode 2 .............................................................................................................. 57
3.4.3 Mode 3 .............................................................................................................. 57
3.5 Pin Functions in Each Operating Mode...........................................................................57
3.6 Memory Map in Each Operating Mode...........................................................................58
Section 4 Exception Handling........................................................................61
4.1 Overview........................................................................................................................ 61
4.1.1 Exception Handling Types and Priority..............................................................61
4.1.2 Exception Handling Operation........................................................................... 61
4.1.3 Exception Vector Table..................................................................................... 62
4.2 Reset...............................................................................................................................63
4.2.1 Overview...........................................................................................................63
4.2.2 Reset Sequence.................................................................................................. 63
4.2.3 Interrupts after Reset..........................................................................................64
4.3 Interrupts ........................................................................................................................64
4.4 Trap Instruction ..............................................................................................................65
4.5 Stack Status after Exception Handling ............................................................................66
4.6 Notes on Stack Usage .....................................................................................................66
Section 5 Interrupt Controller ........................................................................69
5.1 Overview........................................................................................................................ 69
5.1.1 Features.............................................................................................................69
5.1.2 Block Diagram .................................................................................................. 70
5.1.3 Pin Configuration .............................................................................................. 71
5.1.4 Register Configuration.......................................................................................71

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5.2 Register Descriptions......................................................................................................72
5.2.1 System Control Register (SYSCR).....................................................................72
5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB)............................................74
5.2.3 IRQ Status Register (ISR)..................................................................................79
5.2.4 IRQ Enable Register (IER) ................................................................................80
5.2.5 IRQ Sense Control Register (ISCR)...................................................................80
5.3 Interrupt Sources.............................................................................................................81
5.3.1 External Interrupts.............................................................................................81
5.3.2 Internal Interrupts ..............................................................................................82
5.3.3 Interrupt Vector Table .......................................................................................83
5.4 Interrupt Operation..........................................................................................................85
5.4.1 Interrupt Handling Process.................................................................................85
5.4.2 Interrupt Sequence.............................................................................................91
5.4.3 Interrupt Response Time....................................................................................92
5.5 Usage Notes....................................................................................................................92
5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction......................92
5.5.2 Instructions that Inhibit Interrupts......................................................................93
5.5.3 Interrupts during EEPMOV Instruction Execution .............................................94
5.5.4 Usage Notes.......................................................................................................94
Section 6 Bus Controller ................................................................................97
6.1 Overview ........................................................................................................................97
6.1.1 Features.............................................................................................................97
6.1.2 Block Diagram...................................................................................................98
6.1.3 Input/Output Pins...............................................................................................98
6.1.4 Register Configuration.......................................................................................99
6.2 Register Descriptions......................................................................................................99
6.2.1 Access State Control Register (ASTCR)............................................................99
6.2.2 Wait Control Register (WCR)............................................................................100
6.2.3 Wait State Controller Enable Register (WCER).................................................101
6.2.4 Address Control Register (ADRCR)...................................................................102
6.3 Operation........................................................................................................................104
6.3.1 Area Division.....................................................................................................104
6.3.2 Bus Control Signal Timing ................................................................................106
6.3.3 Wait Modes .......................................................................................................108
6.3.4 Interconnections with Memory (Example) .........................................................114
6.4 Usage Notes....................................................................................................................116
6.4.1 Register Write Timing.......................................................................................116
6.4.2 Precautions on setting ASTCR and ABWCR* ...................................................116

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Section 7 I/O Ports.........................................................................................117
7.1 Overview........................................................................................................................ 117
7.2 Port 1..............................................................................................................................120
7.2.1 Overview...........................................................................................................120
7.2.2 Register Descriptions......................................................................................... 120
7.2.3 Pin Functions in Each Mode.............................................................................. 122
7.3 Port 2..............................................................................................................................123
7.3.1 Overview...........................................................................................................123
7.3.2 Register Descriptions......................................................................................... 123
7.3.3 Pin Functions in Each Mode.............................................................................. 125
7.3.4 Input Pull-Up Transistors................................................................................... 126
7.4 Port 3..............................................................................................................................127
7.4.1 Overview...........................................................................................................127
7.4.2 Register Descriptions......................................................................................... 127
7.4.3 Pin Functions in Each Mode.............................................................................. 129
7.5 Port 5..............................................................................................................................130
7.5.1 Overview...........................................................................................................130
7.5.2 Register Descriptions......................................................................................... 130
7.5.3 Pin Functions in Each Mode.............................................................................. 132
7.5.4 Input Pull-Up Transistors................................................................................... 133
7.6 Port 6..............................................................................................................................134
7.6.1 Overview...........................................................................................................134
7.6.2 Register Descriptions......................................................................................... 134
7.6.3 Pin Functions in Each Mode.............................................................................. 136
7.7 Port 7..............................................................................................................................138
7.7.1 Overview...........................................................................................................138
7.7.2 Register Description ..........................................................................................139
7.8 Port 8..............................................................................................................................139
7.8.1 Overview...........................................................................................................139
7.8.2 Register Descriptions......................................................................................... 140
7.8.3 Pin Functions..................................................................................................... 142
7.9 Port 9..............................................................................................................................143
7.9.1 Overview...........................................................................................................143
7.9.2 Register Descriptions......................................................................................... 143
7.9.3 Pin Functions..................................................................................................... 145
7.10 Port A ........................................................................................................................... 146
7.10.1 Overview.........................................................................................................146
7.10.2 Register Descriptions.......................................................................................147
7.10.3 Pin Functions...................................................................................................149
7.11 Port B ........................................................................................................................... 153
7.11.1 Overview.........................................................................................................153
7.11.2 Register Descriptions.......................................................................................154

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7.11.3 Pin Functions...................................................................................................156
Section 8 16-Bit Integrated Timer Unit (ITU) ................................................161
8.1 Overview ........................................................................................................................161
8.1.1 Features.............................................................................................................161
8.1.2 Block Diagrams.................................................................................................164
8.1.3 Input/Output Pins...............................................................................................169
8.1.4 Register Configuration.......................................................................................170
8.2 Register Descriptions......................................................................................................172
8.2.1 Timer Start Register (TSTR)..............................................................................172
8.2.2 Timer Synchro Register (TSNC)........................................................................174
8.2.3 Timer Mode Register (TMDR) ..........................................................................176
8.2.4 Timer Function Control Register (TFCR) ..........................................................179
8.2.5 Timer Output Master Enable Register (TOER) ..................................................181
8.2.6 Timer Output Control Register (TOCR).............................................................183
8.2.7 Timer Counters (TCNT) ....................................................................................184
8.2.8 General Registers (GRA, GRB) .........................................................................185
8.2.9 Buffer Registers (BRA, BRB)............................................................................186
8.2.10 Timer Control Registers (TCR)........................................................................187
8.2.11 Timer I/O Control Register (TIOR)..................................................................189
8.2.12 Timer Status Register (TSR)............................................................................191
8.2.13 Timer Interrupt Enable Register (TIER)...........................................................193
8.3 CPU Interface .................................................................................................................195
8.3.1 16-Bit Accessible Registers ...............................................................................195
8.3.2 8-Bit Accessible Registers .................................................................................197
8.4 Operation........................................................................................................................198
8.4.1 Overview...........................................................................................................198
8.4.2 Basic Functions..................................................................................................200
8.4.3 Synchronization.................................................................................................207
8.4.4 PWM Mode.......................................................................................................209
8.4.5 Reset-Synchronized PWM Mode.......................................................................213
8.4.6 Complementary PWM Mode .............................................................................215
8.4.7 Phase Counting Mode........................................................................................224
8.4.8 Buffering ...........................................................................................................227
8.4.9 ITU Output Timing............................................................................................232
8.5 Interrupts ........................................................................................................................234
8.5.1 Setting of Status Flags .......................................................................................234
8.5.2 Clearing of Status Flags.....................................................................................236
8.5.3 Interrupt Sources................................................................................................237
8.6 Usage Notes....................................................................................................................238

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Section 9 Programmable Timing Pattern Controller.......................................253
9.1 Overview........................................................................................................................ 253
9.1.1 Features.............................................................................................................253
9.1.2 Block Diagram .................................................................................................. 254
9.1.3 TPC Pins............................................................................................................255
9.1.4 Registers............................................................................................................ 256
9.2 Register Descriptions......................................................................................................257
9.2.1 Port A Data Direction Register (PADDR)..........................................................257
9.2.2 Port A Data Register (PADR)............................................................................ 257
9.2.3 Port B Data Direction Register (PBDDR) ..........................................................258
9.2.4 Port B Data Register (PBDR)............................................................................. 258
9.2.5 Next Data Register A (NDRA)...........................................................................259
9.2.6 Next Data Register B (NDRB)........................................................................... 261
9.2.7 Next Data Enable Register A (NDERA) ............................................................263
9.2.8 Next Data Enable Register B (NDERB)............................................................. 264
9.2.9 TPC Output Control Register (TPCR)................................................................ 265
9.2.10 TPC Output Mode Register (TPMR)................................................................ 267
9.3 Operation........................................................................................................................ 269
9.3.1 Overview...........................................................................................................269
9.3.2 Output Timing...................................................................................................270
9.3.3 Normal TPC Output...........................................................................................271
9.3.4 Non-Overlapping TPC Output ........................................................................... 273
9.3.5 TPC Output Triggering by Input Capture........................................................... 275
9.4 Usage Notes.................................................................................................................... 275
9.4.1 Operation of TPC Output Pins ...........................................................................275
9.4.2 Note on Non-Overlapping Output...................................................................... 275
Section 10 Watchdog Timer...........................................................................277
10.1 Overview ...................................................................................................................... 277
10.1.1 Features........................................................................................................... 277
10.1.2 Block Diagram.................................................................................................278
10.1.3 Pin Configuration.............................................................................................278
10.1.4 Register Configuration..................................................................................... 279
10.2 Register Descriptions.................................................................................................... 279
10.2.1 Timer Counter (TCNT)....................................................................................279
10.2.2 Timer Control/Status Register (TCSR)............................................................. 280
10.2.3 Reset Control/Status Register (RSTCSR)......................................................... 282
10.2.4 Notes on Register Access................................................................................. 283
10.3 Operation......................................................................................................................284
10.3.1 Watchdog Timer Operation..............................................................................284
10.3.2 Interval Timer Operation .................................................................................285
10.3.3 Timing of Setting of Overflow Flag (OVF)......................................................286

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10.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST)................................286
10.4 Interrupts.......................................................................................................................287
10.5 Usage Notes..................................................................................................................287
Section 11 Serial Communication Interface....................................................289
11.1 Overview ......................................................................................................................289
11.1.1 Features ...........................................................................................................289
11.1.2 Block Diagram.................................................................................................290
11.1.3 Input/Output Pins.............................................................................................291
11.1.4 Register Configuration.....................................................................................291
11.2 Register Descriptions ....................................................................................................292
11.2.1 Receive Shift Register (RSR)...........................................................................292
11.2.2 Receive Data Register (RDR) ..........................................................................292
11.2.3 Transmit Shift Register (TSR)..........................................................................293
11.2.4 Transmit Data Register (TDR).........................................................................293
11.2.5 Serial Mode Register (SMR)............................................................................294
11.2.6 Serial Control Register (SCR)..........................................................................297
11.2.7 Serial Status Register (SSR).............................................................................301
11.2.8 Bit Rate Register (BRR) ..................................................................................305
11.3 Operation......................................................................................................................313
11.3.1 Overview.........................................................................................................313
11.3.2 Operation in Asynchronous Mode....................................................................315
11.3.3 Multiprocessor Communication .......................................................................325
11.3.4 Synchronous Operation....................................................................................332
11.4 SCI Interrupts................................................................................................................340
11.5 Usage Notes..................................................................................................................340
Section 12 A/D Converter ..............................................................................345
12.1 Overview ......................................................................................................................345
12.1.1 Features ...........................................................................................................345
12.1.2 Block Diagram.................................................................................................346
12.1.3 Input Pins.........................................................................................................347
12.1.4 Register Configuration.....................................................................................348
12.2 Register Descriptions ....................................................................................................348
12.2.1 A/D Data Registers A to D (ADDRA to ADDRD)...........................................348
12.2.2 A/D Control/Status Register (ADCSR).............................................................350
12.2.3 A/D Control Register (ADCR).........................................................................352
12.3 CPU Interface ...............................................................................................................353
12.4 Operation......................................................................................................................354
12.4.1 Single Mode (SCAN = 0).................................................................................355
12.4.2 Scan Mode (SCAN = 1)...................................................................................357
12.4.3 Input Sampling and A/D Conversion Time.......................................................359
12.4.4 External Trigger Input Timing.........................................................................360

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12.5 Interrupts ......................................................................................................................361
12.6 Usage Notes.................................................................................................................. 361
Section 13 RAM............................................................................................363
13.1 Overview ...................................................................................................................... 363
13.1.1 Block Diagram.................................................................................................363
13.1.2 Register Configuration..................................................................................... 364
13.2 System Control Register (SYSCR)................................................................................364
13.3 Operation......................................................................................................................365
13.3.1 Mode 1 ............................................................................................................365
13.3.2 Mode 2 .............................................................................................................365
13.3.3 Mode 3 .............................................................................................................365
Section 14 ROM............................................................................................367
14.1 Overview ...................................................................................................................... 367
14.1.1 Block Diagram.................................................................................................367
14.2 PROM Mode.................................................................................................................368
14.2.1 PROM Mode Setting........................................................................................368
14.2.2 Socket Adapter and Memory Map.................................................................... 368
14.3 Programming ................................................................................................................ 370
14.3.1 Programming and Verification......................................................................... 371
14.3.2 Programming Precautions................................................................................ 374
14.4 Reliability of Programmed Data....................................................................................375
Section 15 Clock Pulse Generator..................................................................377
15.1 Overview ...................................................................................................................... 377
15.1.1 Block Diagram.................................................................................................377
15.2 Oscillator Circuit .......................................................................................................... 377
15.2.1 Connecting a Crystal Resonator.......................................................................378
15.2.2 External Clock Input........................................................................................380
15.3 Duty Adjustment Circuit...............................................................................................382
15.4 Prescalers...................................................................................................................... 382
Section 16 Power-Down State........................................................................383
16.1 Overview ...................................................................................................................... 383
16.2 Register Configuration..................................................................................................384
16.2.1 System Control Register (SYSCR)................................................................... 384
16.3 Sleep Mode................................................................................................................... 385
16.3.1 Transition to Sleep Mode................................................................................. 385
16.3.2 Exit from Sleep Mode......................................................................................386
16.4 Software Standby Mode................................................................................................386
16.4.1 Transition to Software Standby Mode..............................................................386
16.4.2 Exit from Software Standby Mode...................................................................386