Hitachi H8/3035 Series User manual

Hitachi Single-Chip Microcomputer
H8/3035 Series
H8/3035, H8/3034, H8/3033
Hardware Manual

Notice
When using this document, keep the following in mind:
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whole or part of this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from
accidents or any other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the
characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no
responsibility for any intellectual property claims or other problems that may result from
applications based on the examples described herein.
5. No license is granted by implication or otherwise under any patents or other rights of any
third party or Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales
company. Such use includes, but is not limited to, use in life support systems. Buyers of
Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to
use the products in MEDICAL APPLICATIONS.

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Contents
Contents..... .....................................................................................................i
Preface....... .....................................................................................................1
Section 1 Overview........................................................................................3
1.1 Overview ........................................................................................................................3
1.2 Block Diagram................................................................................................................7
1.3 Pin Description ...............................................................................................................8
1.3.1 Pin Arrangement................................................................................................8
1.3.2 Pin Functions.....................................................................................................9
1.4 Pin Functions..................................................................................................................12
Section 2 CPU................................................................................................17
2.1 Overview ........................................................................................................................17
2.1.1 Features.............................................................................................................17
2.1.2 Differences from H8/300 CPU...........................................................................18
2.2 CPU Operating Modes....................................................................................................18
2.3 Address Space.................................................................................................................19
2.4 Register Configuration....................................................................................................20
2.4.1 Overview...........................................................................................................20
2.4.2 General Registers...............................................................................................21
2.4.3 Control Registers...............................................................................................22
2.4.4 Initial CPU Register Values...............................................................................23
2.5 Data Formats...................................................................................................................23
2.5.1 General Register Data Formats ..........................................................................24
2.5.2 Memory Data Formats.......................................................................................26
2.6 Instruction Set.................................................................................................................27
2.6.1 Instruction Set Overview....................................................................................27
2.6.2 Instructions and Addressing Modes....................................................................28
2.6.3 Tables of Instructions Classified by Function.....................................................29
2.6.4 Basic Instruction Formats ..................................................................................38
2.6.5 Notes on Use of Bit Manipulation Instructions...................................................39
2.7 Addressing Modes and Effective Address Calculation.....................................................39
2.7.1 Addressing Modes .............................................................................................39
2.7.2 Effective Address Calculation............................................................................42
2.8 Processing States.............................................................................................................46
2.8.1 Overview...........................................................................................................46
2.8.2 Program Execution State....................................................................................47
2.8.3 Exception-Handling State ..................................................................................47

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2.8.4 Exception-Handling Sequences..........................................................................48
2.8.5 Reset State.........................................................................................................49
2.8.6 Power-Down State.............................................................................................49
2.9 Basic Operational Timing............................................................................................... 50
2.9.1 Overview...........................................................................................................50
2.9.2 On-Chip Memory Access Timing ......................................................................50
2.9.3 On-Chip Supporting Module Access Timing...................................................... 51
2.9.4 Access to External Address Space......................................................................52
Section 3 MCU Operating Modes ..................................................................53
3.1 Overview........................................................................................................................ 53
3.1.1 Operating Mode Selection .................................................................................53
3.1.2 Register Configuration.......................................................................................53
3.2 Mode Control Register (MDCR).....................................................................................54
3.3 System Control Register (SYSCR).................................................................................. 55
3.4 Operating Mode Descriptions..........................................................................................57
3.4.1 Mode 1 .............................................................................................................. 57
3.4.2 Mode 2 .............................................................................................................. 57
3.4.3 Mode 3 .............................................................................................................. 57
3.5 Pin Functions in Each Operating Mode...........................................................................57
3.6 Memory Map in Each Operating Mode...........................................................................58
Section 4 Exception Handling........................................................................61
4.1 Overview........................................................................................................................ 61
4.1.1 Exception Handling Types and Priority..............................................................61
4.1.2 Exception Handling Operation........................................................................... 61
4.1.3 Exception Vector Table..................................................................................... 62
4.2 Reset...............................................................................................................................63
4.2.1 Overview...........................................................................................................63
4.2.2 Reset Sequence.................................................................................................. 63
4.2.3 Interrupts after Reset..........................................................................................64
4.3 Interrupts ........................................................................................................................64
4.4 Trap Instruction ..............................................................................................................65
4.5 Stack Status after Exception Handling ............................................................................66
4.6 Notes on Stack Usage .....................................................................................................66
Section 5 Interrupt Controller ........................................................................69
5.1 Overview........................................................................................................................ 69
5.1.1 Features.............................................................................................................69
5.1.2 Block Diagram .................................................................................................. 70
5.1.3 Pin Configuration .............................................................................................. 71
5.1.4 Register Configuration.......................................................................................71

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5.2 Register Descriptions......................................................................................................72
5.2.1 System Control Register (SYSCR).....................................................................72
5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB)............................................74
5.2.3 IRQ Status Register (ISR)..................................................................................79
5.2.4 IRQ Enable Register (IER) ................................................................................80
5.2.5 IRQ Sense Control Register (ISCR)...................................................................80
5.3 Interrupt Sources.............................................................................................................81
5.3.1 External Interrupts.............................................................................................81
5.3.2 Internal Interrupts ..............................................................................................82
5.3.3 Interrupt Vector Table .......................................................................................83
5.4 Interrupt Operation..........................................................................................................85
5.4.1 Interrupt Handling Process.................................................................................85
5.4.2 Interrupt Sequence.............................................................................................91
5.4.3 Interrupt Response Time....................................................................................92
5.5 Usage Notes....................................................................................................................92
5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction......................92
5.5.2 Instructions that Inhibit Interrupts......................................................................93
5.5.3 Interrupts during EEPMOV Instruction Execution .............................................94
5.5.4 Usage Notes.......................................................................................................94
Section 6 Bus Controller ................................................................................97
6.1 Overview ........................................................................................................................97
6.1.1 Features.............................................................................................................97
6.1.2 Block Diagram...................................................................................................98
6.1.3 Input/Output Pins...............................................................................................98
6.1.4 Register Configuration.......................................................................................99
6.2 Register Descriptions......................................................................................................99
6.2.1 Access State Control Register (ASTCR)............................................................99
6.2.2 Wait Control Register (WCR)............................................................................100
6.2.3 Wait State Controller Enable Register (WCER).................................................101
6.2.4 Address Control Register (ADRCR)...................................................................102
6.3 Operation........................................................................................................................104
6.3.1 Area Division.....................................................................................................104
6.3.2 Bus Control Signal Timing ................................................................................106
6.3.3 Wait Modes .......................................................................................................108
6.3.4 Interconnections with Memory (Example) .........................................................114
6.4 Usage Notes....................................................................................................................116
6.4.1 Register Write Timing.......................................................................................116
6.4.2 Precautions on setting ASTCR and ABWCR* ...................................................116

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Section 7 I/O Ports.........................................................................................117
7.1 Overview........................................................................................................................ 117
7.2 Port 1..............................................................................................................................120
7.2.1 Overview...........................................................................................................120
7.2.2 Register Descriptions......................................................................................... 120
7.2.3 Pin Functions in Each Mode.............................................................................. 122
7.3 Port 2..............................................................................................................................123
7.3.1 Overview...........................................................................................................123
7.3.2 Register Descriptions......................................................................................... 123
7.3.3 Pin Functions in Each Mode.............................................................................. 125
7.3.4 Input Pull-Up Transistors................................................................................... 126
7.4 Port 3..............................................................................................................................127
7.4.1 Overview...........................................................................................................127
7.4.2 Register Descriptions......................................................................................... 127
7.4.3 Pin Functions in Each Mode.............................................................................. 129
7.5 Port 5..............................................................................................................................130
7.5.1 Overview...........................................................................................................130
7.5.2 Register Descriptions......................................................................................... 130
7.5.3 Pin Functions in Each Mode.............................................................................. 132
7.5.4 Input Pull-Up Transistors................................................................................... 133
7.6 Port 6..............................................................................................................................134
7.6.1 Overview...........................................................................................................134
7.6.2 Register Descriptions......................................................................................... 134
7.6.3 Pin Functions in Each Mode.............................................................................. 136
7.7 Port 7..............................................................................................................................138
7.7.1 Overview...........................................................................................................138
7.7.2 Register Description ..........................................................................................139
7.8 Port 8..............................................................................................................................139
7.8.1 Overview...........................................................................................................139
7.8.2 Register Descriptions......................................................................................... 140
7.8.3 Pin Functions..................................................................................................... 142
7.9 Port 9..............................................................................................................................143
7.9.1 Overview...........................................................................................................143
7.9.2 Register Descriptions......................................................................................... 143
7.9.3 Pin Functions..................................................................................................... 145
7.10 Port A ........................................................................................................................... 146
7.10.1 Overview.........................................................................................................146
7.10.2 Register Descriptions.......................................................................................147
7.10.3 Pin Functions...................................................................................................149
7.11 Port B ........................................................................................................................... 153
7.11.1 Overview.........................................................................................................153
7.11.2 Register Descriptions.......................................................................................154

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7.11.3 Pin Functions...................................................................................................156
Section 8 16-Bit Integrated Timer Unit (ITU) ................................................161
8.1 Overview ........................................................................................................................161
8.1.1 Features.............................................................................................................161
8.1.2 Block Diagrams.................................................................................................164
8.1.3 Input/Output Pins...............................................................................................169
8.1.4 Register Configuration.......................................................................................170
8.2 Register Descriptions......................................................................................................172
8.2.1 Timer Start Register (TSTR)..............................................................................172
8.2.2 Timer Synchro Register (TSNC)........................................................................174
8.2.3 Timer Mode Register (TMDR) ..........................................................................176
8.2.4 Timer Function Control Register (TFCR) ..........................................................179
8.2.5 Timer Output Master Enable Register (TOER) ..................................................181
8.2.6 Timer Output Control Register (TOCR).............................................................183
8.2.7 Timer Counters (TCNT) ....................................................................................184
8.2.8 General Registers (GRA, GRB) .........................................................................185
8.2.9 Buffer Registers (BRA, BRB)............................................................................186
8.2.10 Timer Control Registers (TCR)........................................................................187
8.2.11 Timer I/O Control Register (TIOR)..................................................................189
8.2.12 Timer Status Register (TSR)............................................................................191
8.2.13 Timer Interrupt Enable Register (TIER)...........................................................193
8.3 CPU Interface .................................................................................................................195
8.3.1 16-Bit Accessible Registers ...............................................................................195
8.3.2 8-Bit Accessible Registers .................................................................................197
8.4 Operation........................................................................................................................198
8.4.1 Overview...........................................................................................................198
8.4.2 Basic Functions..................................................................................................200
8.4.3 Synchronization.................................................................................................207
8.4.4 PWM Mode.......................................................................................................209
8.4.5 Reset-Synchronized PWM Mode.......................................................................213
8.4.6 Complementary PWM Mode .............................................................................215
8.4.7 Phase Counting Mode........................................................................................224
8.4.8 Buffering ...........................................................................................................227
8.4.9 ITU Output Timing............................................................................................232
8.5 Interrupts ........................................................................................................................234
8.5.1 Setting of Status Flags .......................................................................................234
8.5.2 Clearing of Status Flags.....................................................................................236
8.5.3 Interrupt Sources................................................................................................237
8.6 Usage Notes....................................................................................................................238

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Section 9 Programmable Timing Pattern Controller.......................................253
9.1 Overview........................................................................................................................ 253
9.1.1 Features.............................................................................................................253
9.1.2 Block Diagram .................................................................................................. 254
9.1.3 TPC Pins............................................................................................................255
9.1.4 Registers............................................................................................................ 256
9.2 Register Descriptions......................................................................................................257
9.2.1 Port A Data Direction Register (PADDR)..........................................................257
9.2.2 Port A Data Register (PADR)............................................................................ 257
9.2.3 Port B Data Direction Register (PBDDR) ..........................................................258
9.2.4 Port B Data Register (PBDR)............................................................................. 258
9.2.5 Next Data Register A (NDRA)...........................................................................259
9.2.6 Next Data Register B (NDRB)........................................................................... 261
9.2.7 Next Data Enable Register A (NDERA) ............................................................263
9.2.8 Next Data Enable Register B (NDERB)............................................................. 264
9.2.9 TPC Output Control Register (TPCR)................................................................ 265
9.2.10 TPC Output Mode Register (TPMR)................................................................ 267
9.3 Operation........................................................................................................................ 269
9.3.1 Overview...........................................................................................................269
9.3.2 Output Timing...................................................................................................270
9.3.3 Normal TPC Output...........................................................................................271
9.3.4 Non-Overlapping TPC Output ........................................................................... 273
9.3.5 TPC Output Triggering by Input Capture........................................................... 275
9.4 Usage Notes.................................................................................................................... 275
9.4.1 Operation of TPC Output Pins ...........................................................................275
9.4.2 Note on Non-Overlapping Output...................................................................... 275
Section 10 Watchdog Timer...........................................................................277
10.1 Overview ...................................................................................................................... 277
10.1.1 Features........................................................................................................... 277
10.1.2 Block Diagram.................................................................................................278
10.1.3 Pin Configuration.............................................................................................278
10.1.4 Register Configuration..................................................................................... 279
10.2 Register Descriptions.................................................................................................... 279
10.2.1 Timer Counter (TCNT)....................................................................................279
10.2.2 Timer Control/Status Register (TCSR)............................................................. 280
10.2.3 Reset Control/Status Register (RSTCSR)......................................................... 282
10.2.4 Notes on Register Access................................................................................. 283
10.3 Operation......................................................................................................................284
10.3.1 Watchdog Timer Operation..............................................................................284
10.3.2 Interval Timer Operation .................................................................................285
10.3.3 Timing of Setting of Overflow Flag (OVF)......................................................286

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10.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST)................................286
10.4 Interrupts.......................................................................................................................287
10.5 Usage Notes..................................................................................................................287
Section 11 Serial Communication Interface....................................................289
11.1 Overview ......................................................................................................................289
11.1.1 Features ...........................................................................................................289
11.1.2 Block Diagram.................................................................................................290
11.1.3 Input/Output Pins.............................................................................................291
11.1.4 Register Configuration.....................................................................................291
11.2 Register Descriptions ....................................................................................................292
11.2.1 Receive Shift Register (RSR)...........................................................................292
11.2.2 Receive Data Register (RDR) ..........................................................................292
11.2.3 Transmit Shift Register (TSR)..........................................................................293
11.2.4 Transmit Data Register (TDR).........................................................................293
11.2.5 Serial Mode Register (SMR)............................................................................294
11.2.6 Serial Control Register (SCR)..........................................................................297
11.2.7 Serial Status Register (SSR).............................................................................301
11.2.8 Bit Rate Register (BRR) ..................................................................................305
11.3 Operation......................................................................................................................313
11.3.1 Overview.........................................................................................................313
11.3.2 Operation in Asynchronous Mode....................................................................315
11.3.3 Multiprocessor Communication .......................................................................325
11.3.4 Synchronous Operation....................................................................................332
11.4 SCI Interrupts................................................................................................................340
11.5 Usage Notes..................................................................................................................340
Section 12 A/D Converter ..............................................................................345
12.1 Overview ......................................................................................................................345
12.1.1 Features ...........................................................................................................345
12.1.2 Block Diagram.................................................................................................346
12.1.3 Input Pins.........................................................................................................347
12.1.4 Register Configuration.....................................................................................348
12.2 Register Descriptions ....................................................................................................348
12.2.1 A/D Data Registers A to D (ADDRA to ADDRD)...........................................348
12.2.2 A/D Control/Status Register (ADCSR).............................................................350
12.2.3 A/D Control Register (ADCR).........................................................................352
12.3 CPU Interface ...............................................................................................................353
12.4 Operation......................................................................................................................354
12.4.1 Single Mode (SCAN = 0).................................................................................355
12.4.2 Scan Mode (SCAN = 1)...................................................................................357
12.4.3 Input Sampling and A/D Conversion Time.......................................................359
12.4.4 External Trigger Input Timing.........................................................................360

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12.5 Interrupts ......................................................................................................................361
12.6 Usage Notes.................................................................................................................. 361
Section 13 RAM............................................................................................363
13.1 Overview ...................................................................................................................... 363
13.1.1 Block Diagram.................................................................................................363
13.1.2 Register Configuration..................................................................................... 364
13.2 System Control Register (SYSCR)................................................................................364
13.3 Operation......................................................................................................................365
13.3.1 Mode 1 ............................................................................................................365
13.3.2 Mode 2 .............................................................................................................365
13.3.3 Mode 3 .............................................................................................................365
Section 14 ROM............................................................................................367
14.1 Overview ...................................................................................................................... 367
14.1.1 Block Diagram.................................................................................................367
14.2 PROM Mode.................................................................................................................368
14.2.1 PROM Mode Setting........................................................................................368
14.2.2 Socket Adapter and Memory Map.................................................................... 368
14.3 Programming ................................................................................................................ 370
14.3.1 Programming and Verification......................................................................... 371
14.3.2 Programming Precautions................................................................................ 374
14.4 Reliability of Programmed Data....................................................................................375
Section 15 Clock Pulse Generator..................................................................377
15.1 Overview ...................................................................................................................... 377
15.1.1 Block Diagram.................................................................................................377
15.2 Oscillator Circuit .......................................................................................................... 377
15.2.1 Connecting a Crystal Resonator.......................................................................378
15.2.2 External Clock Input........................................................................................380
15.3 Duty Adjustment Circuit...............................................................................................382
15.4 Prescalers...................................................................................................................... 382
Section 16 Power-Down State........................................................................383
16.1 Overview ...................................................................................................................... 383
16.2 Register Configuration..................................................................................................384
16.2.1 System Control Register (SYSCR)................................................................... 384
16.3 Sleep Mode................................................................................................................... 385
16.3.1 Transition to Sleep Mode................................................................................. 385
16.3.2 Exit from Sleep Mode......................................................................................386
16.4 Software Standby Mode................................................................................................386
16.4.1 Transition to Software Standby Mode..............................................................386
16.4.2 Exit from Software Standby Mode...................................................................386

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16.4.3 Selection of Oscillator Waiting Time after Exit from Software Standby Mode.387
16.4.4 Sample Application of Software Standby Mode...............................................387
16.4.5 Usage Note ......................................................................................................388
16.5 Hardware Standby Mode...............................................................................................388
16.5.1 Transition to Hardware Standby Mode.............................................................388
16.5.2 Exit from Hardware Standby Mode..................................................................389
16.5.3 Timing for Hardware Standby Mode................................................................389
Section 17 Electrical Characteristics (Preliminary).........................................391
17.1 Absolute Maximum Ratings..........................................................................................391
17.2 Electrical Characteristics................................................................................................392
17.2.1 DC Characteristics............................................................................................392
17.2.2 AC Characteristics...........................................................................................403
17.2.3 A/D Conversion Characteristics.......................................................................410
17.3 Operational Timing.......................................................................................................411
17.3.1 Bus Timing......................................................................................................411
17.3.2 Control Signal Timing .....................................................................................413
17.3.3 Clock Timing...................................................................................................414
17.3.4 TPC and I/O Port Timing.................................................................................415
17.3.5 ITU Timing......................................................................................................415
17.3.6 SCI Input/Output Timing.................................................................................416
Appendix A Instruction Set............................................................................417
A.1 Instruction List...............................................................................................................417
A.2 Operation Code Maps......................................................................................................432
A.3 Number of States Required for Execution ......................................................................435
Appendix B Internal I/O Register Field..........................................................445
B.1 Addresses.......................................................................................................................445
B.2 Function.........................................................................................................................453
TSTR—Timer Start Register H'60 ITU (all channels)..................................................454
TSNC—Timer Synchro Register H'61 ITU (all channels)............................................455
TMDR—Timer Mode Register H'62 ITU (all channels) ..............................................456
TFCR—Timer Function Control Register H'63 ITU (all channels) ..............................457
TCR0—Timer Control Register 0 H'64 ITU0..............................................................458
TIOR0—Timer I/O Control Register 0 H'65 ITU0.......................................................459
TIER0—Timer Interrupt Enable Register 0 H'66 ITU0................................................460
TSR0—Timer Status Register 0 H'67 ITU0.................................................................461
TCNT0 H/L—Timer Counter 0 H/L H'68, H'69 ITU0.................................................462
GRA0 H/L—General Register A0 H/L H'6A, H'6B ITU0............................................462
GRB0 H/L—General Register B0 H/L H'6C, H'6D ITU0 ............................................462
TCR1—Timer Control Register 1 H'6E ITU1..............................................................462
TIOR1—Timer I/O Control Register 1 H'6F ITU1.......................................................463

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TIER1—Timer Interrupt Enable Register 1 H'70 ITU1................................................ 463
TSR1—Timer Status Register 1 H'71 ITU1................................................................. 463
TCNT1 H/L—Timer Counter 1 H/L H'72, H'73 ITU1................................................. 463
GRA1 H/L—General Register A1 H/L H'74, H'75 ITU1 ............................................. 464
GRB1 H/L—General Register B1 H/L H'76, H'77 ITU1..............................................464
TCR2—Timer Control Register 2 H'78 ITU2.............................................................. 464
TIOR2—Timer I/O Control Register 2 H'79 ITU2.......................................................465
TIER2—Timer Interrupt Enable Register 2 H'7A ITU2............................................... 465
TSR2—Timer Status Register 2 H'7B ITU2 ................................................................465
TCNT2 H/L—Timer Counter 2 H/L H'7C, H'7D ITU2................................................466
GRA2 H/L—General Register A2 H/L H'7E, H'7F ITU2............................................. 466
GRB2 H/L—General Register B2 H/L H'80, H'81 ITU2..............................................466
TCR3—Timer Control Register 3 H'82 ITU3.............................................................. 467
TIOR3—Timer I/O Control Register 3 H'83 ITU3.......................................................467
TIER3—Timer Interrupt Enable Register 3 H'84 ITU3................................................ 467
TSR3—Timer Status Register 3 H'85 ITU3................................................................. 468
TCNT3 H/L—Timer Counter 3 H/L H'86, H'87 ITU3................................................. 469
GRA3 H/L—General Register A3 H/L H'88, H'89 ITU3 ............................................. 469
GRB3 H/L—General Register B3 H/L H'8A, H'8B ITU3............................................469
BRA3 H/L—Buffer Register A3 H/L H'8C, H'8D ITU3..............................................470
BRB3 H/L—Buffer Register B3 H/L H'8E, H'8F ITU3 ...............................................470
TOER—Timer Output Enable Register H'90 ITU (all channels).................................. 470
TOCR—Timer Output Control Register H'91 ITU (all channels).................................472
TCR4—Timer Control Register 4 H'92 ITU4.............................................................. 473
TIOR4—Timer I/O Control Register 4 H'93 ITU4.......................................................473
TIER4—Timer Interrupt Enable Register 4 H'94 ITU4................................................ 473
TSR4—Timer Status Register 4 H'95 ITU4................................................................. 473
TCNT4 H/L—Timer Counter 4 H/L H'96, H'97 ITU4................................................. 474
GRA4 H/L—General Register A4 H/L H'98, H'99 ITU4 ............................................. 474
GRB4 H/L—General Register B4 H/L H'9A, H'9B ITU4............................................474
BRA4 H/L—Buffer Register A4 H/L H'9C, H'9D ITU4..............................................474
BRB4 H/L—Buffer Register B4 H/L H'9E, H'9F ITU4 ...............................................475
TPMR—TPC Output Mode Register H'A0 TPC.......................................................... 476
TPCR—TPC Output Control Register H'A1 TPC........................................................477
NDERB—Next Data Enable Register B H'A2 TPC.....................................................478
NDERA—Next Data Enable Register A H'A3 TPC..................................................... 478
NDRB—Next Data Register B H'A4/H'A6 TPC..........................................................479
NDRA—Next Data Register A H'A5/H'A7 TPC..........................................................480
TCNT—Timer Counter H'A9 (read), WDT H'A8 (write)............................................. 481
RSTCSR—Reset Control/Status Register H'AB (read), WDT H'AA (write)................481
TCSR—Timer Control/Status Register H'A8 WDT.....................................................482
SMR—Serial Mode Register H'B0 SCI .......................................................................483
BRR—Bit Rate Register H'B1 SCI..............................................................................484

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SCR—Serial Control Register H'B2 SCI......................................................................485
TDR—Transmit Data Register H'B3 SCI.....................................................................486
SSR—Serial Status Register H'B4 SCI ........................................................................487
RDR—Receive Data Register H'B5 SCI......................................................................488
P1DDR—Port 1 Data Direction Register H'C0 Port 1..................................................488
P2DDR—Port 2 Data Direction Register H'C1 Port 2..................................................488
P1DR—Port 1 Data Register H'C2 Port 1....................................................................489
P2DR—Port 2 Data Register H'C3 Port 2....................................................................489
P3DDR—Port 3 Data Direction Register H'C4 Port 3..................................................489
P3DR—Port 3 Data Register H'C6 Port 3....................................................................489
P5DDR—Port 5 Data Direction Register H'C8 Port 5..................................................490
P6DDR—Port 6 Data Direction Register H'C9 Port 6..................................................490
P5DR—Port 5 Data Register H'CA Port 5 ...................................................................490
P6DR—Port 6 Data Register H'CB Port 6....................................................................491
P8DDR—Port 8 Data Direction Register H'CD Port 8.................................................491
P7DR—Port 7 Data Register H'CE Port 7....................................................................491
P8DR—Port 8 Data Register H'CF Port 8....................................................................492
P9DDR—Port 9 Data Direction Register H'D0 Port 9..................................................492
PADDR—Port A Data Direction Register H'D1 Port A ...............................................492
P9DR—Port 9 Data Register H'D2 Port 9....................................................................493
PADR—Port A Data Register H'D3 Port A..................................................................493
PBDDR—Port B Data Direction Register H'D4 Port B................................................493
PBDR—Port B Data Register H'D6 Port B..................................................................494
P2PCR—Port 2 Input Pull-Up Control Register H'D8 Port 2........................................494
P5PCR—Port 5 Input Pull-Up Control Register H'DB Port 5.......................................494
ADDRA H/L—A/D Data Register A H/L H'E0, H'E1 A/D..........................................495
ADDRB H/L—A/D Data Register B H/L H'E2, H'E3 A/D ..........................................495
ADDRC H/L—A/D Data Register C H/L H'E4, H'E5 A/D ..........................................495
ADDRD H/L—A/D Data Register D H/L H'E6, H'E7 A/D..........................................496
ADCR—A/D Control Register H'E9 A/D....................................................................496
ADCSR—A/D Control/Status Register H'E8 A/D........................................................497
ASTCR—Access State Control Register H'ED Bus controller .....................................498
WCR—Wait Control Register H'EE Bus controller.....................................................499
WCER—Wait Controller Enable Register H'EF Bus controller...................................500
MDCR—Mode Control Register H'F1 System control.................................................500
SYSCR—System Control Register H'F2 System control..............................................501
ADRCR—Address Control Register H'F3 Bus controller.............................................502
ISCR—IRQ Sense Control Register H'F4 Interrupt controller......................................503
IER—IRQ Enable Register H'F5 Interrupt controller...................................................503
ISR—IRQ Status Register H'F6 Interrupt controller.....................................................504
IPRA—Interrupt Priority Register A H'F8 Interrupt controller.....................................505
IPRB—Interrupt Priority Register B H'F9 Interrupt controller.....................................505

xii
Appendix C I/O Port Block Diagrams............................................................507
C.1 Port 1 Block Diagram.....................................................................................................507
C.2 Port 2 Block Diagram.....................................................................................................508
C.3 Port 3 Block Diagram.....................................................................................................509
C.4 Port 5 Block Diagram.....................................................................................................510
C.5 Port 6 Block Diagram....................................................................................................511
C.6 Port 7 Block Diagram.....................................................................................................513
C.7 Port 8 Block Diagram.....................................................................................................514
C.8 Port 9 Block Diagram.....................................................................................................516
C.9 Port A Block Diagram.................................................................................................... 519
C.10 Port B Block Diagram.................................................................................................. 522
Appendix D Pin States...................................................................................527
D.1 Port States in Each Mode ............................................................................................... 527
D.2 Pin States at Reset.......................................................................................................... 529
Appendix E Timing of Transition to and
Recovery from Hardware Standby Mode .........................................................533
Appendix F Product Code Lineup..................................................................535
Appendix G Package Dimensions ..................................................................537

1
Preface

2

3
Section 1 Overview
1.1 Overview
The H8/3035 Series comprises microcomputers (MCUs) that integrate system supporting
functions together with an H8/300H CPU core featuring an original Hitachi architecture.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space. Its instruction set is upward-compatible at the object-code level with the H8/300 CPU,
enabling easy porting of software from the H8/300 Series.
The on-chip system supporting functions include ROM, RAM, a 16-bit integrated timer unit
(ITU), a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial
communication interface (SCI), an A/D converter, I/O ports, and other facilities.
The H8/3035 Series consists of three models: the H8/3035 with 256 kbytes of ROM and 4 kbytes
of RAM, the H8/3034 with 192 kbytes of ROM and 4 kbytes of RAM, and the H8/3033 with 128
kbytes of ROM and 4 kbytes of RAM.
The three MCU operating modes offer a choice of expanded mode and single-chip mode.
In addition to the masked-ROM versions of the H8/3035 Series, a ZTAT™*version with user-
programmable on-chip PROM is also available. This version enables users to respond quickly
and flexibly to changing application specifications, growing production volumes, and other
conditions.
Table 1-1 summarizes the features of the H8/3035 Series.
Note: * ZTAT (Zero Turn-Around Time) is a trademark of Hitachi, Ltd.

4
Table 1-1 Features
Feature Description
CPU Upward-compatible with the H8/300 CPU at the object-code level
General-register machine
• Sixteen 16-bit general registers
(also useable as sixteen 8-bit registers or eight 32-bit registers)
High-speed operation
• Maximum clock rate: 18 MHz
• Add/subtract: 111 ns
• Multiply/divide: 778 ns
Two CPU operating modes
• Normal mode (64-kbyte address space)*
• Advanced mode (16-Mbyte address space)
Instruction features
• 8/16/32-bit data transfer, arithmetic, and logic instructions
• Signed and unsigned multiply instructions (8 bits ×8 bits, 16 bits ×16 bits)
• Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16 bits)
• Bit accumulator function
• Bit manipulation instructions with register-indirect specification of bit
positions
Memory H8/3035
• ROM: 256 kbytes
• RAM: 4 kbytes
H8/3034
• ROM: 192 kbytes
• RAM: 4 kbytes
H8/3033
• ROM: 128 kbytes
• RAM: 4 kbytes
Interrupt
controller • Six external interrupt pins: NMI,
,54
0to
,54
4
• 21 internal interrupts
• Three selectable interrupt priority levels
Bus controller • Address space can be partitioned into eight areas, with independent bus
specifications in each area
• Two-state or three-state access selectable for each area
• Selection of four wait modes
Note: *Normal mode cannot be used with the H8/3035 Series.

5
Table 1-1 Features (cont)
Feature Description
16-bit integrated
timer unit (ITU) • Five 16-bit timer channels, capable of processing up to 12 pulse outputs
or 10 pulse inputs
• 16-bit timer counter (channels 0 to 4)
• Two multiplexed output compare/input capture pins (channels 0 to 4)
• Operation can be synchronized (channels 0 to 4)
• PWM mode available (channels 0 to 4)
• Phase counting mode available (channel 2)
• Buffering available (channels 3 and 4)
• Reset-synchronized PWM mode available (channels 3 and 4)
• Complementary PWM mode available (channels 3 and 4)
Programmable
timing pattern
controller (TPC)
• Maximum 16-bit pulse output, using ITU as time base
• Up to four 4-bit pulse output groups (or one 16-bit group, or two 8-bit
groups)
• Non-overlap mode available
Watchdog timer
(WDT), 1 channel • Reset signal can be generated by overflow
• Reset signal can be output externally
• Usable as an interval timer
Serial
communication
interface (SCI),
1 channel
• Selection of asynchronous or synchronous mode
• Full duplex: can transmit and receive simultaneously
• On-chip baud-rate generator
A/D converter • Resolution: 10 bits
• Eight channels, with selection of single or scan mode
• Variable analog conversion voltage range
• Sample-and-hold function
• Can be externally triggered
I/O ports • 55 input/output pins
• 8 input-only pins

6
Table 1-1 Features (cont)
Feature Description
Operating modes Three MCU operating modes
Mode Address Space Address Pins Bus Width
Mode 1 1 Mbyte A0to A19 8 bits
Mode 2 16 Mbytes A23 to A08 bits
Mode 3 1 Mbyte — —
Power-down
state • Sleep mode
• Software standby mode
• Hardware standby mode
Other features • On-chip clock oscillator
Product lineup Model Package ROM
HD6473035F
HD6473035TE 80-pin QFP (FP-80A) 80-pin TQFP (TFP-80C) PROM
HD6433035F
HD6433035TE 80-pin QFP (FP-80A) 80-pin TQFP (TFP-80C) Mask ROM
HD6433034F
HD6433034TE 80-pin QFP (FP-80A) 80-pin TQFP (TFP-80C) Mask ROM
HD6433033F
HD6433033TE 80-pin QFP (FP-80A) 80-pin TQFP (TFP-80C) Mask ROM