Hitachi H8/3032 Series User manual

Hitachi Microcomputer
H8/3032 Series
Hardware Manual
OMC942723169
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Preface
The H8/3032 Series is a series of high-performance single-chip microcontrollers that integrate
system supporting functions together with an H8/300H CPU core.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space.*
The on-chip system supporting functions include ROM, RAM, a 16-bit integrated timer unit
(ITU), a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial
communication interface (SCI), an A/D converter, I/O ports, and other facilities.
The three operating modes offer a choice of expanded mode and single-chip mode, enabling the
H8/3032 Series to adapt quickly and flexibly to a variety of conditions.
This manual describes the H8/3032 Series hardware. For details of the instruction set, refer to the
H8/300H Programming Manual.
Note: * The H8/3032 Series has a maximum address space of 1 Mbyte.
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Contents
Section 1 Overview..................................................................................................... 1
1.1 Overview ........................................................................................................................ 1
1.2 Block Diagram................................................................................................................ 5
1.3 Pin Description ............................................................................................................... 6
1.3.1 Pin Arrangement............................................................................................. 6
1.3.2 Pin Functions.................................................................................................. 7
1.4 Pin Functions.................................................................................................................. 10
Section 2 CPU............................................................................................................... 15
2.1 Overview ........................................................................................................................ 15
2.1.1 Features........................................................................................................... 15
2.1.2 Differences from H8/300 CPU....................................................................... 16
2.2 CPU Operating Modes.................................................................................................... 17
2.3 Address Space................................................................................................................. 18
2.4 Register Configuration.................................................................................................... 19
2.4.1 Overview......................................................................................................... 19
2.4.2 General Registers............................................................................................ 20
2.4.3 Control Registers............................................................................................ 21
2.4.4 Initial CPU Register Values............................................................................ 22
2.5 Data Formats................................................................................................................... 23
2.5.1 General Register Data Formats....................................................................... 23
2.5.2 Memory Data Formats.................................................................................... 24
2.6 Instruction Set................................................................................................................. 26
2.6.1 Instruction Set Overview................................................................................ 26
2.6.2 Instructions and Addressing Modes................................................................ 27
2.6.3 Tables of Instructions Classified by Function ................................................ 28
2.6.4 Basic Instruction Formats............................................................................... 38
2.6.5 Notes on Use of Bit Manipulation Instructions.............................................. 39
2.7 Addressing Modes and Effective Address Calculation.................................................. 39
2.7.1 Addressing Modes.......................................................................................... 39
2.7.2 Effective Address Calculation........................................................................ 42
2.8 Processing States ............................................................................................................ 46
2.8.1 Overview......................................................................................................... 46
2.8.2 Program Execution State ................................................................................ 47
2.8.3 Exception-Handling State............................................................................... 47
2.8.4 Exception-Handling Sequences...................................................................... 49
2.8.5 Reset State ...................................................................................................... 50
2.8.6 Power-Down State.......................................................................................... 50
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2.9 Basic Operational Timing............................................................................................... 51
2.9.1 Overview......................................................................................................... 51
2.9.2 On-Chip Memory Access Timing................................................................... 51
2.9.3 On-Chip Supporting Module Access Timing................................................. 53
2.9.4 Access to External Address Space.................................................................. 54
Section 3 MCU Operating Modes........................................................................... 55
3.1 Overview ........................................................................................................................ 55
3.1.1 Operating Mode Selection.............................................................................. 55
3.1.2 Register Configuration.................................................................................... 56
3.2 Mode Control Register (MDCR).................................................................................... 57
3.3 System Control Register (SYSCR)................................................................................. 58
3.4 Operating Mode Descriptions......................................................................................... 60
3.4.1 Mode 1............................................................................................................ 60
3.4.2 Mode 2............................................................................................................ 60
3.4.3 Mode 3............................................................................................................ 60
3.5 Pin Functions in Each Operating Mode.......................................................................... 61
3.6 Memory Map in Each Operating Mode.......................................................................... 61
Section 4 Exception Handling.................................................................................. 65
4.1 Overview ........................................................................................................................ 65
4.1.1 Exception Handling Types and Priority.......................................................... 65
4.1.2 Exception Handling Operation....................................................................... 65
4.1.3 Exception Vector Table................................................................................... 66
4.2 Reset ........................................................................................................................ 67
4.2.1 Overview......................................................................................................... 67
4.2.2 Reset Sequence............................................................................................... 67
4.2.3 Interrupts after Reset....................................................................................... 69
4.3 Interrupts ........................................................................................................................ 70
4.4 Trap Instruction............................................................................................................... 71
4.5 Stack Status after Exception Handling........................................................................... 72
4.6 Notes on Stack Usage..................................................................................................... 73
Section 5 Interrupt Controller................................................................................... 75
5.1 Overview ........................................................................................................................ 75
5.1.1 Features........................................................................................................... 75
5.1.2 Block Diagram................................................................................................ 76
5.1.3 Pin Configuration............................................................................................ 77
5.1.4 Register Configuration.................................................................................... 77
5.2 Register Descriptions...................................................................................................... 78
5.2.1 System Control Register (SYSCR)................................................................. 78
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5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB)....................................... 79
5.2.3 IRQ Status Register (ISR) .............................................................................. 85
5.2.4 IRQ Enable Register (IER)............................................................................. 86
5.2.5 IRQ Sense Control Register (ISCR)............................................................... 87
5.3 Interrupt Sources............................................................................................................. 88
5.3.1 External Interrupts.......................................................................................... 88
5.3.2 Internal Interrupts ........................................................................................... 89
5.3.3 Interrupt Vector Table..................................................................................... 89
5.4 Interrupt Operation ......................................................................................................... 92
5.4.1 Interrupt Handling Process............................................................................. 92
5.4.2 Interrupt Sequence.......................................................................................... 97
5.4.3 Interrupt Response Time................................................................................. 98
5.5 Usage Notes.................................................................................................................... 99
5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction................ 99
5.5.2 Instructions that Inhibit Interrupts.................................................................. 100
5.5.3 Interrupts during EEPMOV Instruction Execution ........................................ 100
Section 6 Bus Controller............................................................................................ 101
6.1 Overview ........................................................................................................................ 101
6.1.1 Features........................................................................................................... 101
6.1.2 Block Diagram................................................................................................ 102
6.1.3 Input/Output Pins............................................................................................ 103
6.1.4 Register Configuration.................................................................................... 103
6.2 Register Descriptions...................................................................................................... 104
6.2.1 Access State Control Register (ASTCR)........................................................ 104
6.2.2 Wait Control Register (WCR)......................................................................... 105
6.2.3 Wait State Controller Enable Register (WCER)............................................. 106
6.3 Operation ........................................................................................................................ 107
6.3.1 Area Division.................................................................................................. 107
6.3.2 Bus Control Signal Timing............................................................................. 109
6.3.3 Wait Modes..................................................................................................... 111
6.3.4 Interconnections with Memory (Example)..................................................... 117
6.4 Usage Notes.................................................................................................................... 118
6.4.1 Register Write Timing .................................................................................... 118
Section 7 I/O Ports....................................................................................................... 119
7.1 Overview ........................................................................................................................ 119
7.2 Port 1 ........................................................................................................................ 122
7.2.1 Overview......................................................................................................... 122
7.2.2 Register Descriptions...................................................................................... 123
7.2.3 Pin Functions in Each Mode........................................................................... 124
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7.3 Port 2 ........................................................................................................................ 126
7.3.1 Overview......................................................................................................... 126
7.3.2 Register Descriptions...................................................................................... 127
7.3.3 Pin Functions in Each Mode........................................................................... 128
7.3.4 Input Pull-Up Transistors................................................................................ 130
7.4 Port 3 ........................................................................................................................ 131
7.4.1 Overview......................................................................................................... 131
7.4.2 Register Descriptions...................................................................................... 131
7.4.3 Pin Functions in Each Mode........................................................................... 133
7.5 Port 5 ........................................................................................................................ 134
7.5.1 Overview......................................................................................................... 134
7.5.2 Register Descriptions...................................................................................... 134
7.5.3 Pin Functions in Each Mode........................................................................... 137
7.5.4 Input Pull-Up Transistors................................................................................ 138
7.6 Port 6 ........................................................................................................................ 139
7.6.1 Overview......................................................................................................... 139
7.6.2 Register Descriptions...................................................................................... 139
7.6.3 Pin Functions in Each Mode........................................................................... 141
7.7 Port 7 ........................................................................................................................ 144
7.7.1 Overview......................................................................................................... 144
7.7.2 Register Description ....................................................................................... 145
7.8 Port 8 ........................................................................................................................ 146
7.8.1 Overview......................................................................................................... 146
7.8.2 Register Descriptions...................................................................................... 147
7.8.3 Pin Functions.................................................................................................. 148
7.9 Port 9 ........................................................................................................................ 150
7.9.1 Overview......................................................................................................... 150
7.9.2 Register Descriptions...................................................................................... 150
7.9.3 Pin Functions.................................................................................................. 152
7.10 Port A ........................................................................................................................ 153
7.10.1 Overview......................................................................................................... 153
7.10.2 Register Descriptions...................................................................................... 154
7.10.3 Pin Functions ................................................................................................. 156
7.11 Port B ........................................................................................................................ 161
7.11.1 Overview......................................................................................................... 161
7.11.2 Register Descriptions...................................................................................... 161
7.11.3 Pin Functions.................................................................................................. 163
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Section 8 16-Bit Integrated Timer Unit (ITU)..................................................... 169
8.1 Overview ........................................................................................................................ 169
8.1.1 Features........................................................................................................... 169
8.1.2 Block Diagrams.............................................................................................. 172
8.1.3 Input/Output Pins............................................................................................ 177
8.1.4 Register Configuration.................................................................................... 178
8.2 Register Descriptions...................................................................................................... 181
8.2.1 Timer Start Register (TSTR) .......................................................................... 181
8.2.2 Timer Synchro Register (TSNC).................................................................... 182
8.2.3 Timer Mode Register (TMDR)....................................................................... 184
8.2.4 Timer Function Control Register (TFCR) ...................................................... 187
8.2.5 Timer Output Master Enable Register (TOER).............................................. 189
8.2.6 Timer Output Control Register (TOCR)......................................................... 192
8.2.7 Timer Counters (TCNT)................................................................................. 193
8.2.8 General Registers (GRA, GRB) ..................................................................... 194
8.2.9 Buffer Registers (BRA, BRB)........................................................................ 195
8.2.10 Timer Control Registers (TCR)...................................................................... 196
8.2.11 Timer I/O Control Register (TIOR)................................................................ 198
8.2.12 Timer Status Register (TSR)........................................................................... 200
8.2.13 Timer Interrupt Enable Register (TIER)......................................................... 203
8.3 CPU Interface ................................................................................................................. 205
8.3.1 16-Bit Accessible Registers............................................................................ 205
8.3.2 8-Bit Accessible Registers.............................................................................. 207
8.4 Operation ........................................................................................................................ 209
8.4.1 Overview......................................................................................................... 209
8.4.2 Basic Functions............................................................................................... 210
8.4.3 Synchronization.............................................................................................. 220
8.4.4 PWM Mode .................................................................................................... 222
8.4.5 Reset-Synchronized PWM Mode................................................................... 226
8.4.6 Complementary PWM Mode.......................................................................... 229
8.4.7 Phase Counting Mode..................................................................................... 239
8.4.8 Buffering......................................................................................................... 241
8.4.9 ITU Output Timing......................................................................................... 248
8.5 Interrupts ........................................................................................................................ 250
8.5.1 Setting of Status Flags.................................................................................... 250
8.5.2 Clearing of Status Flags.................................................................................. 252
8.5.3 Interrupt Sources............................................................................................. 253
8.6 Usage Notes.................................................................................................................... 254
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Section 9 Programmable Timing Pattern Controller......................................... 269
9.1 Overview ........................................................................................................................ 269
9.1.1 Features........................................................................................................... 269
9.1.2 Block Diagram................................................................................................ 270
9.1.3 TPC Pins......................................................................................................... 271
9.1.4 Registers ......................................................................................................... 272
9.2 Register Descriptions...................................................................................................... 273
9.2.1 Port A Data Direction Register (PADDR)...................................................... 273
9.2.2 Port A Data Register (PADR)......................................................................... 273
9.2.3 Port B Data Direction Register (PBDDR)...................................................... 274
9.2.4 Port B Data Register (PBDR)......................................................................... 274
9.2.5 Next Data Register A (NDRA)....................................................................... 275
9.2.6 Next Data Register B (NDRB)....................................................................... 277
9.2.7 Next Data Enable Register A (NDERA)........................................................ 279
9.2.8 Next Data Enable Register B (NDERB)......................................................... 280
9.2.9 TPC Output Control Register (TPCR)............................................................ 281
9.2.10 TPC Output Mode Register (TPMR).............................................................. 284
9.3 Operation ........................................................................................................................ 286
9.3.1 Overview......................................................................................................... 286
9.3.2 Output Timing................................................................................................. 287
9.3.3 Normal TPC Output........................................................................................ 288
9.3.4 Non-Overlapping TPC Output........................................................................ 290
9.3.5 TPC Output Triggering by Input Capture....................................................... 292
9.4 Usage Notes.................................................................................................................... 293
9.4.1 Operation of TPC Output Pins........................................................................ 293
9.4.2 Note on Non-Overlapping Output.................................................................. 293
Section 10 Watchdog Timer........................................................................................ 295
10.1 Overview ........................................................................................................................ 295
10.1.1 Features........................................................................................................... 295
10.1.2 Block Diagram................................................................................................ 296
10.1.3 Pin Configuration............................................................................................ 296
10.1.4 Register Configuration.................................................................................... 297
10.2 Register Descriptions...................................................................................................... 298
10.2.1 Timer Counter (TCNT)................................................................................... 298
10.2.2 Timer Control/Status Register (TCSR)........................................................... 299
10.2.3 Reset Control/Status Register (RSTCSR) ...................................................... 301
10.2.4 Notes on Register Access ............................................................................... 303
10.3 Operation ........................................................................................................................ 305
10.3.1 Watchdog Timer Operation............................................................................. 305
10.3.2 Interval Timer Operation ................................................................................ 306
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10.3.3 Timing of Setting of Overflow Flag (OVF).................................................... 307
10.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) ............................. 308
10.4 Interrupts ........................................................................................................................ 309
10.5 Usage Notes.................................................................................................................... 309
Section 11 Serial Communication Interface........................................................... 311
11.1 Overview ........................................................................................................................ 311
11.1.1 Features........................................................................................................... 311
11.1.2 Block Diagram................................................................................................ 313
11.1.3 Input/Output Pins............................................................................................ 314
11.1.4 Register Configuration.................................................................................... 314
11.2 Register Descriptions...................................................................................................... 315
11.2.1 Receive Shift Register (RSR)......................................................................... 315
11.2.2 Receive Data Register (RDR)......................................................................... 315
11.2.3 Transmit Shift Register (TSR)........................................................................ 316
11.2.4 Transmit Data Register (TDR) ....................................................................... 316
11.2.5 Serial Mode Register (SMR).......................................................................... 317
11.2.6 Serial Control Register (SCR)........................................................................ 321
11.2.7 Serial Status Register (SSR)........................................................................... 325
11.2.8 Bit Rate Register (BRR)................................................................................. 329
11.3 Operation ........................................................................................................................ 338
11.3.1 Overview......................................................................................................... 338
11.3.2 Operation in Asynchronous Mode.................................................................. 340
11.3.3 Multiprocessor Communication ..................................................................... 349
11.3.4 Synchronous Operation .................................................................................. 356
11.4 SCI Interrupts.................................................................................................................. 365
11.5 Usage Notes.................................................................................................................... 366
Section 12 A/D Converter............................................................................................ 371
12.1 Overview ........................................................................................................................ 371
12.1.1 Features........................................................................................................... 371
12.1.2 Block Diagram................................................................................................ 372
12.1.3 Input Pins........................................................................................................ 373
12.1.4 Register Configuration.................................................................................... 374
12.2 Register Descriptions...................................................................................................... 375
12.2.1 A/D Data Registers A to D (ADDRA to ADDRD)........................................ 375
12.2.2 A/D Control/Status Register (ADCSR).......................................................... 376
12.2.3 A/D Control Register (ADCR)....................................................................... 379
12.3 CPU Interface ................................................................................................................. 380
12.4 Operation ........................................................................................................................ 381
12.4.1 Single Mode (SCAN = 0)............................................................................... 381
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12.4.2 Scan Mode (SCAN = 1).................................................................................. 383
12.4.3 Input Sampling and A/D Conversion Time.................................................... 385
12.4.4 External Trigger Input Timing........................................................................ 386
12.5 Interrupts ........................................................................................................................ 387
12.6 Usage Notes.................................................................................................................... 387
Section 13 RAM............................................................................................................. 389
13.1 Overview ........................................................................................................................ 389
13.1.1 Block Diagram................................................................................................ 389
13.1.2 Register Configuration.................................................................................... 390
13.2 System Control Register (SYSCR)................................................................................. 391
13.3 Operation ........................................................................................................................ 392
13.3.1 Mode 1............................................................................................................ 392
13.3.2 Modes 2 and 3................................................................................................. 392
Section 14 ROM............................................................................................................. 393
14.1 Overview ........................................................................................................................ 393
14.1.1 Block Diagram................................................................................................ 393
14.2 PROM Mode................................................................................................................... 394
14.2.1 PROM Mode Setting ...................................................................................... 394
14.2.2 Socket Adapter and Memory Map.................................................................. 394
14.3 Programming .................................................................................................................. 397
14.3.1 Programming and Verification........................................................................ 397
14.3.2 Programming Precautions............................................................................... 402
14.4 Reliability of Programmed Data..................................................................................... 403
Section 15 Clock Pulse Generator............................................................................. 405
15.1 Overview ........................................................................................................................ 405
15.1.1 Block Diagram................................................................................................ 405
15.2 Oscillator Circuit ............................................................................................................ 406
15.2.1 Connecting a Crystal Resonator ..................................................................... 406
15.2.2 External Clock Input....................................................................................... 408
15.3 Duty Adjustment Circuit................................................................................................. 410
15.4 Prescalers........................................................................................................................ 410
Section 16 Power-Down State.................................................................................... 411
16.1 Overview ........................................................................................................................ 411
16.2 Register Configuration.................................................................................................... 412
16.2.1 System Control Register (SYSCR)................................................................. 412
16.3 Sleep Mode..................................................................................................................... 414
16.3.1 Transition to Sleep Mode................................................................................ 414
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16.3.2 Exit from Sleep Mode..................................................................................... 414
16.4 Software Standby Mode ................................................................................................. 415
16.4.1 Transition to Software Standby Mode............................................................ 415
16.4.2 Exit from Software Standby Mode................................................................. 415
16.4.3 Selection of Waiting Time for Exit from Software Standby Mode ................ 416
16.4.4 Sample Application of Software Standby Mode............................................ 417
16.4.5 Note................................................................................................................. 417
16.5 Hardware Standby Mode................................................................................................ 418
16.5.1 Transition to Hardware Standby Mode........................................................... 418
16.5.2 Exit from Hardware Standby Mode................................................................ 418
16.5.3 Timing for Hardware Standby Mode.............................................................. 418
Section 17 Electrical Characteristics........................................................................ 419
17.1 Absolute Maximum Ratings........................................................................................... 419
17.2 Electrical Characteristics................................................................................................ 420
17.2.1 DC Characteristics.......................................................................................... 420
17.2.2 AC Characteristics.......................................................................................... 430
17.2.3 A/D Conversion Characteristics..................................................................... 437
17.3 Operational Timing......................................................................................................... 438
17.3.1 Bus Timing ..................................................................................................... 438
17.3.2 Control Signal Timing .................................................................................... 442
17.3.3 Clock Timing.................................................................................................. 444
17.3.4 TPC and I/O Port Timing................................................................................ 444
17.3.5 ITU Timing..................................................................................................... 445
17.3.6 SCI Input/Output Timing................................................................................ 446
Appendix A Instruction Set............................................................................................ 447
A.1 Instruction List................................................................................................................ 447
A.2 Operating Code Maps..................................................................................................... 462
A.3 Number of States Required for Execution...................................................................... 465
Appendix B Register Field............................................................................................. 474
B.1 Register Addresses and Bit Names................................................................................. 474
B.2 Register Descriptions...................................................................................................... 482
Appendix C I/O Port Block Diagrams........................................................................ 532
C.1 Port 1 Block Diagram..................................................................................................... 532
C.2 Port 2 Block Diagram..................................................................................................... 533
C.3 Port 3 Block Diagram..................................................................................................... 534
C.4 Port 5 Block Diagram..................................................................................................... 535
C.5 Port 6 Block Diagram..................................................................................................... 536
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C.6 Port 7 Block Diagram..................................................................................................... 538
C.7 Port 8 Block Diagram..................................................................................................... 539
C.8 Port 9 Block Diagram..................................................................................................... 540
C.9 Port A Block Diagram .................................................................................................... 543
C.10 Port B Block Diagram .................................................................................................... 546
Appendix D Pin States..................................................................................................... 550
D.1 Port States in Each Mode................................................................................................ 550
D.2 Pin States at Reset........................................................................................................... 552
Appendix E Timing of Transition to and Recovery
from Hardware Standby Mode.............................................................. 555
Appendix F Package Dimensions................................................................................ 556
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Section 1 Overview
1.1 Overview
The H8/3032 Series is a series of microcontrollers (MCUs) that integrate system supporting
functions together with an H8/300H CPU core having an original Hitachi architecture.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space.*1 Its instruction set is upward-compatible at the object-code level with the H8/300 CPU,
enabling easy porting of software from the H8/300 Series.
The on-chip system supporting functions include ROM, RAM, a 16-bit integrated timer unit
(ITU), a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial
communication interface (SCI), an A/D converter, I/O ports, and other facilities.
The three members of the H8/3032 Series are the H8/3032, the H8/3031, and the H8/3030. The
H8/3032 has 64 kbytes of ROM and 2 kbytes of RAM. The H8/3031 has 32 kbytes of ROM and
1 kbyte of RAM. The H8/3030 has 16 kbytes of ROM and 512 bytes of RAM.
Three MCU operating modes offer a choice of data bus width and address space size. The modes
(modes 1 to 3) include a single-chip mode and expanded mode.
In addition to the masked-ROM versions of the H8/3032 Series, the H8/3032 has a ZTAT™*2
version with user-programmable on-chip PROM. This version enables users to respond quickly
and flexibly to changing application specifications, growing production volumes, and other
conditions.
Table 1-1 summarizes the features of the H8/3032 Series.
Notes: 1. The H8/3032 Series has a maximum address space of 1 Mbyte.
2. ZTAT (Zero Turn-Around Time) is a trademark of Hitachi, Ltd.
1
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Table 1-1 Features
Feature Description
CPU Upward-compatible with the H8/300 CPU at the object-code level
General-register machine
• Sixteen 16-bit general registers
(also useable as sixteen 8-bit registers or eight 32-bit registers)
High-speed operation
• Maximum clock rate: 16 MHz
• Add/subtract: 125 ns
• Multiply/divide: 875 ns
Two CPU operating modes
• Normal mode (64-kbyte address space)
• Advanced mode (1-Mbyte address space)
Instruction features
• 8/16/32-bit data transfer, arithmetic, and logic instructions
• Signed and unsigned multiply instructions (8 bits ×8 bits, 16 bits ×16 bits)
• Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16 bits)
• Bit accumulator function
• Bit manipulation instructions with register-indirect specification of bit positions
Memory H8/3032
• ROM: 64 kbytes
• RAM: 2 kbytes
H8/3031
• ROM: 32 kbytes
• RAM: 1 kbyte
H8/3030
• ROM: 16 kbytes
• RAM: 512 bytes
Interrupt • Six external interrupt pins: NMI, IRQ0to IRQ4
controller • 21 internal interrupts
• Three selectable interrupt priority levels
Bus controller • Address space can be partitioned into eight areas, with independent bus
specifications in each area
• Two-state or three-state access selectable for each area
• Selection of four wait modes
2
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Table 1-1 Features (cont)
Feature Description
16-bit integrated • Five 16-bit timer channels, capable of processing up to 12 pulse outputs or 10
timer unit (ITU) pulse inputs
• 16-bit timer counter (channels 0 to 4)
• Two multiplexed output compare/input capture pins (channels 0 to 4)
• Operation can be synchronized (channels 0 to 4)
• PWM mode available (channels 0 to 4)
• Phase counting mode available (channel 2)
• Buffering available (channels 3 and 4)
• Reset-synchronized PWM mode available (channels 3 and 4)
• Complementary PWM mode available (channels 3 and 4)
Programmable • Maximum 16-bit pulse output, using ITU as time base
timing pattern • Up to four 4-bit pulse output groups (or one 16-bit group, or two 8-bit groups)
controller (TPC) • Non-overlap mode available
Watchdog • Reset signal can be generated by overflow
timer (WDT), • Reset signal can be output externally
1 channel • Usable as an interval timer
Serial • Selection of asynchronous or synchronous mode
communication • Full duplex: can transmit and receive simultaneously
interface (SCI), • On-chip baud-rate generator
2 channels
A/D converter • Resolution: 10 bits
• Eight channels, with selection of single or scan mode
• Variable analog conversion voltage range
• Sample-and-hold function
• Can be externally triggered
I/O ports • 55 input/output pins
• 8 input-only pins
3
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Table 1-1 Features (cont)
Feature Description
Operating modes Three MCU operating modes
Address Address Bus
Mode Space Pins Width
Mode 1 1 Mbyte A0to A19 8 bits
Mode 2 64 kbytes — —
Mode 3 1 Mbyte — —
Power-down • Sleep mode
state • Software standby mode
• Hardware standby mode
Other features • On-chip clock oscillator
Product lineup Model Package ROM
HD6473032F 80-pin QFP (FP-80A) PROM
HD6473032TF 80-pin TQFP (TFP-80C)
HD6433032F 80-pin QFP (FP-80A) Mask ROM
HD6433032TF 80-pin TQFP (TFP-80C)
HD6433031F 80-pin QFP (FP-80A) Mask ROM
HD6433031TF 80-pin TQFP (TFP-80C)
HD6433030F 80-pin QFP (FP-80A) Mask ROM
HD6433030TF 80-pin TQFP (TFP-80C)
4
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1.2 Block Diagram
Figure 1-1 shows an internal block diagram.
Figure 1-1 Block Diagram
P77/AN7
P76/AN6 P75/AN5 P74/AN4 P73/AN3
P72/AN2
P71/AN1 P70/AN0
Vref
AVCC
AVSS
PA7/TIOCB2
PA6/TIOCA2 PA5/TIOCB1 PA4/TIOCA1
PA3/TIOCB0/TKCKD
PA2/TIOCA0/TCLKC
PA1/TCLKB
PA0/TCLKA
PB7/TP15/ADTRG
PB6/TP14
PB5/TP13/TOCXB4
PB4/TP12/TOCXA4
PB2/TP11/TIOCB4
PB2/TP10/TIOCA4
PB1/TP9/TIOCB3
PB0/TP8/TIOCA3
P27/A15
P26/A14
P25/A13
P24/A12
P23/A11
P22/A10
P21/A9
P20/A8
P17/A7
P16/A6
P15/A5
P14/A4
P13/A3
P12/A2
P11/A1
P10/A0
P94/SCK/IRQ4
P92/RxD
P90/TxD
P53/A15
P52/A16
P51/A17
P50/A18
Data bus (lower)
Bus
controller
Clock osc.
H8/300H CPU
PROM*
(or masked
ROM)
RAM
16-bit
integrated
timer-pulse unit
(ITU)
Programmable
timing pattern
controller (TPC)
Interrupt
controller
Watchdog 
timer
(WDT)
Serial
communication
interface
(SCI) ×1 channel
A/D converter
Port 3
P65/WR
P64/RD
P63/AS
P60/WAIT
P83/IRQ3
P82/IRQ2
P81/IRQ1
P80/IRQ0
MD1
MD0
EXTAL
XTAL
ø
STBY
RES
RESO
NMI
VCC VCC
VSS VSS VSS
P37/D7
P36/D6 P35/D5 P34/D4 P33/D3 P32/D2 P31/D1 P30/D0
Port 2Port 1 Port 5
Port 9
Port 7Port APort B
Port 8 Port 6
Address bus
Data bus (upper)
Note: PROM version is available only in the H8/3032 Series.
5
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