Hitachi H8/3006 User manual

H8/3006, H8/3007
HD6413006, HD6413007
Hardware Manual
ADE-602-145C
Rev. 4.0
1/29/00
Hitachi, Ltd.

Cautions
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have received the latest product standards or specifications before final design, purchase or
use.
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However, contact Hitachi’s sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of
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without written approval from Hitachi.
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semiconductor products.

Preface
The H8/3006 and H8/3007 is a series of high-performance microcontrollers that integrate system
supporting functions together with an H8/300H CPU core.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space.
The on-chip supporting functions include RAM, 16-bit timers, 8-bit timers, a programmable
timing pattern controller (TPC), a watchdog timer (WDT), a serial communication interface (SCI),
an A/D converter, a D/A converter, I/O ports, and a DMA controller (DMAC).
The address space is divided into eight areas. The data bus width and access cycle length can be
selected independently in each area, simplifying the connection of different types of memory. Four
MCU operating modes (modes 1 to 4) are provided, offering a choice of data bus width initial
value and address space.
With these features, the H8/3006 and H8/3007 offers easy implementation of compact, high-
performance systems.
This manual describes the H8/3006 and H8/3007 Series hardware. For details of the instruction
set, refer to the H8/300H Series Programming Manual.

List of Items Revised or Added for This Version
Page Item Description
3 1.1 Overview
Table 1-1 Feature Watchdog timer (WDT) Specification description amended
28 2.6.1 Instruction Set Overview Number of instruction
types amended
35 Table 2-7 Bit Manipulation Instructions Function description
added
41 2.6.5 Notes on Use of Bit Manipulation Instruction
Explanation Description added
45 Table 2-13 Effective Address Calculation No. 1 in Addressing Mode
and Instruction Format
column amended
57 Table 3-1 Operating Mode Selection Table amended
57 3.1.1 Operating Mode Selection Description added
70 4.2.2 Reset Sequence Description added
77 5.1.1 Features Description added
144 Figure 6.15 Example of Wait State Insertion Timing Figure amended
175 Figure 6.42 Example of Idle Cycle Operation (2)
(ICIS0 = 1)
(b) Idle cycle inserted
Bus cycle B amended
205 7.4.2 I/O Mode Description added
Table 7.6 Register Functions in I/O Mode Description added
207 7.4.3 Idle Mode Description added
208 Table 7.7 Register Functions in Idle Mode Description added
210 7.4.4 Repeat Mode Description added
211 Table 7.8 Register Functions in Repeat Mode Description added
226 7.4.8 DMAC Bus Cycle Note added
248 8.3.2 Register Configuration
Port 6 Data Direction Register (P6DDR) Description amended
249 8.3.2 Register Configuration
Port 6 Data Register (P6DR) Description amended
253 8.5.1 Overview Reference changed
Figure 8.4 Port 8 Pin Configuration Description added
254 8.5.2 Register Configuration
Port 8 Data Direction Register (P8DDR) Description amended

Page Item Description
255 8.5.2 Register Configuration
Port 8 Data Register (P8DR) Description amended
258 8.6.2 Register Configuration
Port 9 Data Direction Register (P9DDR) Description amended
263 8.7.2 Register Configuration
Port A Data Direction Register (PADDR) Description amended
272 Figure 8.7 Port B Pin Configuration Description added
273 8.8.2 Register Configuration
Port B Data Direction Register (PBDDR) Description amended
279 to 346 Section 9 16-Bit Timers Register names changed
TCNT →16TCNT
TCR →16TCR
347 to 382 Section 10 8-Bit Timers Register names changed
TCNT →8TCNT
TCR →8TCR
TCSR →8TCSR
351 Table 10.2 8-Bit Timer Register 8TCSR2 initial value
changed
355 10.2.4 Timer Control Register (8TCR)
Bits 4 and 3 Description amended
358 10.2.5 Timer Control/Status Registers (8TCSR)
Bit 4 Description added
411 Table 12.2 WDT Registers Note 3 added
462 Figure 13.5 Sample Flowchart for Transmitting Serial
Data Description added to (1)
502 Table 14.5 Bit Rates (bit/s) for Various BRR Settings
(When n = 0) 20.00 MHz value added
503 Table 14.6 BRR Settings for Typical Bit Rates (bits/s)
(When n = 0) 20.00 MHz value added
Table 14.7 Maximum Bit Rate for Various Frequencies
(Smart Card Interface Mode) 20.00 MHz value added
511 Figure 14.10 Procedure for Stopping and Restarting
the Clock Restart procedure amended
554 Figure 18.7 External Clock Output Setting Delay
Timing Figure amended
556 18.5.3 Usage Notes Text of 1st note amended
640, 641 B.1 Addresses Register names amended

Page Item Description
647 B.2 Functions
P8DDR—Port 8 Data Direction Register Note deleted
680 B.2 Functions
TSTR—Timer Start Register Description amended
681 B.2 Functions
TSNC—Timer Syncro Register Description amended
682 B.2 Functions
TMDR—Timer Mode Register Description amended
684 B.2 Functions
TISRA—Timer Interrupt Status Register A Description amended
685 B.2 Function
TISRB—Timer Interrupt Status Register B Description amended
686 B.2 Functions
TISRC—Timer Interrupt Status Register C Description amended
687 B.2 Functions
16TCR0—Timer Control Register 0 Register name changed
689 B.2 Functions
16TCNT0H/L—Timer Counter 0H/L Register name changed
690 B.2 Functions
16TCR1—Timer Control Register 1 Register name changed
B.2 Function
16TCNT1H/L—Timer Counter 1H/L Register name changed
691 B.2 Functions
16TCR2—Timer Control Register 2 Register name changed
692 B.2 Functions
16TCNT2H/L—Timer Counter 2H/L Register name changed
694 B.2 Functions
8TCR0—Timer Control Register 0
8TCR1—Timer Control Register 1
Register names changed,
description amended
695 B.2 Functions
8TCSR0—Timer Control/Status Register 0 Register names changed, description amended
696 B.2 Functions
8TCSR1—Timer Control/Status Register 1 Register names changed, description amended
697 B.2 Functions
8TCNT0—Timer Counter 0
8TCNT1—Timer Counter 1
Register names changed
700 B.2 Functions
8TCR2—Timer Control Register 2
8TCR3—Timer Control Register 3
Register names changed,
description amended

Page Item Description
701 B.2 Functions
8TCSR2—Timer Control/Status Register 2
8TCSR3—Timer Control/Status Register 3
Register names changed,
description amended
702 B.2 Functions
8TCNT2—Timer Counter 2
8TCNT3—Timer Counter 3
Register name changed
723 B.2 Functions
P6DR—Port 6 Data Register Description amended
729 Figure C.1 Port 4 Block Diagram Figure amended
730 to 732 Figure C.2(a) to Figure C.2(c)
Port 6 Block Diagram Figure amended
735 to 738 Figure C.4(a) to Figure C.4(d)
Port 8 Block Diagram Figure amended
739 to 744 Figure C.5(a) to Figure C.5(f)
Port 8 Block Diagram Figure amended
745 to 747 Figure C.6(a) to Figure C.6(c)
Port A Block Diagram Figure amended
748 to 753 Figure C.7(a) to Figure C.7(f)
Port B Block Diagram Figure amended

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Contents
Section 1 Overview.............................................................................................................. 1
1.1 Overview............................................................................................................................ 1
1.2 Internal Block Diagram...................................................................................................... 5
1.3 Pin Description................................................................................................................... 6
1.3.1 Pin Arrangement................................................................................................... 6
1.3.2 Pin Functions........................................................................................................ 8
1.3.3 Pin Assignments in Each Mode............................................................................ 13
Section 2 CPU........................................................................................................................ 17
2.1 Overview............................................................................................................................ 17
2.1.1 Features................................................................................................................. 17
2.1.2 Differences from H8/300 CPU ............................................................................. 18
2.2 CPU Operating Modes....................................................................................................... 19
2.3 Address Space.................................................................................................................... 20
2.4 Register Configuration.......................................................................................................21
2.4.1 Overview............................................................................................................... 21
2.4.2 General Registers.................................................................................................. 22
2.4.3 Control Registers.................................................................................................. 23
2.4.4 Initial CPU Register Values.................................................................................. 24
2.5 Data Formats...................................................................................................................... 25
2.5.1 General Register Data Formats............................................................................. 25
2.5.2 Memory Data Formats.......................................................................................... 26
2.6 Instruction Set.................................................................................................................... 28
2.6.1 Instruction Set Overview...................................................................................... 28
2.6.2 Instructions and Addressing Modes...................................................................... 29
2.6.3 Tables of Instructions Classified by Function...................................................... 30
2.6.4 Basic Instruction Formats..................................................................................... 39
2.6.5 Notes on Use of Bit Manipulation Instructions.................................................... 40
2.7 Addressing Modes and Effective Address Calculation...................................................... 42
2.7.1 Addressing Modes................................................................................................ 42
2.7.2 Effective Address Calculation.............................................................................. 44
2.8 Processing States................................................................................................................ 48
2.8.1 Overview............................................................................................................... 48
2.8.2 Program Execution State ...................................................................................... 49
2.8.3 Exception-Handling State..................................................................................... 49
2.8.4 Exception-Handling Sequences............................................................................ 51
2.8.5 Bus-Released State................................................................................................ 52
2.8.6 Reset State ............................................................................................................ 52
2.8.7 Power-Down State................................................................................................ 52

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2.9 Basic Operational Timing.................................................................................................. 53
2.9.1 Overview............................................................................................................... 53
2.9.2 On-Chip Memory Access Timing ........................................................................ 53
2.9.3 On-Chip Supporting Module Access Timing....................................................... 54
2.9.4 Access to External Address Space........................................................................ 55
Section 3 MCU Operating Modes................................................................................... 57
3.1 Overview............................................................................................................................ 57
3.1.1 Operating Mode Selection.................................................................................... 57
3.1.2 Register Configration............................................................................................ 58
3.2 Mode Control Register (MDCR) ....................................................................................... 58
3.3 System Control Register (SYSCR).................................................................................... 59
3.4 Operating Mode Descriptions............................................................................................ 62
3.4.1 Mode 1.................................................................................................................. 62
3.4.2 Mode 2.................................................................................................................. 62
3.4.3 Mode 3.................................................................................................................. 62
3.4.4 Mode 4.................................................................................................................. 62
3.5 Pin Functions in Each Operating Mode............................................................................. 63
3.6 Memory Map in Each Operating Mode............................................................................. 63
3.6.1 Note on Reserved Areas........................................................................................ 63
Section 4 Exception Handling.......................................................................................... 67
4.1 Overview............................................................................................................................ 67
4.1.1 Exception Handling Types and Priority................................................................ 67
4.1.2 Exception Handling Operation ............................................................................. 67
4.1.3 Exception Vector Table........................................................................................ 68
4.2 Reset................................................................................................................................... 70
4.2.1 Overview............................................................................................................... 70
4.2.2 Reset Sequence ..................................................................................................... 70
4.2.3 Interrupts after Reset............................................................................................. 72
4.3 Interrupts............................................................................................................................ 73
4.4 Trap Instruction.................................................................................................................. 73
4.5 Stack Status after Exception Handling .............................................................................. 74
4.6 Notes on Stack Usage ........................................................................................................ 74
Section 5 Interrupt Controller........................................................................................... 77
5.1 Overview............................................................................................................................ 77
5.1.1 Features................................................................................................................. 77
5.1.2 Block Diagram...................................................................................................... 78
5.1.3 Pin Configuration.................................................................................................. 79
5.1.4 Register Configuration.......................................................................................... 79
5.2 Register Descriptions......................................................................................................... 80
5.2.1 System Control Register (SYSCR)....................................................................... 80

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5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) ............................................. 81
5.2.3 IRQ Status Register (ISR) .................................................................................... 88
5.2.4 IRQ Enable Register (IER)................................................................................... 89
5.2.5 IRQ Sense Control Register (ISCR)..................................................................... 90
5.3 Interrupt Sources................................................................................................................ 91
5.3.1 External Interrupts................................................................................................ 91
5.3.2 Internal Interrupts.................................................................................................. 92
5.3.3 Interrupt Vector Table .......................................................................................... 92
5.4 Interrupt Operation............................................................................................................. 96
5.4.1 Interrupt Handling Process ................................................................................... 96
5.4.2 Interrupt Sequence................................................................................................ 101
5.4.3 Interrupt Response Time....................................................................................... 102
5.5 Usage Notes ....................................................................................................................... 103
5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction...................... 103
5.5.2 Instructions that Inhibit Interrupts........................................................................ 104
5.5.3 Interrupts during EEPMOV Instruction Execution .............................................. 104
Section 6 Bus Controller.................................................................................................... 105
6.1 Overview............................................................................................................................ 105
6.1.1 Features................................................................................................................. 105
6.1.2 Block Diagram...................................................................................................... 107
6.1.3 Pin Configuration.................................................................................................. 108
6.1.4 Register Configuration.......................................................................................... 109
6.2 Register Descriptions......................................................................................................... 110
6.2.1 Bus Width Control Register (ABWCR) ............................................................... 110
6.2.2 Access State Control Register (ASTCR).............................................................. 111
6.2.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 111
6.2.4 Bus Release Control Register (BRCR)................................................................. 115
6.2.5 Bus Control Register (BCR)................................................................................. 116
6.2.6 Chip Select Control Register (CSCR) .................................................................. 118
6.2.7 DRAM Control Register A (DRCRA).................................................................. 119
6.2.8 DRAM Control Register B (DRCRB).................................................................. 121
6.2.9 Refresh Timer Control/Status Register (RTMCSR)............................................. 124
6.2.10 Refresh Timer Counter (RTCNT) ........................................................................ 125
6.2.11 Refresh Time Constant Register (RTCOR).......................................................... 126
6.3 Operation............................................................................................................................ 127
6.3.1 Area Division........................................................................................................ 127
6.3.2 Bus Specifications ................................................................................................ 129
6.3.3 Memory Interfaces................................................................................................ 130
6.3.4 Chip Select Signals............................................................................................... 130
6.4 Basic Bus Interface............................................................................................................ 132
6.4.1 Overview............................................................................................................... 132
6.4.2 Data Size and Data Alignment.............................................................................. 132

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6.4.3 Valid Strobes........................................................................................................ 133
6.4.4 Memory Areas...................................................................................................... 134
6.4.5 Basic Bus Control Signal Timing......................................................................... 136
6.4.6 Wait Control.......................................................................................................... 143
6.5 DRAM Interface ................................................................................................................ 145
6.5.1 Overview............................................................................................................... 145
6.5.2 DRAM Space and RAS Output Pin Settings........................................................ 145
6.5.3 Address Multiplexing............................................................................................ 146
6.5.4 Data Bus................................................................................................................ 146
6.5.5 Pins Used for DRAM Interface ............................................................................ 146
6.5.6 Basic Timing......................................................................................................... 147
6.5.7 Precharge State Control........................................................................................ 148
6.5.8 Wait Control.......................................................................................................... 149
6.5.9 Byte Access Control and CAS Output Pin ........................................................... 150
6.5.10 Burst Operation..................................................................................................... 152
6.5.11 Refresh Control..................................................................................................... 157
6.5.12 Examples of Use................................................................................................... 160
6.5.13 Usage Notes.......................................................................................................... 164
6.6 Interval Timer .................................................................................................................... 167
6.6.1 Operation .............................................................................................................. 167
6.7 Interrupt Sources................................................................................................................ 172
6.8 Burst ROM Interface.......................................................................................................... 172
6.8.1 Overview............................................................................................................... 172
6.8.2 Basic Timing......................................................................................................... 172
6.8.3 Wait Control.......................................................................................................... 173
6.9 Idle Cycle........................................................................................................................... 174
6.9.1 Operation .............................................................................................................. 174
6.9.2 Pin States in Idle Cycle......................................................................................... 177
6.10 Bus Arbiter......................................................................................................................... 178
6.10.1 Operation .............................................................................................................. 178
6.11 Register and Pin Input Timing........................................................................................... 181
6.11.1 Register Write Timing.......................................................................................... 181
6.11.2 BREQ Pin Input Timing....................................................................................... 182
Section 7 DMA Controller................................................................................................. 183
7.1 Overview............................................................................................................................ 183
7.1.1 Features................................................................................................................. 183
7.1.2 Block Diagram...................................................................................................... 184
7.1.3 Functional Overview ............................................................................................ 185
7.1.4 Pin Configuration.................................................................................................. 186
7.1.5 Register Configuration.......................................................................................... 186
7.2 Register Descriptions (1) (Short Address Mode)............................................................... 188
7.2.1 Memory Address Registers (MAR)...................................................................... 188

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7.2.2 I/O Address Registers (IOAR).............................................................................. 189
7.2.3 Execute Transfer Count Registers (ETCR) .......................................................... 189
7.2.4 Data Transfer Control Registers (DTCR)............................................................. 191
7.3 Register Descriptions (2) (Full Address Mode)................................................................. 194
7.3.1 Memory Address Registers (MAR)...................................................................... 194
7.3.2 I/O Address Registers (IOAR).............................................................................. 194
7.3.3 Execute Transfer Count Registers (ETCR).......................................................... 195
7.3.4 Data Transfer Control Registers (DTCR)............................................................. 197
7.4 Operation............................................................................................................................ 203
7.4.1 Overview............................................................................................................... 203
7.4.2 I/O Mode............................................................................................................... 205
7.4.3 Idle Mode.............................................................................................................. 207
7.4.4 Repeat Mode......................................................................................................... 210
7.4.5 Normal Mode........................................................................................................ 214
7.4.6 Block Transfer Mode............................................................................................ 217
7.4.7 DMAC Activation ................................................................................................ 222
7.4.8 DMAC Bus Cycle................................................................................................. 224
7.4.9 Multiple-Channel Operation................................................................................. 230
7.4.10 External Bus Requests, DRAM Interface, and DMAC........................................ 231
7.4.11 NMI Interrupts and DMAC.................................................................................. 232
7.4.12 Aborting a DMAC Transfer.................................................................................. 233
7.4.13 Exiting Full Address Mode................................................................................... 234
7.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode.......................... 235
7.5 Interrupts............................................................................................................................ 236
7.6 Usage Notes ....................................................................................................................... 237
7.6.1 Note on Word Data Transfer ................................................................................ 237
7.6.2 DMAC Self-Access.............................................................................................. 237
7.6.3 Longword Access to Memory Address Registers ................................................ 237
7.6.4 Note on Full Address Mode Setup........................................................................ 237
7.6.5 Note on Activating DMAC by Internal Interrupts................................................ 238
7.6.6 NMI Interrupts and Block Transfer Mode............................................................ 239
7.6.7 Memory and I/O Address Register Values........................................................... 239
7.6.8 Bus Cycle when Transfer is Aborted.................................................................... 240
7.6.9 Transfer Requests by A/D Converter.................................................................... 240
Section 8 I/O Ports ............................................................................................................... 241
8.1 Overview............................................................................................................................ 241
8.2 Port 4.................................................................................................................................. 244
8.2.1 Overview............................................................................................................... 244
8.2.2 Register Configuration.......................................................................................... 245
8.3 Port 6.................................................................................................................................. 247
8.3.1 Overview............................................................................................................... 247
8.3.2 Register Configuration.......................................................................................... 248

vi
8.4 Port 7.................................................................................................................................. 251
8.4.1 Overview............................................................................................................... 251
8.4.2 Register Configuration.......................................................................................... 252
8.5 Port 8.................................................................................................................................. 253
8.5.1 Overview............................................................................................................... 253
8.5.2 Register Configuration.......................................................................................... 254
8.6 Port 9.................................................................................................................................. 257
8.6.1 Overview............................................................................................................... 257
8.6.2 Register Configuration.......................................................................................... 258
8.7 Port A................................................................................................................................. 261
8.7.1 Overview............................................................................................................... 261
8.7.2 Register Configuration.......................................................................................... 263
8.8 Port B ................................................................................................................................. 272
8.8.1 Overview............................................................................................................... 272
8.8.2 Register Configuration.......................................................................................... 273
Section 9 16-Bit Timer........................................................................................................ 279
9.1 Overview............................................................................................................................ 279
9.1.1 Features................................................................................................................. 279
9.1.2 Block Diagrams.................................................................................................... 282
9.1.3 Pin Configuration.................................................................................................. 285
9.1.4 Register Configuration.......................................................................................... 286
9.2 Register Descriptions......................................................................................................... 288
9.2.1 Timer Start Register (TSTR)................................................................................ 288
9.2.2 Timer Synchro Register (TSNC).......................................................................... 289
9.2.3 Timer Mode Register (TMDR)............................................................................. 290
9.2.4 Timer Interrupt Status Register A (TISRA).......................................................... 292
9.2.5 Timer Interrupt Status Register B (TISRB).......................................................... 295
9.2.6 Timer Interrupt Status Register C (TISRC).......................................................... 298
9.2.7 Timer Counters (16TCNT)................................................................................... 300
9.2.8 General Registers (GRA, GRB)............................................................................ 301
9.2.9 Timer Control Registers (16TCR)........................................................................ 302
9.2.10 Timer I/O Control Register (TIOR)...................................................................... 304
9.2.11 Timer Output Level Setting Register C (TOLR).................................................. 306
9.3 CPU Interface..................................................................................................................... 309
9.3.1 16-Bit Accessible Registers.................................................................................. 309
9.3.2 8-Bit Accessible Registers.................................................................................... 311
9.4 Operation............................................................................................................................ 312
9.4.1 Overview............................................................................................................... 312
9.4.2 Basic Functions..................................................................................................... 312
9.4.3 Synchronization.................................................................................................... 322
9.4.4 PWM Mode .......................................................................................................... 324
9.4.5 Phase Counting Mode........................................................................................... 328

vii
9.4.6 Setting Initial Value of 16-Bit Timer Output........................................................ 330
9.5 Interrupts............................................................................................................................ 331
9.5.1 Setting of Status Flags.......................................................................................... 331
9.5.2 Timing of Clearing of Status Flags....................................................................... 333
9.5.3 Interrupt Sources and DMA Controller Activation.............................................. 334
9.6 Usage Notes ....................................................................................................................... 335
Section 10 8-Bit Timers...................................................................................................... 347
10.1 Overview............................................................................................................................ 347
10.1.1 Features................................................................................................................. 347
10.1.2 Block Diagram...................................................................................................... 349
10.1.3 Pin Configuration.................................................................................................. 350
10.1.4 Register Configuration.......................................................................................... 351
10.2 Register Descriptions......................................................................................................... 352
10.2.1 Timer Counters (8TCNT)..................................................................................... 352
10.2.2 Time Constant Registers A (TCORA).................................................................. 353
10.2.3 Time Constant Registers B (TCORB).................................................................. 354
10.2.4 Timer Control Register (8TCR)............................................................................ 354
10.2.5 Timer Control/Status Registers (8TCSR)............................................................. 357
10.3 CPU Interface..................................................................................................................... 361
10.3.1 8-Bit Registers...................................................................................................... 361
10.4 Operation............................................................................................................................ 363
10.4.1 8TCNT Count Timing .......................................................................................... 363
10.4.2 Compare Match Timing........................................................................................ 364
10.4.3 Input Capture Signal Timing................................................................................ 365
10.4.4 Timing of Status Flag Setting............................................................................... 366
10.4.5 Operation with Cascaded Connection .................................................................. 367
10.4.6 Input Capture Setting............................................................................................ 369
10.5 Interrupt.............................................................................................................................. 371
10.5.1 Interrupt Source.................................................................................................... 371
10.5.2 A/D Converter Activation..................................................................................... 372
10.6 8-Bit Timer Application Example...................................................................................... 372
10.7 Usage Notes ....................................................................................................................... 373
10.7.1 Contention between 8TCNT Write and Clear...................................................... 373
10.7.2 Contention between 8TCNT Write and Increment............................................... 374
10.7.3 Contention between TCOR Write and Compare Match....................................... 375
10.7.4 Contention between TCOR Read and Input Capture............................................ 376
10.7.5 Contention between Counter Clearing by Input Capture and Counter Increment 377
10.7.6 Contention between TCOR Write and Input Capture........................................... 378
10.7.7 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode
(Cascaded Connection)......................................................................................... 379
10.7.8 Contention between Compare Matches A and B.................................................. 380
10.7.9 8TCNT Operation at Internal Clock Source Switchover...................................... 380

viii
Section 11 Programmable Timing Pattern Controller (TPC).................................. 383
11.1 Overview............................................................................................................................ 383
11.1.1 Features................................................................................................................. 383
11.1.2 Block Diagram...................................................................................................... 384
11.1.3 Pin Configuration.................................................................................................. 385
11.1.4 Register Configuration.......................................................................................... 386
11.2 Register Descriptions......................................................................................................... 387
11.2.1 Port A Data Direction Register (PADDR)............................................................ 387
11.2.2 Port A Data Register (PADR)............................................................................... 387
11.2.3 Port B Data Direction Register (PBDDR)............................................................ 388
11.2.4 Port B Data Register (PBDR)............................................................................... 388
11.2.5 Next Data Register A (NDRA)............................................................................. 389
11.2.6 Next Data Register B (NDRB) ............................................................................. 391
11.2.7 Next Data Enable Register A (NDERA).............................................................. 393
11.2.8 Next Data Enable Register B (NDERB)............................................................... 394
11.2.9 TPC Output Control Register (TPCR).................................................................. 395
11.2.10 TPC Output Mode Register (TPMR).................................................................... 398
11.3 Operation............................................................................................................................ 400
11.3.1 Overview............................................................................................................... 400
11.3.2 Output Timing ...................................................................................................... 401
11.3.3 Normal TPC Output.............................................................................................. 402
11.3.4 Non-Overlapping TPC Output.............................................................................. 404
11.3.5 TPC Output Triggering by Input Capture............................................................. 406
11.4 Usage Notes ....................................................................................................................... 407
11.4.1 Operation of TPC Output Pins.............................................................................. 407
11.4.2 Note on Non-Overlapping Output........................................................................ 407
Section 12 Watchdog Timer.............................................................................................. 409
12.1 Overview............................................................................................................................ 409
12.1.1 Features................................................................................................................. 409
12.1.2 Block Diagram...................................................................................................... 410
12.1.3 Pin Configuration.................................................................................................. 410
12.1.4 Register Configuration.......................................................................................... 411
12.2 Register Descriptions......................................................................................................... 412
12.2.1 Timer Counter (TCNT)......................................................................................... 412
12.2.2 Timer Control/Status Register (TCSR) ................................................................ 413
12.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 415
12.2.4 Notes on Register Access...................................................................................... 417
12.3 Operation............................................................................................................................ 419
12.3.1 Watchdog Timer Operation.................................................................................. 419
12.3.2 Interval Timer Operation...................................................................................... 420
12.3.3 Timing of Setting of Overflow Flag (OVF).......................................................... 421
12.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST)................................... 422

ix
12.4 Interrupts............................................................................................................................ 423
12.5 Usage Notes ....................................................................................................................... 423
Section 13 Serial Communication Interface................................................................. 425
13.1 Overview............................................................................................................................ 425
13.1.1 Features................................................................................................................. 425
13.1.2 Block Diagram...................................................................................................... 427
13.1.3 Pin Configuration.................................................................................................. 428
13.1.4 Register Configuration.......................................................................................... 429
13.2 Register Descriptions......................................................................................................... 430
13.2.1 Receive Shift Register (RSR) ............................................................................... 430
13.2.2 Receive Data Register (RDR)............................................................................... 430
13.2.3 Transmit Shift Register (TSR).............................................................................. 431
13.2.4 Transmit Data Register (TDR).............................................................................. 431
13.2.5 Serial Mode Register (SMR)................................................................................ 432
13.2.6 Serial Control Register (SCR).............................................................................. 436
13.2.7 Serial Status Register (SSR) ................................................................................. 440
13.2.8 Bit Rate Register (BRR) ....................................................................................... 446
13.3 Operation............................................................................................................................ 455
13.3.1 Overview............................................................................................................... 455
13.3.2 Operation in Asynchronous Mode........................................................................ 457
13.3.3 Multiprocessor Communication............................................................................ 467
13.3.4 Synchronous Operation ........................................................................................ 473
13.4 SCI Interrupts..................................................................................................................... 482
13.5 Usage Notes ....................................................................................................................... 483
13.5.1 Notes on Use of SCI ............................................................................................. 483
Section 14 Smart Card Interface...................................................................................... 489
14.1 Overview............................................................................................................................ 489
14.1.1 Features................................................................................................................. 489
14.1.2 Block Diagram...................................................................................................... 490
14.1.3 Pin Configuration.................................................................................................. 490
14.1.4 Register Configuration.......................................................................................... 491
14.2 Register Descriptions......................................................................................................... 492
14.2.1 Smart Card Mode Register (SCMR)..................................................................... 492
14.2.2 Serial Status Register (SSR) ................................................................................. 494
14.2.3 Serial Mode Register (SMR)................................................................................ 496
14.2.4 Serial Control Register (SCR).............................................................................. 496
14.3 Operation............................................................................................................................ 497
14.3.1 Overview............................................................................................................... 497
14.3.2 Pin Connections.................................................................................................... 498
14.3.3 Data Format.......................................................................................................... 498
14.3.4 Register Settings ................................................................................................... 500

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14.3.5 Clock..................................................................................................................... 502
14.3.6 Transmitting and Receiving Data ......................................................................... 504
14.4 Usage Notes ....................................................................................................................... 512
Section 15 A/D Converter.................................................................................................. 515
15.1 Overview............................................................................................................................ 515
15.1.1 Features................................................................................................................. 515
15.1.2 Block Diagram...................................................................................................... 516
15.1.3 Pin Configuration.................................................................................................. 517
15.1.4 Register Configuration.......................................................................................... 518
15.2 Register Descriptions......................................................................................................... 519
15.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 519
15.2.2 A/D Control/Status Register (ADCSR)................................................................ 520
15.2.3 A/D Control Register (ADCR) ............................................................................. 523
15.3 CPU Interface..................................................................................................................... 524
15.4 Operation............................................................................................................................ 525
15.4.1 Single Mode (SCAN = 0) ..................................................................................... 525
15.4.2 Scan Mode (SCAN = 1)........................................................................................ 527
15.4.3 Input Sampling and A/D Conversion Time.......................................................... 529
15.4.4 External Trigger Input Timing.............................................................................. 530
15.5 Interrupts............................................................................................................................ 531
15.6 Usage Notes ....................................................................................................................... 531
Section 16 D/A Converter.................................................................................................. 537
16.1 Overview............................................................................................................................ 537
16.1.1 Features................................................................................................................. 537
16.1.2 Block Diagram...................................................................................................... 537
16.1.3 Pin Configuration.................................................................................................. 538
16.1.4 Register Configuration.......................................................................................... 538
16.2 Register Descriptions......................................................................................................... 539
16.2.1 D/A Data Registers 0 and 1 (DADR0/1).............................................................. 539
16.2.2 D/A Control Register (DACR) ............................................................................. 539
16.2.3 D/A Standby Control Register (DASTCR) .......................................................... 541
16.3 Operation............................................................................................................................ 542
16.4 D/A Output Control ........................................................................................................... 544
Section 17 RAM.................................................................................................................... 545
17.1 Overview............................................................................................................................ 545
17.1.1 Block Diagram...................................................................................................... 545
17.1.2 Register Configuration.......................................................................................... 546
17.2 System Control Register (SYSCR).................................................................................... 547
17.3 Operation............................................................................................................................ 548

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Section 18 Clock Pulse Generator................................................................................... 549
18.1 Overview............................................................................................................................ 549
18.1.1 Block Diagram...................................................................................................... 549
18.2 Oscillator Circuit................................................................................................................ 550
18.2.1 Connecting a Crystal Resonator............................................................................ 550
18.2.2 External Clock Input............................................................................................. 552
18.3 Duty Adjustment Circuit.................................................................................................... 555
18.4 Prescalers ........................................................................................................................... 555
18.5 Frequency Divider.............................................................................................................. 555
18.5.1 Register Configuration.......................................................................................... 555
18.5.2 Division Control Register (DIVCR)..................................................................... 555
18.5.3 Usage Notes.......................................................................................................... 556
Section 19 Power-Down State.......................................................................................... 557
19.1 Overview............................................................................................................................ 557
19.2 Register Configuration....................................................................................................... 559
19.2.1 System Control Register (SYSCR)....................................................................... 559
19.2.2 Module Standby Control RegisterH (MSTCRH) ................................................. 561
19.2.3 Module Standby Control Register L (MSTCRL) ................................................. 562
19.3 Sleep Mode ........................................................................................................................ 564
19.3.1 Transition to Sleep Mode...................................................................................... 564
19.3.2 Exit from Sleep Mode........................................................................................... 564
19.4 Software Standby Mode..................................................................................................... 565
19.4.1 Transition to Software Standby Mode.................................................................. 565
19.4.2 Exit from Software Standby Mode....................................................................... 565
19.4.3 Selection of Waiting Time for Exit from Software Standby Mode...................... 566
19.4.4 Sample Application of Software Standby Mode.................................................. 567
19.4.5 Note....................................................................................................................... 567
19.5 Hardware Standby Mode ................................................................................................... 568
19.5.1 Transition to Hardware Standby Mode................................................................. 568
19.5.2 Exit from Hardware Standby Mode...................................................................... 568
19.5.3 Timing for Hardware Standby Mode.................................................................... 568
19.6 Module Standby Function.................................................................................................. 569
19.6.1 Module Standby Timing....................................................................................... 569
19.6.2 Read/Write in Module Standby............................................................................ 569
19.6.3 Usage Notes.......................................................................................................... 569
19.7 System Clock Output Disabling Function ......................................................................... 570
Section 20 Electrical Characteristics.............................................................................. 571
20.1 Absolute Maximum Ratings.............................................................................................. 571
20.2 Electrical Characteristics.................................................................................................... 572
20.2.1 DC Characteristics................................................................................................ 572

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20.2.2 AC Characteristics................................................................................................ 582
20.2.3 A/D Conversion Characteristics ........................................................................... 590
20.2.4 D/A Conversion Characteristics ........................................................................... 592
20.3 Operational Timing............................................................................................................ 593
20.3.1 Clock Timing........................................................................................................ 593
20.3.2 Control Signal Timing.......................................................................................... 594
20.3.3 Bus Timing ........................................................................................................... 596
20.3.4 DRAM Interface Bus Timing ............................................................................... 602
20.3.5 TPC and I/O Port Timing...................................................................................... 605
20.3.6 Timer Input/Output Timing.................................................................................. 606
20.3.7 SCI Input/Output Timing...................................................................................... 607
20.3.8 DMAC Timing...................................................................................................... 608
Appendix A Instruction Set............................................................................................... 609
A.1 Instruction List................................................................................................................... 609
A.2 Operation Code Map ......................................................................................................... 624
A.3 Number of States Required for Execution......................................................................... 627
Appendix B Internal I/O Registers.................................................................................. 636
B.1 Addresses ........................................................................................................................... 636
B.2 Functions............................................................................................................................ 645
Appendix C I/O Port Block Diagrams ........................................................................... 729
C.1 Port 4 Block Diagram........................................................................................................ 729
C.2 Port 6 Block Diagrams....................................................................................................... 730
C.3 Port 7 Block Diagrams....................................................................................................... 734
C.4 Port 8 Block Diagrams....................................................................................................... 735
C.5 Port 9 Block Diagrams....................................................................................................... 739
C.6 Port A Block Diagrams...................................................................................................... 745
C.7 Port B Block Diagrams...................................................................................................... 748
Appendix D Pin States........................................................................................................ 754
D.1 Port States in Each Mode................................................................................................... 754
D.2 Pin States at Reset.............................................................................................................. 760
Appendix E Timing of Transition to and Recovery from Hardware
Standby Mode............................................................................................... 762
Appendix F List of Product Codes................................................................................. 763
Appendix G Package Dimensions................................................................................... 764

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Appendix H Comparison of H8/300H Series Product Specifications.................. 767
H.1 Differences between H8/3067 and H8/3062 Series, H8/3048 Series,
H8/3007 and H8/3006, and H8/3002................................................................................. 767
H.2 Comparison of Pin Functions of 100-Pin Package Products (FP-100B, TFP-100B) ....... 770