Hitachi H8/3006 User manual

H8/3006, H8/3007
HD6413006, HD6413007
Hardware Manual
ADE-602-145C
Rev. 4.0
1/29/00
Hitachi, Ltd.

Cautions
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patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Hitachi bears no responsibility for problems that may arise with third party’s
rights, including intellectual property rights, in connection with use of the information
contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you
have received the latest product standards or specifications before final design, purchase or
use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.
However, contact Hitachi’s sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of
the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi
semiconductor products.

Preface
The H8/3006 and H8/3007 is a series of high-performance microcontrollers that integrate system
supporting functions together with an H8/300H CPU core.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space.
The on-chip supporting functions include RAM, 16-bit timers, 8-bit timers, a programmable
timing pattern controller (TPC), a watchdog timer (WDT), a serial communication interface (SCI),
an A/D converter, a D/A converter, I/O ports, and a DMA controller (DMAC).
The address space is divided into eight areas. The data bus width and access cycle length can be
selected independently in each area, simplifying the connection of different types of memory. Four
MCU operating modes (modes 1 to 4) are provided, offering a choice of data bus width initial
value and address space.
With these features, the H8/3006 and H8/3007 offers easy implementation of compact, high-
performance systems.
This manual describes the H8/3006 and H8/3007 Series hardware. For details of the instruction
set, refer to the H8/300H Series Programming Manual.

List of Items Revised or Added for This Version
Page Item Description
3 1.1 Overview
Table 1-1 Feature Watchdog timer (WDT) Specification description amended
28 2.6.1 Instruction Set Overview Number of instruction
types amended
35 Table 2-7 Bit Manipulation Instructions Function description
added
41 2.6.5 Notes on Use of Bit Manipulation Instruction
Explanation Description added
45 Table 2-13 Effective Address Calculation No. 1 in Addressing Mode
and Instruction Format
column amended
57 Table 3-1 Operating Mode Selection Table amended
57 3.1.1 Operating Mode Selection Description added
70 4.2.2 Reset Sequence Description added
77 5.1.1 Features Description added
144 Figure 6.15 Example of Wait State Insertion Timing Figure amended
175 Figure 6.42 Example of Idle Cycle Operation (2)
(ICIS0 = 1)
(b) Idle cycle inserted
Bus cycle B amended
205 7.4.2 I/O Mode Description added
Table 7.6 Register Functions in I/O Mode Description added
207 7.4.3 Idle Mode Description added
208 Table 7.7 Register Functions in Idle Mode Description added
210 7.4.4 Repeat Mode Description added
211 Table 7.8 Register Functions in Repeat Mode Description added
226 7.4.8 DMAC Bus Cycle Note added
248 8.3.2 Register Configuration
Port 6 Data Direction Register (P6DDR) Description amended
249 8.3.2 Register Configuration
Port 6 Data Register (P6DR) Description amended
253 8.5.1 Overview Reference changed
Figure 8.4 Port 8 Pin Configuration Description added
254 8.5.2 Register Configuration
Port 8 Data Direction Register (P8DDR) Description amended

Page Item Description
255 8.5.2 Register Configuration
Port 8 Data Register (P8DR) Description amended
258 8.6.2 Register Configuration
Port 9 Data Direction Register (P9DDR) Description amended
263 8.7.2 Register Configuration
Port A Data Direction Register (PADDR) Description amended
272 Figure 8.7 Port B Pin Configuration Description added
273 8.8.2 Register Configuration
Port B Data Direction Register (PBDDR) Description amended
279 to 346 Section 9 16-Bit Timers Register names changed
TCNT →16TCNT
TCR →16TCR
347 to 382 Section 10 8-Bit Timers Register names changed
TCNT →8TCNT
TCR →8TCR
TCSR →8TCSR
351 Table 10.2 8-Bit Timer Register 8TCSR2 initial value
changed
355 10.2.4 Timer Control Register (8TCR)
Bits 4 and 3 Description amended
358 10.2.5 Timer Control/Status Registers (8TCSR)
Bit 4 Description added
411 Table 12.2 WDT Registers Note 3 added
462 Figure 13.5 Sample Flowchart for Transmitting Serial
Data Description added to (1)
502 Table 14.5 Bit Rates (bit/s) for Various BRR Settings
(When n = 0) 20.00 MHz value added
503 Table 14.6 BRR Settings for Typical Bit Rates (bits/s)
(When n = 0) 20.00 MHz value added
Table 14.7 Maximum Bit Rate for Various Frequencies
(Smart Card Interface Mode) 20.00 MHz value added
511 Figure 14.10 Procedure for Stopping and Restarting
the Clock Restart procedure amended
554 Figure 18.7 External Clock Output Setting Delay
Timing Figure amended
556 18.5.3 Usage Notes Text of 1st note amended
640, 641 B.1 Addresses Register names amended

Page Item Description
647 B.2 Functions
P8DDR—Port 8 Data Direction Register Note deleted
680 B.2 Functions
TSTR—Timer Start Register Description amended
681 B.2 Functions
TSNC—Timer Syncro Register Description amended
682 B.2 Functions
TMDR—Timer Mode Register Description amended
684 B.2 Functions
TISRA—Timer Interrupt Status Register A Description amended
685 B.2 Function
TISRB—Timer Interrupt Status Register B Description amended
686 B.2 Functions
TISRC—Timer Interrupt Status Register C Description amended
687 B.2 Functions
16TCR0—Timer Control Register 0 Register name changed
689 B.2 Functions
16TCNT0H/L—Timer Counter 0H/L Register name changed
690 B.2 Functions
16TCR1—Timer Control Register 1 Register name changed
B.2 Function
16TCNT1H/L—Timer Counter 1H/L Register name changed
691 B.2 Functions
16TCR2—Timer Control Register 2 Register name changed
692 B.2 Functions
16TCNT2H/L—Timer Counter 2H/L Register name changed
694 B.2 Functions
8TCR0—Timer Control Register 0
8TCR1—Timer Control Register 1
Register names changed,
description amended
695 B.2 Functions
8TCSR0—Timer Control/Status Register 0 Register names changed, description amended
696 B.2 Functions
8TCSR1—Timer Control/Status Register 1 Register names changed, description amended
697 B.2 Functions
8TCNT0—Timer Counter 0
8TCNT1—Timer Counter 1
Register names changed
700 B.2 Functions
8TCR2—Timer Control Register 2
8TCR3—Timer Control Register 3
Register names changed,
description amended

Page Item Description
701 B.2 Functions
8TCSR2—Timer Control/Status Register 2
8TCSR3—Timer Control/Status Register 3
Register names changed,
description amended
702 B.2 Functions
8TCNT2—Timer Counter 2
8TCNT3—Timer Counter 3
Register name changed
723 B.2 Functions
P6DR—Port 6 Data Register Description amended
729 Figure C.1 Port 4 Block Diagram Figure amended
730 to 732 Figure C.2(a) to Figure C.2(c)
Port 6 Block Diagram Figure amended
735 to 738 Figure C.4(a) to Figure C.4(d)
Port 8 Block Diagram Figure amended
739 to 744 Figure C.5(a) to Figure C.5(f)
Port 8 Block Diagram Figure amended
745 to 747 Figure C.6(a) to Figure C.6(c)
Port A Block Diagram Figure amended
748 to 753 Figure C.7(a) to Figure C.7(f)
Port B Block Diagram Figure amended

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Contents
Section 1 Overview.............................................................................................................. 1
1.1 Overview............................................................................................................................ 1
1.2 Internal Block Diagram...................................................................................................... 5
1.3 Pin Description................................................................................................................... 6
1.3.1 Pin Arrangement................................................................................................... 6
1.3.2 Pin Functions........................................................................................................ 8
1.3.3 Pin Assignments in Each Mode............................................................................ 13
Section 2 CPU........................................................................................................................ 17
2.1 Overview............................................................................................................................ 17
2.1.1 Features................................................................................................................. 17
2.1.2 Differences from H8/300 CPU ............................................................................. 18
2.2 CPU Operating Modes....................................................................................................... 19
2.3 Address Space.................................................................................................................... 20
2.4 Register Configuration.......................................................................................................21
2.4.1 Overview............................................................................................................... 21
2.4.2 General Registers.................................................................................................. 22
2.4.3 Control Registers.................................................................................................. 23
2.4.4 Initial CPU Register Values.................................................................................. 24
2.5 Data Formats...................................................................................................................... 25
2.5.1 General Register Data Formats............................................................................. 25
2.5.2 Memory Data Formats.......................................................................................... 26
2.6 Instruction Set.................................................................................................................... 28
2.6.1 Instruction Set Overview...................................................................................... 28
2.6.2 Instructions and Addressing Modes...................................................................... 29
2.6.3 Tables of Instructions Classified by Function...................................................... 30
2.6.4 Basic Instruction Formats..................................................................................... 39
2.6.5 Notes on Use of Bit Manipulation Instructions.................................................... 40
2.7 Addressing Modes and Effective Address Calculation...................................................... 42
2.7.1 Addressing Modes................................................................................................ 42
2.7.2 Effective Address Calculation.............................................................................. 44
2.8 Processing States................................................................................................................ 48
2.8.1 Overview............................................................................................................... 48
2.8.2 Program Execution State ...................................................................................... 49
2.8.3 Exception-Handling State..................................................................................... 49
2.8.4 Exception-Handling Sequences............................................................................ 51
2.8.5 Bus-Released State................................................................................................ 52
2.8.6 Reset State ............................................................................................................ 52
2.8.7 Power-Down State................................................................................................ 52

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2.9 Basic Operational Timing.................................................................................................. 53
2.9.1 Overview............................................................................................................... 53
2.9.2 On-Chip Memory Access Timing ........................................................................ 53
2.9.3 On-Chip Supporting Module Access Timing....................................................... 54
2.9.4 Access to External Address Space........................................................................ 55
Section 3 MCU Operating Modes................................................................................... 57
3.1 Overview............................................................................................................................ 57
3.1.1 Operating Mode Selection.................................................................................... 57
3.1.2 Register Configration............................................................................................ 58
3.2 Mode Control Register (MDCR) ....................................................................................... 58
3.3 System Control Register (SYSCR).................................................................................... 59
3.4 Operating Mode Descriptions............................................................................................ 62
3.4.1 Mode 1.................................................................................................................. 62
3.4.2 Mode 2.................................................................................................................. 62
3.4.3 Mode 3.................................................................................................................. 62
3.4.4 Mode 4.................................................................................................................. 62
3.5 Pin Functions in Each Operating Mode............................................................................. 63
3.6 Memory Map in Each Operating Mode............................................................................. 63
3.6.1 Note on Reserved Areas........................................................................................ 63
Section 4 Exception Handling.......................................................................................... 67
4.1 Overview............................................................................................................................ 67
4.1.1 Exception Handling Types and Priority................................................................ 67
4.1.2 Exception Handling Operation ............................................................................. 67
4.1.3 Exception Vector Table........................................................................................ 68
4.2 Reset................................................................................................................................... 70
4.2.1 Overview............................................................................................................... 70
4.2.2 Reset Sequence ..................................................................................................... 70
4.2.3 Interrupts after Reset............................................................................................. 72
4.3 Interrupts............................................................................................................................ 73
4.4 Trap Instruction.................................................................................................................. 73
4.5 Stack Status after Exception Handling .............................................................................. 74
4.6 Notes on Stack Usage ........................................................................................................ 74
Section 5 Interrupt Controller........................................................................................... 77
5.1 Overview............................................................................................................................ 77
5.1.1 Features................................................................................................................. 77
5.1.2 Block Diagram...................................................................................................... 78
5.1.3 Pin Configuration.................................................................................................. 79
5.1.4 Register Configuration.......................................................................................... 79
5.2 Register Descriptions......................................................................................................... 80
5.2.1 System Control Register (SYSCR)....................................................................... 80

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5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) ............................................. 81
5.2.3 IRQ Status Register (ISR) .................................................................................... 88
5.2.4 IRQ Enable Register (IER)................................................................................... 89
5.2.5 IRQ Sense Control Register (ISCR)..................................................................... 90
5.3 Interrupt Sources................................................................................................................ 91
5.3.1 External Interrupts................................................................................................ 91
5.3.2 Internal Interrupts.................................................................................................. 92
5.3.3 Interrupt Vector Table .......................................................................................... 92
5.4 Interrupt Operation............................................................................................................. 96
5.4.1 Interrupt Handling Process ................................................................................... 96
5.4.2 Interrupt Sequence................................................................................................ 101
5.4.3 Interrupt Response Time....................................................................................... 102
5.5 Usage Notes ....................................................................................................................... 103
5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction...................... 103
5.5.2 Instructions that Inhibit Interrupts........................................................................ 104
5.5.3 Interrupts during EEPMOV Instruction Execution .............................................. 104
Section 6 Bus Controller.................................................................................................... 105
6.1 Overview............................................................................................................................ 105
6.1.1 Features................................................................................................................. 105
6.1.2 Block Diagram...................................................................................................... 107
6.1.3 Pin Configuration.................................................................................................. 108
6.1.4 Register Configuration.......................................................................................... 109
6.2 Register Descriptions......................................................................................................... 110
6.2.1 Bus Width Control Register (ABWCR) ............................................................... 110
6.2.2 Access State Control Register (ASTCR).............................................................. 111
6.2.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 111
6.2.4 Bus Release Control Register (BRCR)................................................................. 115
6.2.5 Bus Control Register (BCR)................................................................................. 116
6.2.6 Chip Select Control Register (CSCR) .................................................................. 118
6.2.7 DRAM Control Register A (DRCRA).................................................................. 119
6.2.8 DRAM Control Register B (DRCRB).................................................................. 121
6.2.9 Refresh Timer Control/Status Register (RTMCSR)............................................. 124
6.2.10 Refresh Timer Counter (RTCNT) ........................................................................ 125
6.2.11 Refresh Time Constant Register (RTCOR).......................................................... 126
6.3 Operation............................................................................................................................ 127
6.3.1 Area Division........................................................................................................ 127
6.3.2 Bus Specifications ................................................................................................ 129
6.3.3 Memory Interfaces................................................................................................ 130
6.3.4 Chip Select Signals............................................................................................... 130
6.4 Basic Bus Interface............................................................................................................ 132
6.4.1 Overview............................................................................................................... 132
6.4.2 Data Size and Data Alignment.............................................................................. 132