Hitachi H8/3827R Series User manual

H8/3827R Series
H8/3827R HD6473827R, HD6433827R
H8/3826R HD6433826R
H8/3825R HD6433825R
H8/3824R HD6433824R
H8/3823R HD6433823R
H8/3822R HD6433822R
Hardware Manual
ADE-602-196
Rev. 1.0
9/15/99
Hitachi Ltd.

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However, contact Hitachi’s sales office before using the product in an application that
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semiconductor products.

i
Preface
The H8/300L Series of single-chip microcomputers has the high-speed H8/300L CPU at its core,
with many necessary peripheral functions on-chip. The H8/300L CPU instruction set is
compatible with the H8/300 CPU.
The H8/3827R Series has a system-on-a-chip architecture that includes such peripheral functions
as a as an LCD controller/driver, six timers, a 14-bit PWM, a two-channel serial communication
interface, and an A/D converter. This allows H8/3827R Series devices to be used as embedded
microcomputers in systems requiring LCD display.
This manual describes the hardware of the H8/3827R Series. For details on the instruction set,
refer to the H8/300L Series Programming Manual.

ii
Contents
Section 1 Overview............................................................................................................ 1
1.1 Overview............................................................................................................................ 1
1.2 Internal Block Diagram...................................................................................................... 6
1.3 Pin Arrangement and Functions......................................................................................... 7
1.3.1 Pin Arrangement................................................................................................... 7
1.3.2 Pin Functions........................................................................................................ 9
Section 2 CPU..................................................................................................................... 13
2.1 Overview............................................................................................................................ 13
2.1.1 Features................................................................................................................. 13
2.1.2 Address Space....................................................................................................... 14
2.1.3 Register Configuration.......................................................................................... 14
2.2 Register Descriptions......................................................................................................... 15
2.2.1 General Registers.................................................................................................. 15
2.2.2 Control Registers.................................................................................................. 15
2.2.3 Initial Register Values .......................................................................................... 16
2.3 Data Formats...................................................................................................................... 17
2.3.1 Data Formats in General Registers....................................................................... 18
2.3.2 Memory Data Formats.......................................................................................... 19
2.4 Addressing Modes.............................................................................................................. 20
2.4.1 Addressing Modes................................................................................................ 20
2.4.2 Effective Address Calculation.............................................................................. 22
2.5 Instruction Set.................................................................................................................... 26
2.5.1 Data Transfer Instructions .................................................................................... 28
2.5.2 Arithmetic Operations .......................................................................................... 30
2.5.3 Logic Operations .................................................................................................. 31
2.5.4 Shift Operations.................................................................................................... 31
2.5.5 Bit Manipulations ................................................................................................. 33
2.5.6 Branching Instructions.......................................................................................... 37
2.5.7 System Control Instructions.................................................................................. 39
2.5.8 Block Data Transfer Instruction............................................................................ 40
2.6 Basic Operational Timing.................................................................................................. 42
2.6.1 Access to On-Chip Memory (RAM, ROM) ......................................................... 42
2.6.2 Access to On-Chip Peripheral Modules................................................................ 43
2.7 CPU States ......................................................................................................................... 45
2.7.1 Overview............................................................................................................... 45
2.7.2 Program Execution State ...................................................................................... 46
2.7.3 Program Halt State................................................................................................ 46
2.7.4 Exception-Handling State..................................................................................... 46

iii
2.8 Memory Map...................................................................................................................... 47
2.8.1 Memory Map........................................................................................................ 47
2.9 Application Notes .............................................................................................................. 53
2.9.1 Notes on Data Access ........................................................................................... 53
2.9.2 Notes on Bit Manipulation.................................................................................... 55
2.9.3 Notes on Use of the EEPMOV Instruction........................................................... 61
Section 3 Exception Handling........................................................................................ 63
3.1 Overview............................................................................................................................ 63
3.2 Reset................................................................................................................................... 63
3.2.1 Overview............................................................................................................... 63
3.2.2 Reset Sequence ..................................................................................................... 63
3.2.3 Interrupt Immediately after Reset......................................................................... 65
3.3 Interrupts............................................................................................................................ 65
3.3.1 Overview............................................................................................................... 65
3.3.2 Interrupt Control Registers ................................................................................... 67
3.3.3 External Interrupts................................................................................................ 76
3.3.4 Internal Interrupts.................................................................................................. 77
3.3.5 Interrupt Operations.............................................................................................. 78
3.3.6 Interrupt Response Time....................................................................................... 83
3.4 Application Notes .............................................................................................................. 84
3.4.1 Notes on Stack Area Use...................................................................................... 84
3.4.2 Notes on Rewriting Port Mode Registers ............................................................. 85
Section 4 Clock Pulse Generators................................................................................. 87
4.1 Overview............................................................................................................................ 87
4.1.1 Block Diagram...................................................................................................... 87
4.1.2 System Clock and Subclock.................................................................................. 87
4.2 System Clock Generator.................................................................................................... 88
4.3 Subclock Generator............................................................................................................ 91
4.4 Prescalers ........................................................................................................................... 93
4.5 Note on Oscillators ............................................................................................................ 94
Section 5 Power-Down Modes ...................................................................................... 95
5.1 Overview............................................................................................................................ 95
5.1.1 System Control Registers...................................................................................... 98
5.2 Sleep Mode ........................................................................................................................ 102
5.2.1 Transition to Sleep Mode...................................................................................... 102
5.2.2 Clearing Sleep Mode ............................................................................................ 103
5.2.3 Clock Frequency in Sleep (Medium-Speed) Mode.............................................. 103
5.3 Standby Mode.................................................................................................................... 103
5.3.1 Transition to Standby Mode.................................................................................. 103
5.3.2 Clearing Standby Mode........................................................................................ 104

iv
5.3.3 Oscillator Settling Time after Standby Mode is Cleared...................................... 105
5.3.4 Standby Mode Transition and Pin States.............................................................. 106
5.3.5 Notes on External Input Signal Changes before/after Standby Mode.................. 106
5.4 Watch Mode....................................................................................................................... 108
5.4.1 Transition to Watch Mode.................................................................................... 108
5.4.2 Clearing Watch Mode........................................................................................... 108
5.4.3 Oscillator Settling Time after Watch Mode is Cleared ........................................ 108
5.4.4 Notes on External Input Signal Changes before/after Watch Mode..................... 108
5.5 Subsleep Mode................................................................................................................... 109
5.5.1 Transition to Subsleep Mode................................................................................ 109
5.5.2 Clearing Subsleep Mode....................................................................................... 109
5.6 Subactive Mode.................................................................................................................. 110
5.6.1 Transition to Subactive Mode............................................................................... 110
5.6.2 Clearing Subactive Mode...................................................................................... 110
5.6.3 Operating Frequency in Subactive Mode ............................................................. 110
5.7 Active (Medium-Speed) Mode.......................................................................................... 111
5.7.1 Transition to Active (Medium-Speed) Mode........................................................ 111
5.7.2 Clearing Active (Medium-Speed) Mode.............................................................. 111
5.7.3 Operating Frequency in Active (Medium-Speed) Mode...................................... 111
5.8 Direct Transfer................................................................................................................... 112
5.8.1 Overview of Direct Transfer................................................................................. 112
5.8.2 Direct Transition Times........................................................................................ 113
5.8.3 Notes on External Input Signal Changes before/after Direct Transition.............. 115
5.9 Module Standby Mode....................................................................................................... 116
5.9.1 Setting Module Standby Mode ............................................................................. 116
5.9.2 Clearing Module Standby Mode........................................................................... 116
Section 6 ROM.................................................................................................................... 119
6.1 Overview............................................................................................................................ 119
6.1.1 Block Diagram...................................................................................................... 119
6.2 H8/3827R PROM Mode.................................................................................................... 120
6.2.1 Setting to PROM Mode........................................................................................ 120
6.2.2 Socket Adapter Pin Arrangement and Memory Map ........................................... 120
6.3 H8/3827R Programming.................................................................................................... 123
6.3.1 Writing and Verifying........................................................................................... 123
6.3.2 Programming Precautions..................................................................................... 128
6.4 Reliability of Programmed Data........................................................................................ 129
Section 7 RAM.................................................................................................................... 131
7.1 Overview............................................................................................................................ 131
7.1.1 Block Diagram...................................................................................................... 131

v
Section 8 I/O Ports............................................................................................................. 133
8.1 Overview............................................................................................................................ 133
8.2 Port 1.................................................................................................................................. 135
8.2.1 Overview............................................................................................................... 135
8.2.2 Register Configuration and Description ............................................................... 135
8.2.3 Pin Functions........................................................................................................ 140
8.2.4 Pin States .............................................................................................................. 142
8.2.5 MOS Input Pull-Up............................................................................................... 142
8.3 Port 3.................................................................................................................................. 143
8.3.1 Overview............................................................................................................... 143
8.3.2 Register Configuration and Description ............................................................... 143
8.3.3 Pin Functions........................................................................................................ 147
8.3.4 Pin States .............................................................................................................. 149
8.3.5 MOS Input Pull-Up............................................................................................... 149
8.4 Port 4.................................................................................................................................. 150
8.4.1 Overview............................................................................................................... 150
8.4.2 Register Configuration and Description ............................................................... 150
8.4.3 Pin Functions........................................................................................................ 151
8.4.4 Pin States............................................................................................................... 152
8.5 Port 5.................................................................................................................................. 153
8.5.1 Overview............................................................................................................... 153
8.5.2 Register Configuration and Description ............................................................... 153
8.5.3 Pin Functions........................................................................................................ 156
8.5.4 Pin States .............................................................................................................. 156
8.5.5 MOS Input Pull-Up............................................................................................... 157
8.6 Port 6.................................................................................................................................. 157
8.6.1 Overview............................................................................................................... 157
8.6.2 Register Configuration and Description ............................................................... 158
8.6.3 Pin Functions........................................................................................................ 159
8.6.4 Pin States .............................................................................................................. 159
8.6.5 MOS Input Pull-Up............................................................................................... 160
8.7 Port 7.................................................................................................................................. 160
8.7.1 Overview............................................................................................................... 160
8.7.2 Register Configuration and Description ............................................................... 161
8.7.3 Pin Functions........................................................................................................ 162
8.7.4 Pin States .............................................................................................................. 162
8.8 Port 8.................................................................................................................................. 163
8.8.1 Overview............................................................................................................... 163
8.8.2 Register Configuration and Description ............................................................... 163
8.8.3 Pin Functions........................................................................................................ 165
8.8.4 Pin States .............................................................................................................. 166

vi
8.9 Port A................................................................................................................................. 166
8.9.1 Overview............................................................................................................... 166
8.9.2 Register Configuration and Description ............................................................... 167
8.9.3 Pin Functions........................................................................................................ 168
8.9.4 Pin States .............................................................................................................. 169
8.10 Port B ................................................................................................................................. 169
8.10.1 Overview............................................................................................................... 169
8.10.2 Register Configuration and Description ............................................................... 170
8.11 Input/Output Data Inversion Function............................................................................... 170
8.11.1 Overview............................................................................................................... 170
8.11.2 Register Configuration and Descriptions.............................................................. 171
8.11.3 Note on Modification of Serial Port Control Register.......................................... 173
Section 9 Timers................................................................................................................. 175
9.1 Overview............................................................................................................................ 175
9.2 Timer A.............................................................................................................................. 176
9.2.1 Overview............................................................................................................... 176
9.2.2 Register Descriptions............................................................................................ 178
9.2.3 Timer Operation.................................................................................................... 182
9.2.4 Timer A Operation States ..................................................................................... 183
9.3 Timer C.............................................................................................................................. 184
9.3.1 Overview............................................................................................................... 184
9.3.2 Register Descriptions............................................................................................ 186
9.3.3 Timer Operation.................................................................................................... 190
9.3.4 Timer C Operation States...................................................................................... 192
9.4 Timer F............................................................................................................................... 193
9.4.1 Overview............................................................................................................... 193
9.4.2 Register Descriptions............................................................................................ 196
9.4.3 CPU Interface........................................................................................................ 203
9.4.4 Operation .............................................................................................................. 206
9.4.5 Application Notes ................................................................................................. 209
9.5 Timer G.............................................................................................................................. 210
9.5.1 Overview............................................................................................................... 210
9.5.2 Register Descriptions............................................................................................ 213
9.5.3 Noise Canceler...................................................................................................... 218
9.5.4 Operation .............................................................................................................. 220
9.5.5 Application Notes ................................................................................................. 224
9.5.6 Timer G Application Example.............................................................................. 229
9.6 Watchdog Timer ................................................................................................................ 230
9.6.1 Overview............................................................................................................... 230
9.6.2 Register Descriptions............................................................................................ 231
9.6.3 Timer Operation.................................................................................................... 235
9.6.4 Watchdog Timer Operation States........................................................................ 236

vii
9.7 Asynchronous Event Counter (AEC)................................................................................. 237
9.7.1 Overview............................................................................................................... 237
9.7.2 Register Descriptions............................................................................................ 239
9.7.3 Operation .............................................................................................................. 244
9.7.4 Asynchronous Event Counter Operation Modes.................................................. 245
9.7.5 Application Notes ................................................................................................. 246
Section 10 Serial Communication Interface................................................................. 247
10.1 Overview............................................................................................................................ 247
10.1.1 Features................................................................................................................. 247
10.1.2 Block diagram....................................................................................................... 249
10.1.3 Pin configuration .................................................................................................. 250
10.1.4 Register configuration .......................................................................................... 250
10.2 Register Descriptions......................................................................................................... 251
10.2.1 Receive shift register (RSR) ................................................................................. 251
10.2.2 Receive data register (RDR)................................................................................. 251
10.2.3 Transmit shift register (TSR)................................................................................ 252
10.2.4 Transmit data register (TDR)................................................................................ 252
10.2.5 Serial mode register (SMR).................................................................................. 253
10.2.6 Serial control register 3 (SCR3)............................................................................ 256
10.2.7 Serial status register (SSR) ................................................................................... 260
10.2.8 Bit rate register (BRR).......................................................................................... 264
10.2.9 Clock stop register 1 (CKSTPR1) ........................................................................ 268
10.2.10 Serial Port Control Register (SPCR) .................................................................... 269
10.3 Operation............................................................................................................................ 271
10.3.1 Overview............................................................................................................... 271
10.3.2 Operation in Asynchronous Mode........................................................................ 275
10.3.3 Operation in Synchronous Mode.......................................................................... 284
10.3.4 Multiprocessor Communication Function............................................................ 291
10.4 Interrupts............................................................................................................................ 298
10.5 Application Notes .............................................................................................................. 299
Section 11 14-Bit PWM...................................................................................................... 305
11.1 Overview............................................................................................................................ 305
11.1.1 Features................................................................................................................. 305
11.1.2 Block Diagram...................................................................................................... 305
11.1.3 Pin Configuration.................................................................................................. 306
11.1.4 Register Configuration.......................................................................................... 306
11.2 Register Descriptions......................................................................................................... 307
11.2.1 PWM Control Register (PWCR).......................................................................... 307
11.2.2 PWM Data Registers U and L (PWDRU, PWDRL)............................................ 308
11.2.3 Clock Stop Register 2 (CKSTPR2) ...................................................................... 308

viii
11.3 Operation............................................................................................................................ 309
11.3.1 Operation .............................................................................................................. 309
11.3.2 PWM Operation Modes........................................................................................ 310
Section 12 A/D Converter.................................................................................................. 311
12.1 Overview............................................................................................................................ 311
12.1.1 Features................................................................................................................. 311
12.1.2 Block Diagram...................................................................................................... 312
12.1.3 Pin Configuration.................................................................................................. 313
12.1.4 Register Configuration.......................................................................................... 313
12.2 Register Descriptions......................................................................................................... 314
12.2.1 A/D Result Registers (ADRRH, ADRRL) ........................................................... 314
12.2.2 A/D Mode Register (AMR).................................................................................. 314
12.2.3 A/D Start Register (ADSR).................................................................................. 316
12.2.4 Clock Stop Register 1 (CKSTPR1) ...................................................................... 317
12.3 Operation............................................................................................................................ 318
12.3.1 A/D Conversion Operation................................................................................... 318
12.3.2 Start of A/D Conversion by External Trigger Input ............................................. 318
12.3.3 A/D Converter Operation Modes.......................................................................... 319
12.4 Interrupts............................................................................................................................ 319
12.5 Typical Use........................................................................................................................ 319
12.6 Application Notes .............................................................................................................. 322
Section 13 LCD Controller/Driver.................................................................................. 323
13.1 Overview............................................................................................................................ 323
13.1.1 Features................................................................................................................. 323
13.1.2 Block Diagram...................................................................................................... 324
13.1.3 Pin Configuration.................................................................................................. 325
13.1.4 Register Configuration.......................................................................................... 325
13.2 Register Descriptions......................................................................................................... 326
13.2.1 LCD Port Control Register (LPCR)...................................................................... 326
13.2.2 LCD Control Register (LCR)................................................................................ 328
13.2.3 LCD Control Register 2 (LCR2) .......................................................................... 330
13.2.4 Clock Stop Register 2 (CKSTPR2) ...................................................................... 332
13.3 Operation............................................................................................................................ 333
13.3.1 Settings up to LCD Display.................................................................................. 333
13.3.2 Relationship between LCD RAM and Display .................................................... 336
13.3.3 Luminance Adjustment Function (V0Pin)............................................................ 343
13.3.4 Low-Power-Consumption LCD Drive System..................................................... 343
13.3.5 Operation in Power-Down Modes........................................................................ 348
13.3.6 Boosting the LCD Drive Power Supply................................................................ 349
13.3.7 Connection to HD66100....................................................................................... 350

ix
Section 14 Power Supply Circuit..................................................................................... 353
14.1 Overview............................................................................................................................ 353
14.2 When Using the Internal Power Supply Step-Down Circuit.............................................. 353
14.3 When Not Using the Internal Power Supply Step-Down Circuit...................................... 354
Section 15 Electrical Characteristics.............................................................................. 355
15.1 H8/3827R Series Absolute Maximum Ratings.................................................................. 355
15.2 H8/3827R Series Electrical Characteristics....................................................................... 356
15.2.1 Power Supply Voltage and Operating Range ....................................................... 356
15.2.2 DC Characteristics................................................................................................ 359
15.2.3 AC Characteristics................................................................................................ 365
15.2.4 A/D Converter Characteristics.............................................................................. 368
15.2.5 LCD Characteristics.............................................................................................. 370
15.3 Operation Timing............................................................................................................... 372
15.4 Output Load Circuit ........................................................................................................... 376
15.5 Resonator Equivalent Circuit............................................................................................. 376
Appendix A CPU Instruction Set .................................................................................... 377
A.1 Instructions......................................................................................................................... 377
A.2 Operation Code Map.......................................................................................................... 385
A.3 Number of Execution States .............................................................................................. 387
Appendix B Internal I/O Registers.................................................................................. 393
B.1 Addresses ........................................................................................................................... 393
B.2 Functions............................................................................................................................ 397
Appendix C I/O Port Block Diagrams ........................................................................... 448
C.1 Block Diagrams of Port 1 .................................................................................................. 448
C.2 Block Diagrams of Port 3 .................................................................................................. 451
C.3 Block Diagrams of Port 4 .................................................................................................. 458
C.4 Block Diagram of Port 5.................................................................................................... 462
C.5 Block Diagram of Port 6.................................................................................................... 463
C.6 Block Diagram of Port 7.................................................................................................... 464
C.7 Block Diagrams of Port 8 .................................................................................................. 465
C.8 Block Diagram of Port A................................................................................................... 466
C.9 Block Diagram of Port B ................................................................................................... 467
Appendix D Port States in the Different Processing States..................................... 468
Appendix E List of Product Codes.................................................................................. 469
Appendix F Package Dimensions.................................................................................... 471

1
Section 1 Overview
1.1 Overview
The H8/300L Series is a series of single-chip microcomputers (MCU: microcomputer unit), built
around the high-speed H8/300L CPU and equipped with peripheral system functions on-chip.
Within the H8/300L Series, the H8/3827R Series comprises single-chip microcomputers equipped
with an LCD (liquid crystal display) controller/driver. Other on-chip peripheral functions include
six timers, a 14-bit pulse width modulator (PWM), two serial communication interface channels,
and an A/D converter. Together, these functions make the H8/3827R Series ideally suited for
embedded applications in systems requiring low power consumption and LCD display. Models in
the H8/3827R Series are the H8/3822R, with on-chip 16-kbyte ROM and 1-kbyte RAM, the
H8/3823R, with 24-kbyte ROM and 1-kbyte RAM, the H8/3824R, with 32-kbyte ROM and 2-
kbyte RAM, the H8/3825R, with 40-kbyte ROM and 2-kbyte RAM, the H8/3826R, with 48-kbyte
ROM and 2-kbyte RAM, and the H8/3827R, with 60-kbyte ROM and 2-kbyte RAM.
The H8/3827R is also available in a ZTAT™* version with on-chip PROM which can be
programmed as required by the user.
Table 1.1 summarizes the features of the H8/3827R Series.
Note: * ZTAT (Zero Turn Around Time) is a trademark of Hitachi, Ltd.

2
Table 1.1 Features
Item Description
CPU High-speed H8/300L CPU
• General-register architecture
General registers: Sixteen 8-bit registers (can be used as eight 16-bit
registers)
• Operating speed
 Max. operating speed: 8 MHz
 Add/subtract: 0.25 µs (operating at 8 MHz)
 Multiply/divide: 1.75 µs (operating at 8 MHz)
 Can run on 32.768 kHz or 38.4 kHz subclock
• Instruction set compatible with H8/300 CPU
 Instruction length of 2 bytes or 4 bytes
 Basic arithmetic operations between registers
 MOV instruction for data transfer between memory and registers
• Typical instructions
 Multiply (8 bits ×8 bits)
 Divide (16 bits ÷8 bits)
 Bit accumulator
 Register-indirect designation of bit position
Interrupts 36 interrupt sources
• 13 external interrupt sources (IRQ4to IRQ0, WKP7to WKP0)
• 23 internal interrupt sources
Clock pulse generators Two on-chip clock pulse generators
• System clock pulse generator: 1 to 16 MHz
• Subclock pulse generator: 32.768 kHz, 38.4 kHz
Power-down modes Seven power-down modes
• Sleep (high-speed) mode
• Sleep (medium-speed) mode
• Standby mode
• Watch mode
• Subsleep mode
• Subactive mode
• Active (medium-speed) mode

3
Table 1.1 Features (cont)
Item Description
Memory Large on-chip memory
• H8/3822R: 16-kbyte ROM, 1-kbyte RAM
• H8/3823R: 24-kbyte ROM, 1-kbyte RAM
• H8/3824R: 32-kbyte ROM, 2-kbyte RAM
• H8/3825R: 40-kbyte ROM, 2-kbyte RAM
• H8/3826R: 48-kbyte ROM, 2-kbyte RAM
• H8/3827R: 60-kbyte ROM, 2-kbyte RAM
I/O ports 64 pins
• 55 I/O pins
• 9 input pins
Timers Six on-chip timers
• Timer A: 8-bit timer
Count-up timer with selection of eight internal clock signals divided
from the system clock (ø)*and four clock signals divided from the
watch clock (øw)*
• Asynchronous event counter: 16-bit timer
 Count-up timer able to count asynchronous external events
independently of the MCU's internal clocks
• Timer C: 8-bit timer
 Count-up/down timer with selection of seven internal clock signals
or event input from external pin
 Auto-reloading
• Timer F: 16-bit timer
 Can be used as two independent 8-bit timers
 Count-up timer with selection of four internal clock signals or event
input from external pin
 Provision for toggle output by means of compare-match function
• Timer G: 8-bit timer
 Count-up timer with selection of four internal clock signals
 Incorporates input capture function (built-in noise canceler)
• Watchdog timer
 Reset signal generated by overflow of 8-bit counter
Note: *See section 4, Clock Pulse Generator, for the definition of ø and øw.

4
Table 1.1 Features (cont)
Item Description
Serial communication
interface Two serial communication interface channels on chip
• SCI3-1: 8-bit synchronous/asynchronous serial interface
Incorporates multiprocessor communication function
• SCI3-2: 8-bit synchronous/asynchronous serial interface
Incorporates multiprocessor communication function
14-bit PWM Pulse-division PWM output for reduced ripple
• Can be used as a 14-bit D/A converter by connecting to an external
low-pass filter.
A/D converter Successive approximations using a resistance ladder
• 8-channel analog input pins
• Conversion time: 31/ø or 62/ø per channel
LCD controller/driver LCD controller/driver equipped with a maximum of 32 segment pins and
four common pins
• Choice of four duty cycles (static, 1/2, 1/3, or 1/4)
• Segment pins can be switched to general-purpose port function in 8-
bit units

5
Table 1.1 Features (cont)
Item Specification
Product lineup Product Code
Mask ROM
Version ZTAT Version Package ROM/RAM Size
HD6433822RH — 80-pin QFP (FP-80A) ROM 16 kbytes
HD6433822RF — 80-pin QFP (FP-80B) RAM 1 kbyte
HD6433822RW — 80-pin TQFP (TFP-80C)
HD6433823RH — 80-pin QFP (FP-80A) ROM 24 kbytes
HD6433823RF — 80-pin QFP (FP-80B) RAM 1 kbyte
HD6433823RW — 80-pin TQFP (TFP-80C)
HD6433824RH — 80-pin QFP (FP-80A) ROM 32 kbytes
HD6433824RF — 80-pin QFP (FP-80B) RAM 2 kbytes
HD6433824RW — 80-pin TQFP (TFP-80C)
HD6433825RH — 80-pin QFP (FP-80A) ROM 40 kbytes
HD6433825RF — 80-pin QFP (FP-80B) RAM 2 kbytes
HD6433825RW — 80-pin TQFP (TFP-80C)
HD6433826RH — 80-pin QFP (FP-80A) ROM 48 kbytes
HD6433826RF — 80-pin QFP (FP-80B) RAM 2 kbytes
HD6433826RW — 80-pin TQFP (TFP-80C)
HD6433827RH HD6473827RH 80-pin QFP (FP-80A) ROM 60 kbytes
HD6433827RF HD6473827RF 80-pin QFP (FP-80B) RAM 2 kbytes
HD6433827RW HD6473827RW 80-pin TQFP (TFP-80C)

6
1.2 Internal Block Diagram
Figure 1.1 shows a block diagram of the H8/3827R Series.
P1 0 /TMOW
P1
1 /TMOFL
P1
2 /TMOFH
P1
3 /TMIG 
P1 4 /IRQ 4 /ADTRG
P1
5 /IRQ 1 /TMIC
P1
6 /IRQ 2
P1 7 /IRQ 3 /TMIF
P3 0 /PWM
P3
1 /UD
P3
2 /RESO
P3
3 /SCK 31
P3 4 /RXD 31
P3 5 /TXD 31
P3 6 /AEVH
P3
7 /AEVL
P5 0 /WKP 0 /SEG 1
P5 1 /WKP 1 /SEG 2
P5 2 /WKP 2 /SEG 3
P5 3 /WKP 3 /SEG 4
P5 4 /WKP 4 /SEG 5
P5 5 /WKP 5 /SEG 6
P5 6 /WKP 6 /SEG 7
P5 7 /WKP 7 /SEG 8
P4 0 /SCK 32
P4 1 /RXD 32
P4 2 /TXD 32
P4 3 /IRQ 0
OSC
1
OSC
2
System Clock
OSC
Port 1
Port APort 8Port 7Port 6
Port 3Port 4Port 5
X
1
X
2
Sub Clock
OSC
V
SS
V
SS
V
CC
CV
CC
RES TEST
H8/300L
CPU
LCD Power
Supply
ROM
(60k/48k/40k/32k
24k/16k)
RAM
(2k/1k)
Timer - A
Timer - C
Timer - F
Timer - G
Asynchronous
counter
Serial
communication
interface 3-1
Serial
communication
interface 3-2
14-bit
PWM
WDT
LCD
Controller
A/D
(10bit)
V 0
V 1
V 2
V 3
PA 3 /COM 4
PA 2 /COM 3
PA 1 /COM 2
PA 0 /COM 1
P8 7 /SEG 32 /CL 1
P8 6 /SEG 31 /CL 2
P8 5 /SEG 30 /DO
P8
4 /SEG 29 /M
P8
3 /SEG 28
P8 2 /SEG 27
P8 1 /SEG 26
P8 0 /SEG 25
P7 7 /SEG 24
P7 6 /SEG 23
P7 5 /SEG 22
P7 4 /SEG 21
P7 3 /SEG 20
P7 2 /SEG 19
P7 1 /SEG 18
P7 0 /SEG 17
P6 7 /SEG 16
P6 6 /SEG 15
P6 5 /SEG 14
P6 4 /SEG 13
P6 3 /SEG 12
P6 2 /SEG 11
P6 1 /SEG 10
P6 0 /SEG 9
Port B
AV
CC
AV
SS
PB
0
/AN
0
PB
1
/AN
1
PB
2
/AN
2
PB
3
/AN
3
PB
4
/AN
4
PB
5
/AN
5
PB
6
/AN
6
PB
7
/AN
7
Figure 1.1 Block Diagram

7
1.3 Pin Arrangement and Functions
1.3.1 Pin Arrangement
The H8/3827R Series pin arrangement is shown in figures 1.2 and 1.3.
P7
7
/SEG24
P7
6
/SEG23
P7
5
/SEG22
P7
4
/SEG21
P7
3
/SEG20
P7
2
/SEG19
P7
1
/SEG18
P7
0
/SEG17
P6
7
/SEG16
P6
6
/SEG15
P6
5
/SEG14
P6
4
/SEG13
P6
3
/SEG12
P6
2
/SEG11
P6
1
/SEG10
P6
0
/SEG9
P5
7
/WKP
7
/SEG8
P5
6
/WKP
6
/SEG7
P5
5
/WKP
5
/SEG6
P5
4
/WKP
4
/SEG5
P8 0 /SEG25
P8
1 /SEG26
P8
2 /SEG27
P8
3 /SEG28
P8
4 /SEG29/M
P8
5 /SEG30/DO
P8
6 /SEG31CL 2
P8 7 /SEG32CL 1
P4 0/ SCK 32
P4 1 /RXD 32
P4 2 /TXD 32
P4 3 /IRQ 0
AV CC
PB 0 /AN 0
PB 1 /AN 1
PB 2 /AN 2
PB 3 /AN 3
PB 4 /AN 4
PB 5 /AN 5
PB 6 /AN 6
PB
7
/AN
7
AV
SS
X1 X2
V
SS
OSC2 OSC1
TEST
RES
P1
0
/TMOW
P1
1
/TMOFL
P1
2
/TMOFH
P1
3
/TMIG
P1
4
/IRQ
4
/ADTRG
P1
5
/IRQ
1
/TMIC
P1
6
/IRQ
2
P1
7
/IRQ
3
/TMIF
P3
0
/PWM
P3
1
/UD
P3
2
/RESO
P5 3 /WKP 3 /SEG4
P5
2 /WKP 2 /SEG3
P5
1 /WKP 1 /SEG2
P5
0 /WKP 0 /SEG1
PA
0 /COM1
PA
1 /COM2
PA
2 /COM3
PA
3 /COM4
V
CC
V0
V1
V2
V3
V
SS
CV CC
P3 7 /AEVL
P3
6 /AEVH
P3
5 /TXD 31
P3 4 /RXD 31
P3 3 /SCK 31
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
123456789
10 11 12 13 14 15 16 17 18 19 20
Figure 1.2 Pin Arrangement (FP-80A, TFP-80C: Top View)

8
PB
5
/AN
5
PB
6
/AN
6
PB
7
/AN
7
AV
SS
X1 X2
V
SS
OSC2 OSC1
TEST
RES
P1
0
/TMOW
P1
1
/TMOFL
P1
2
/TMOFH
P1
3
/TMIG
P1
4
/IRQ
4
/ADTRG
P1
5
/IRQ
1
/TMIC
P1
6
/IRQ
2
P1
7
/IRQ
3
/TMIF
P3
0
/PWM
P3
1
/UD
P3
2
/RESO
P3
3
/SCK
31
P3
4
/RXD
31
54
P8
1
/SEG26
P8
0
/SEG25
P7
7
/SEG24
P7
6
/SEG23
P7
5
/SEG22
P7
4
/SEG21
P7
3
/SEG20
P7
2
/SEG19
P7
1
/SEG18
P7
0
/SEG17
P6
7
/SEG16
P6
6
/SEG15
P6
5
/SEG14
P6
4
/SEG13
P6
3
/SEG12
P6
2
/SEG11
P6
1
/SEG10
P6
0
/SEG9
P5
7
/WKP
7
/SEG8
P5
6
/WKP
6
/SEG7
P5
5
/WKP
5
/SEG6
P5
4
/WKP
4
/SEG5
P5
3
/WKP
3
/SEG4
P5
2
/WKP
2
/SEG3
P8 2 /SEG27
P8
3 /SEG28
P8
4 /SEG29/M
P8
5 /SEG30/DO
P8
6 /SEG31/CL 2
P8 7 /SEG32/CL 1
P4 0 /SCK 32
P4 1 /RXD 32
P4 2 /TXD 32
P4 3 /IRQ 0
AV CC
PB 0 /AN 0
PB 1 /AN 1
PB 2 /AN 2
PB 3 /AN 3
PB 4 /AN 4
P5 1 /WKP 1 /SEG2
P5
0 /WKP 0 /SEG1
PA
0 /COM1
PA
1 /COM2
PA
2 /COM3
PA
3 /COM4
V
CC
V0
V1
V2
V3
V
SS
CV CC
P3 7 /AEVL
P3
6 /AEVH
P3
5 /TXD 31
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
64 63 62 61 60 59 58 57 56 55 53 52 51 50 49 48 47 46 45 44 43 42 41
1 2 3 4 5 6 7 8 9101112131415161718192021222324
Figure 1.3 Pin Arrangement (FP-80B: Top View)

9
1.3.2 Pin Functions
Table 1.2 outlines the pin functions of the H8/3827R Series.
Table 1.2 Pin Functions
Pin No.
Type Symbol FP-80A TFP-80C FP-80B I/O Name and Functions
Power
source pins VCC
CVCC
32
26 34 28 Input Power supply: All VCC pins should be connected to the system power supply.
See section 14, Power Supply Circuit.
VSS 5
27 7 29 Input Ground: All VSS pins should be connected to the system power supply
(0 V).
AVCC 73 75 Input Analog power supply: This is the
power supply pin for the A/D converter.
When the A/D converter is not used,
connect this pin to the system power
supply.
AVSS 2 4 Input Analog ground: This is the A/D
converter ground pin. It should be
connected to the system power supply
(0V).
V031 33 Output LCD power supply: These are the
V1
V2
V3
30
29
28
32
31
30
Input power supply pins for the LCD
controller/driver. They incorporate a
power supply split-resistance, and are
normally used with V0and V1shorted.
Clock pins OSC17 9 Input These pins connect to a crystal or
OSC26 8 Output ceramic oscillator, or can be used to
input an external clock. See section 4,
Clock Pulse Generators, for a typical
connection diagram.
X13 5 Input These pins connect to a 32.768-kHz or
X24 6 Output 38.4-kHz crystal oscillator.
See section 4, Clock Pulse
Generators, for a typical connection
diagram.
System
control RES 9 11 Input Reset: When this pin is driven low, the chip is reset
RESO 20 22 Output Reset output: Outputs the CPU internal
reset signal.