Hitachi SH7709S User manual

To all our customers
Regarding the change of names mentioned in the document, such as
Hitachi Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were
transferred to Renesas Technology Corporation on April 1st 2003.
These operations include microcomputer, logic, analog and discrete devices,
and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors,
and other Hitachi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp.
Thank you for your understanding. Except for our corporate trademark,
logo and corporate statement, no changes whatsoever have been made to the
contents of the document, and these changes do not constitute any alteration
to the contents of the document itself.
Renesas Technology Home Page: www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
Renesas Technology Corp.
查询HD6417709供应商 捷多邦，专业PCB打样工厂，24小时加急出货

Hitachi SuperH™ RISC engine
SH7709S
Hardware Manual
ADE-602-250
Rev. 1.0
09/21/01
Hitachi, Ltd.

Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s
patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Hitachi bears no responsibility for problems that may arise with third party’s
rights, including intellectual property rights, in connection with use of the information
contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you
have received the latest product standards or specifications before final design, purchase or
use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.
However, contact Hitachi’s sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of
the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi
semiconductor products.

Preface
This LSI is a microprocessor with the 32-bit SH-3 CPU as its core and peripheral functions
necessary for configuring a user system.
This LSI is built in with a variety of peripheral functions such as cache memory, memory
management unit (MMU), interrupt controller, timer, three serial communication interfaces, real-
time clock (RTC), use break controller (UBC), bus state controller (BSC) and I/O ports.
This LSI can be used as a microcomputer for devices that require both high speed and low power
consumption.
Target Readers: This manual is designed for use by people who design application systems using
the SH7709S.
To use this manual, basic knowledge of electric circuits, logic circuits and microcomputers is
required.
Purpose: This manual provides the information of the hardware functions and electrical
characteristics of the SH7709S.
The SH3, SH-3E, SH3-DSP Programming Manual contains detailed information of executable
instructions. Please read the Programming Manual together with this manual.
How to Use the Book:
• To understand general functions
 Read the manuala from the beginning.
The manual explains the CPU, system control functions, peripheral functions and electrical
characteristics in that order.
• To understanding CPU functions
 Refer to the separate SH3, SH-3E, SH3-DSP Programming Manual.
Explanatory Note: Bit sequence: upper bit at left, and lower bit at right
List of Related Documents: The latest documents are available on our Web site. Please make
sure that you have the latest version.
(http://www.hitachi.co.jp/Sicd/English/Products/micome.htm
• User manuals for SH7709S
Name of Document Document No.
SH7709S Series Hardware Manual This manual
SH3, SH-3E, SH3-DSP Programming Manual ADE-602-156

• User manuals for development tools
Name of Document Document No.
C/C++ Compiler, Assembler, Optimizing Linkage Editor User’s Manual ADE-702-246
Simulator/Debugger User’s Manual ADE-702-186
Hitachi Embedded Workshop User’s Manual ADE-702-201
• Application note
Name of Document Document No.
C/C++ Compiler Guide ADE-xxx-xxx

i
Contents
Section 1 Overview and Pin Functions........................................................................ 1
1.1 SH7709S Features.............................................................................................................. 1
1.2 Block Diagram.................................................................................................................... 6
1.3 Pin Description................................................................................................................... 7
1.3.1 Pin Assignment ..................................................................................................... 7
1.3.2 Pin Function.......................................................................................................... 9
Section 2 CPU...................................................................................................................... 19
2.1 Register Configuration .......................................................................................................19
2.1.1 Privileged Mode and Banks.................................................................................. 19
2.1.2 General Registers.................................................................................................. 22
2.1.3 System Registers ................................................................................................... 23
2.1.4 Control Registers................................................................................................... 23
2.2 Data Formats ...................................................................................................................... 25
2.2.1 Data Format in Registers....................................................................................... 25
2.2.2 Data Format in Memory........................................................................................ 25
2.3 Instruction Features............................................................................................................ 26
2.3.1 Execution Environment......................................................................................... 26
2.3.2 Addressing Modes ................................................................................................ 28
2.3.3 Instruction Formats ............................................................................................... 32
2.4 Instruction Set .................................................................................................................... 35
2.4.1 Instruction Set Classified by Function.................................................................. 35
2.4.2 Instruction Code Map............................................................................................ 51
2.5 Processor States and Processor Modes............................................................................... 54
2.5.1 Processor States..................................................................................................... 54
2.5.2 Processor Modes ................................................................................................... 55
Section 3 Memory Management Unit (MMU).......................................................... 57
3.1 Overview............................................................................................................................ 57
3.1.1 Features ................................................................................................................. 57
3.1.2 Role of MMU........................................................................................................ 57
3.1.3 SH7709S MMU .................................................................................................... 60
3.1.4 Register Configuration.......................................................................................... 65
3.2 Register Description........................................................................................................... 65
3.3 TLB Functions.................................................................................................................... 67
3.3.1 Configuration of the TLB...................................................................................... 67
3.3.2 TLB Indexing........................................................................................................ 69
3.3.3 TLB Address Comparison .................................................................................... 70
3.3.4 Page Management Information............................................................................. 72

ii
3.4 MMU Functions ................................................................................................................. 73
3.4.1 MMU Hardware Management.............................................................................. 73
3.4.2 MMU Software Management................................................................................ 73
3.4.3 MMU Instruction (LDTLB).................................................................................. 74
3.4.4 Avoiding Synonym Problems ............................................................................... 76
3.5 MMU Exceptions ...............................................................................................................78
3.5.1 TLB Miss Exception ............................................................................................. 78
3.5.2 TLB Protection Violation Exception .................................................................... 79
3.5.3 TLB Invalid Exception.......................................................................................... 80
3.5.4 Initial Page Write Exception ................................................................................. 81
3.5.5 Processing Flow in Event of MMU Exception
(Same Processing Flow for Address Error) .......................................................... 83
3.6 Configuration of Memory-Mapped TLB............................................................................ 84
3.6.1 Data Array............................................................................................................. 85
3.6.2 Usage Examples.................................................................................................... 87
3.7 Usage Note ......................................................................................................................... 87
Section 4 Exception Handling........................................................................................ 89
4.1 Overview............................................................................................................................ 89
4.1.1 Features ................................................................................................................. 89
4.1.2 Register Configuration.......................................................................................... 89
4.2 Exception Handling Function............................................................................................. 89
4.2.1 Exception Handling Flow...................................................................................... 89
4.2.2 Exception Vector Addresses ................................................................................. 90
4.2.3 Acceptance of Exceptions..................................................................................... 92
4.2.4 Exception Codes.................................................................................................... 94
4.2.5 Exception Request Masks ..................................................................................... 95
4.2.6 Returning from Exception Handling..................................................................... 95
4.3 Register Descriptions.......................................................................................................... 96
4.4 Exception Handling Operation........................................................................................... 97
4.4.1 Reset......................................................................................................................97
4.4.2 Interrupts ............................................................................................................... 97
4.4.3 General Exceptions ............................................................................................... 98
4.5 Individual Exception Operations........................................................................................ 98
4.5.1 Resets .................................................................................................................... 98
4.5.2 General Exceptions ............................................................................................... 99
4.5.3 Interrupts ............................................................................................................... 102
4.6 Cautions.............................................................................................................................. 104
Section 5 Cache................................................................................................................... 107
5.1 Overview............................................................................................................................ 107
5.1.1 Features ................................................................................................................. 107
5.1.2 Cache Structure ..................................................................................................... 107

iii
5.1.3 Register Configuration.......................................................................................... 109
5.2 Register Description........................................................................................................... 109
5.2.1 Cache Control Register (CCR).............................................................................. 109
5.2.2 Cache Control Register 2 (CCR2) ........................................................................ 110
5.3 Cache Operation................................................................................................................. 113
5.3.1 Searching the Cache.............................................................................................. 113
5.3.2 Read Access.......................................................................................................... 115
5.3.3 Prefetch Operation ................................................................................................ 115
5.3.4 Write Access ......................................................................................................... 115
5.3.5 Write-Back Buffer................................................................................................. 115
5.3.6 Coherency of Cache and External Memory.......................................................... 116
5.4 Memory-Mapped Cache..................................................................................................... 116
5.4.1 Address Array ....................................................................................................... 116
5.4.2 Data Array............................................................................................................. 117
5.4.3 Examples of Usage................................................................................................ 119
Section 6 Interrupt Controller (INTC).......................................................................... 121
6.1 Overview............................................................................................................................ 121
6.1.1 Features ................................................................................................................. 121
6.1.2 Block Diagram...................................................................................................... 122
6.1.3 Pin Configuration.................................................................................................. 123
6.1.4 Register Configuration.......................................................................................... 124
6.2 Interrupt Sources ................................................................................................................ 125
6.2.1 NMI Interrupt........................................................................................................ 125
6.2.2 IRQ Interrupts ....................................................................................................... 125
6.2.3 IRL Interrupts........................................................................................................ 126
6.2.4 PINT Interrupts ..................................................................................................... 128
6.2.5 On-Chip Peripheral Module Interrupts ................................................................. 128
6.2.6 Interrupt Exception Handling and Priority............................................................ 129
6.3 INTC Registers................................................................................................................... 135
6.3.1 Interrupt Priority Registers A to E (IPRA–IPRE)................................................. 135
6.3.2 Interrupt Control Register 0 (ICR0)...................................................................... 136
6.3.3 Interrupt Control Register 1 (ICR1)...................................................................... 137
6.3.4 Interrupt Control Register 2 (ICR2)...................................................................... 140
6.3.5 PINT Interrupt Enable Register (PINTER)........................................................... 141
6.3.6 Interrupt Request Register 0 (IRR0) ..................................................................... 142
6.3.7 Interrupt Request Register 1 (IRR1) ..................................................................... 144
6.3.8 Interrupt Request Register 2 (IRR2) ..................................................................... 145
6.4 INTC Operation.................................................................................................................. 147
6.4.1 Interrupt Sequence ................................................................................................ 147
6.4.2 Multiple Interrupts ................................................................................................ 149
6.5 Interrupt Response Time......................................................................................................... 149

iv
Section 7 User Break Controller.................................................................................... 153
7.1 Overview............................................................................................................................ 153
7.1.1 Features ................................................................................................................. 153
7.1.2 Block Diagram...................................................................................................... 154
7.1.3 Register Configuration.......................................................................................... 155
7.2 Register Descriptions.......................................................................................................... 156
7.2.1 Break Address Register A (BARA)...................................................................... 156
7.2.2 Break Address Mask Register A (BAMRA)......................................................... 157
7.2.3 Break Bus Cycle Register A (BBRA)................................................................... 158
7.2.4 Break Address Register B (BARB) ...................................................................... 160
7.2.5 Break Address Mask Register B (BAMRB)......................................................... 161
7.2.6 Break Data Register B (BDRB)............................................................................ 162
7.2.7 Break Data Mask Register B (BDMRB)............................................................... 163
7.2.8 Break Bus Cycle Register B (BBRB) ................................................................... 164
7.2.9 Break Control Register (BRCR) ........................................................................... 166
7.2.10 Execution Times Break Register (BETR)............................................................. 170
7.2.11 Branch Source Register (BRSR)........................................................................... 171
7.2.12 Branch Destination Register (BRDR)................................................................... 172
7.2.13 Break ASID Register A (BASRA)........................................................................ 173
7.2.14 Break ASID Register B (BASRB)........................................................................ 173
7.3 Operation Description ........................................................................................................ 174
7.3.1 Flow of the User Break Operation........................................................................ 174
7.3.2 Break on Instruction Fetch Cycle.......................................................................... 175
7.3.3 Break by Data Access Cycle................................................................................. 175
7.3.4 Sequential Break ................................................................................................... 176
7.3.5 Value of Saved Program Counter.......................................................................... 176
7.3.6 PC Trace................................................................................................................ 177
7.3.7 Usage Examples.................................................................................................... 178
7.3.8 Notes...................................................................................................................... 182
Section 8 Power-Down Modes....................................................................................... 185
8.1 Overview............................................................................................................................ 185
8.1.1 Power-Down Modes.............................................................................................. 185
8.1.2 Pin Configuration.................................................................................................. 187
8.1.3 Register Configuration.......................................................................................... 187
8.2 Register Descriptions.......................................................................................................... 187
8.2.1 Standby Control Register (STBCR)...................................................................... 187
8.2.2 Standby Control Register 2 (STBCR2)................................................................. 189
8.3 Sleep Mode......................................................................................................................... 191
8.3.1 Transition to Sleep Mode...................................................................................... 191
8.3.2 Canceling Sleep Mode .......................................................................................... 191
8.4 Standby Mode .................................................................................................................... 192
8.4.1 Transition to Standby Mode.................................................................................. 192

v
8.4.2 Canceling Standby Mode...................................................................................... 193
8.4.3 Clock Pause Function............................................................................................ 194
8.5 Module Standby Function.................................................................................................. 195
8.5.1 Transition to Module Standby Function................................................................ 195
8.5.2 Clearing Module Standby Function...................................................................... 195
8.6 Timing of STATUS Pin Changes....................................................................................... 196
8.6.1 Timing for Resets.................................................................................................. 196
8.6.2 Timing for Canceling Standby.............................................................................. 198
8.6.3 Timing for Canceling Sleep Mode........................................................................ 200
8.7 Hardware Standby Mode.................................................................................................... 203
8.7.1 Transition to Hardware Standby Mode................................................................. 203
8.7.2 Canceling Hardware Standby Mode...................................................................... 204
8.7.3 Hardware Standby Mode Timing.......................................................................... 204
Section 9 On-Chip Oscillation Circuits ....................................................................... 207
9.1 Overview............................................................................................................................ 207
9.1.1 Features ................................................................................................................. 207
9.2 Overview of CPG............................................................................................................... 208
9.2.1 CPG Block Diagram.............................................................................................. 208
9.2.2 CPG Pin Configuration ......................................................................................... 210
9.2.3 CPG Register Configuration ................................................................................. 210
9.3 Clock Operating Modes...................................................................................................... 211
9.4 Register Descriptions.......................................................................................................... 215
9.4.1 Frequency Control Register (FRQCR).................................................................. 215
9.5 Changing the Frequency..................................................................................................... 217
9.5.1 Changing the Multiplication Rate ......................................................................... 217
9.5.2 Changing the Division Ratio................................................................................. 217
9.6 Overview of WDT.............................................................................................................. 218
9.6.1 Block Diagram of WDT........................................................................................ 218
9.6.2 Register Configuration.......................................................................................... 218
9.7 WDTRegisters.................................................................................................................... 219
9.7.1 Watchdog Timer Counter (WTCNT).................................................................... 219
9.7.2 Watchdog Timer Control/Status Register (WTCSR)............................................ 219
9.7.3 Notes on Register Access...................................................................................... 221
9.8 Using the WDT .................................................................................................................. 222
9.8.1 Canceling Standby ................................................................................................ 222
9.8.2 Changing the Frequency........................................................................................ 222
9.8.3 Using Watchdog Timer Mode............................................................................... 223
9.8.4 Using Interval Timer Mode................................................................................... 223
9.9 Notes on Board Design ...................................................................................................... 224
Section 10 Bus State Controller (BSC).......................................................................... 227
10.1 Overview............................................................................................................................ 227