Holtek HT46R46 User manual

HT46R46/C46/R47/C47/R48A/C48A/R49
Cost-Effective A/D Type 8-Bit MCU
Rev. 1.41 1 December 30, 2008
General Description
The Cost-Effective A/D Type MCU Devices are a series
of 8-bit high performance RISC architecture
microcontrollers, designed especially for applications
that interface directly to analog signals, such as those
from sensors. All devices include an integrated
multi-channel Analog to Digital Converter in addition to
one or two Pulse Width Modulation outputs. The usual
Holtek MCU features such as power down and wake-up
functions, oscillator options, programmable frequency
divider, etc. combine to ensure user applications require
a minimum of external components.
The benefits of integrated A/D and PWM functions, in
addition to low power consumption, high performance,
I/O flexibility and low-cost, provide these devices with
the versatility to suit a wide range of application possibil-
ities such as sensor signal processing, motor driving, in-
dustrial control, consumer products, subsystem
controllers, etc. Many features are common to all de-
vices, however, they differ in areas such as I/O pin
count, Program Memory capacity, A/D resolution, stack
capacity and package types.
Features
·Operating voltage:
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
·13 to 23 bidirectional I/O lines
·External interrupt input shared with an I/O line
·8-bit programmable Timer/Event Counter with over-
flow interrupt and 7-stage prescaler
·On-chip crystal and RC oscillator
·Watchdog Timer function
·PFD for audio frequency generation
·Power down and wake-up functions to reduce power
consumption
·Up to 0.5ms instruction cycle with 8MHz system clock
at VDD=5V
·4 or 6-level subroutine nesting
·4 channels 8 or 9-bit resolution A/D converter
·1 or 2 channel 8-bit PWM output shared with I/O lines
·Bit manipulation instruction
·Table read instructions
·63 powerful instructions
·All instructions executed in one or two machine
cycles
·Low voltage reset function
·Range of packaging types

Part No. VDD Program
Memory
Data
Memory I/O Timer Int. A/D PWM Stack Package Types
HT46R46
HT46C46
2.2V~
5.5V 1K´14 64´813 8-bit´138-bit´4 8-bit´1416NSOP, 18DIP/SOP, 20SSOP
HT46R47
HT46C47
2.2V~
5.5V 2K´14 64´813 8-bit´139-bit´4 8-bit´1616NSOP, 18DIP/SOP, 20SSOP
HT46R48A
HT46C48A
2.2V~
5.5V 2K´14 88´819 8-bit´139-bit´4 8-bit´1620DIP/SOP, 24SKDIP/SOP/SSOP
HT46R49 2.2V~
5.5V 4K´15 128´823 8-bit´139-bit´4 8-bit´2620DIP/SOP, 24/28SKDIP/SOP
Note: Part numbers including ²C²are mask version devices, ²R²are OTP devices.
For devices that exist in two package formats, the table reflects the situation for the larger package.
Block Diagram
Note: This block diagram represents the OTP devices, for the mask devices there is no Device Programming
Circuitry.
HT46R46/C46/R47/C47/R48A/C48A/R49
Rev. 1.41 2 December 30, 2008
T i m i n g
G e n e r a t o r
S y s t e m R C /
X ' t a l O s c i l l a t o r I n s t r u c t i o n
D ecoder
I n s t r u c t i o n
R e g i s t e r
W D T
O s c i l l a t o r
D a t a
M e m o r y
A d d r e s s D e c o d e r
M e m o r y
P o i n t e r
M X A C C
Look-up
T a b l e
R e g i s t e r
R e s e t &
L V R
C o n f i g .
R e g i s t e r
T i m e r /
C ounter
C o n f i g .
R e g i s t e r
I n t e r r u p t
C i r c u i t
C o n f i g .
R e g i s t e r
I/O
P o r t s
D e v i c e
P r o g r a m m i n g
C i r c u i t r y
C o n f i g u r a t i o n
O p t i o n
P r o g r a m
M e m o r y
A d d r e s s D e c o d e r
S t a c k
S t a c k P o i n t e r
P r o g r a m
C o u n t e r
Look-up
T a b l e
P o i n t e r
T o P r o g r a m
M e m o r y
A L
S h i f t e r
MX
C o n f i g .
R e g i s t e r
P W M
P F D
A / D
C o n v e r t e r
Device Types
Devices which have the letter ²R²within their part number, indicate that they are OTP devices offering the advantages
of easy and effective program updates, using the Holtek range of development and programming tools. These devices
provide the designer with the means for fast and low-cost product development cycles. Devices which have the letter
²C²within their part number indicate that they are mask version devices. These devices offer a complementary device
for applications that are at a mature state in their design process and have high volume and low cost demands.
Fully pin and functionally compatible with their OTP sister devices, the mask version devices provide the ideal substi-
tute for products which have gone beyond their development cycle and are facing cost-down demands.
In this datasheet, for convenience, when describing device functions, only the OTP types are mentioned by name,
however the same described functions also apply to the Mask type devices.
Selection Table
Most features are common to all devices, the main feature distinguishing them are Program Memory capacity, I/O
count, A/D resolution, stack capacity and package types. The following table summarises the main features of each de-
vice.

Pin Assignment
Pin Description
HT46R46, HT46R47
Pin Name I/O Configuration
Option Description
PA0~PA2
PA3/PFD
PA4/TMR
PA5/INT
PA6~PA7
I/O
Pull-high
Wake-up
PA3 or PFD
Bidirectional 8-bit input/output port. Each individual pin on this port can be config-
ured as a wake-up input by a configuration option. Software instructions determine
if the pin is a CMOS output or Schmitt Trigger input. Configuration options deter-
mine which pins on the port have pull-high resistors. Pins PA3, PA4 and PA5 are
pin-shared with PFD, TMR and INT, respectively.
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
I/O Pull-high
Bidirectional 4-bit input/output port. Software instructions determine if the pin is a
CMOS output or Schmitt Trigger input. Configuration options determine which pins
on the port have pull-high resistors. PB is pin-shared with the A/D input pins. The
A/D inputs are selected via software instructions. Once selected as an A/D input,
the I/O function and pull-high resistor options are disabled automatically.
PD0/PWM I/O Pull-high
PD0 or PWM
Bidirectional 1-bit input/output port. Software instructions determine if the pin is a
CMOS output or Schmitt Trigger input.
A configuration option determines if this pin has a pull-high resistor. The PWM out-
put is pin-shared with pin PD0 selected via a configuration option.
OSC1
OSC2
I
O
Crystal
or RC
OSC1, OSC2 are connected to an external RC network or external crystal, deter-
mined by configuration option, for the internal system clock. If the RC system clock op-
tion is selected, pin OSC2 can be used to measure the system clock at 1/4 frequency.
RES I ¾Schmitt Trigger reset input. Active low.
VDD ¾¾
Positive power supply
VSS ¾¾
Negative power supply, ground
Note: 1. Each pin on PA can be programmed through a configuration option to have a wake-up function.
2. Individual pins can be selected to have a pull-high resistor.
3. Pins PB2/AN2~PB3/AN3 exist but are not bonded out on the 16-pin package.
4. unbonded pins should be setup as outputs or as inputs with pull-high resistors to conserve power.
HT46R46/C46/R47/C47/R48A/C48A/R49
Rev. 1.41 3 December 30, 2008
H T 4 6 R 4 6 / H T 4 6 C 4 6
H T 4 6 R 4 7 / H T 4 6 C 4 7
2 0 S S O P - A
P A 4 / T M R
P A 5 / I N T
P A 6
P A 7
O S C 2
O S C 1
V D D
R E S
P D 0 / P W M
N C
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
1
2
3
4
5
6
7
8
9
1 0
P A 3 / P F D
P A 2
P A 1
P A 0
P B 3 / A N 3
N C
P B 2 / A N 2
P B 1 / A N 1
P B 0 / A N 0
V S S
H T 4 6 R 4 6 / H T 4 6 C 4 6
H T 4 6 R 4 7 / H T 4 6 C 4 7
1 8 D I P - A / S O P - A
P A 4 / T M R
P A 5 / I N T
P A 6
P A 7
O S C 2
O S C 1
V D D
R E S
P D 0 / P W M
P A 3 / P F D
P A 2
P A 1
P A 0
P B 3 / A N 3
P B 2 / A N 2
P B 1 / A N 1
P B 0 / A N 0
V S S
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
1 0
1
2
3
4
5
6
7
8
9
H T 4 6 R 4 8 A / H T 4 6 C 4 8 A
2 0 D I P - A / S O P - A
P B 5
P A 4 / T M R
P A 5 / I N T
P A 6
P A 7
O S C 2
O S C 1
V D D
R E S
P D 0 / P W M
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
1
2
3
4
5
6
7
8
9
1 0
P B 4
P A 3 / P F D
P A 2
P A 1
P A 0
P B 3 / A N 3
P B 2 / A N 2
P B 1 / A N 1
P B 0 / A N 0
V S S
H T 4 6 R 4 8 A / H T 4 6 C 4 8 A
2 4 S K D I P - A / S O P - A / S S O P - A
PB5
PB4
P A 3 / P F D
PA2
PA1
PA0
P B 3 / A N 3
P B 2 / A N 2
P B 1 / A N 1
P B 0 / A N 0
VSS
P C 0
PB6
P B 7
P A 4 / T M R
P A 5 / I N T
PA6
PA7
O S C 2
O S C 1
V D D
R E S
P D 0 / P W M
P C 1
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
H T 4 6 R 4 9
2 8 S K D I P - A / S O P - A
PB6
PB7
P A 4 / T M R
P A 5 / I N T
PA6
PA7
O S C 2
O S C 1
V D D
R E S
P D 1 / P W M 1
P D 0 / P W M 0
P C 4
P C 3
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
PB5
PB4
P A 3 / P F D
PA2
PA1
PA0
P B 3 / A N 3
P B 2 / A N 2
P B 1 / A N 1
P B 0 / A N 0
VSS
P C 0
P C 1
PC 2
PB5
PB4
P A 3 / P F D
PA2
PA1
PA0
P B 3 / A N 3
P B 2 / A N 2
P B 1 / A N 1
P B 0 / A N 0
VSS
P C 0
PB6
PB7
P A 4 / T M R
P A 5 / I N T
PA6
PA7
O S C 2
O S C 1
V D D
R E S
P D 1 / P W M 1
P D 0 / P W M 0
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
H T 4 6 R 4 9
2 4 S K D I P - B / S O P - B
H T 4 6 R 4 6 / H T 4 6 C 4 6
H T 4 6 R 4 7 / H T 4 6 C 4 7
1 6 N S O P - A
P A 4 / T M R
P A 5 / I N T
P A 6
P A 7
O S C 2
O S C 1
V D D
R E S
P A 3 / P F D
P A 2
P A 1
P A 0
P B 1 / A N 1
P B 0 / A N 0
V S S
1 6
1 5
1 4
1 3
1 2
1 1
1 0
9
1
2
3
4
5
6
7
8
P D 0 / P W M
H T 4 6 R 4 9
2 0 D I P - A / S O P - A
P A 4 / T M R
P A 5 / I N T
P A 6
P A 7
O S C 2
O S C 1
V D D
R E S
P D 1 / P W M 1
P D 0 / P W M 0
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
1
2
3
4
5
6
7
8
9
1 0
P A 3 / P F D
P A 2
P A 1
P A 0
P B 3 / A N 3
P B 2 / A N 2
P B 1 / A N 1
P B 0 / A N 0
V S S
P C 0

HT46R48A
Pin Name I/O Configuration
Option Description
PA0~PA2
PA3/PFD
PA4/TMR
PA5/INT
PA6~PA7
I/O
Pull-high
Wake-up
PA3 or PFD
Bidirectional 8-bit input/output port. Each individual pin on this port can be config-
ured as a wake-up input by a configuration option. Software instructions determine
if the pin is a CMOS output or Schmitt Trigger input. Configuration options deter-
mine which pins on the port have pull-high resistors. Pins PA3, PA4 and PA5 are
pin-shared with PFD, TMR and INT, respectively.
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4~PB7
I/O Pull-high
Bidirectional 8-bit input/output port. Software instructions determine if the pin is a
CMOS output or Schmitt Trigger input. Configuration options determine which pins
on the port have pull-high resistors. PB is pin-shared with the A/D input pins. The
A/D inputs are selected via software instructions. Once selected as an A/D input,
the I/O function and pull-high resistor options are disabled automatically.
PC0~PC1 I/O Pull-high
Bidirectional 2-bit input/output port. Software instructions determine if the pin is a
CMOS output or Schmitt Trigger input. Configuration options determine which pins
on the port have pull-high resistors.
PD0/PWM I/O Pull-high
I/O or PWM
Bidirectional 1-bit input/output port. Software instructions determine if the pin is a
CMOS output or Schmitt Trigger input. Configuration option determines if this pin
has a pull-high resistor. The PWM output is pin-shared with pin PD0 selected via a
configuration option.
OSC1
OSC2
I
OCrystal or RC
OSC1, OSC2 are connected to an external RC network or external crystal, deter-
mined by configuration option, for the internal system clock. If the RC system clock
option is selected, pin OSC2 can be used to measure the system clock at 1/4 fre-
quency.
RES I ¾Schmitt Trigger reset input. Active low.
VDD ¾¾ Positive power supply
VSS ¾¾ Negative power supply, ground
Note: 1. Each pin on PA can be programmed through a configuration option to have a wake-up function.
2. Individual pins can be selected to have a pull-high resistor.
3. Pins PB4~PB7 exist but are not bonded out on the 20-pin package.
4. Unbonded pins should be setup as outputs or as inputs with pull-high resistors to conserve power.
HT46R46/C46/R47/C47/R48A/C48A/R49
Rev. 1.41 4 December 30, 2008

HT46R49
Pin Name I/O Configuration
Option Description
PA0~PA2
PA3/PFD
PA4/TMR
PA5/INT
PA6~PA7
I/O
Pull-high
Wake-up
PA3 or PFD
Bidirectional 8-bit input/output port. Each individual pin on this port can be config-
ured as a wake-up input by a configuration option. Software instructions deter-
mine if the pin is a CMOS output or Schmitt Trigger input. Configuration options
determine which pins on the port have pull-high resistors. Pins PA3, PA4 and PA5
are pin-shared with PFD, TMR and INT, respectively.
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4~PB7
I/O Pull-high
Bidirectional 8-bit input/output port. Software instructions determine if the pin is a
CMOS output or Schmitt Trigger input. Configuration options determine which
pins on the port have pull-high resistors. PB is pin-shared with the A/D input pins.
The A/D inputs are selected via software instructions. Once selected as an A/D in-
put, the I/O function and pull-high resistor options are disabled automatically.
PC0~PC4 I/O Pull-high
Bidirectional 5-bit input/output port. Software instructions determine if the pin is a
CMOS output or Schmitt Trigger input. Configuration options determine which
pins on the port have pull-high resistors.
PD0/PWM0
PD1/PWM1 I/O Pull-high I/O or PWM
Bidirectional 2-bit input/output port. Software instructions determine if the pin is a
CMOS output or Schmitt Trigger input. Configuration option determines if this pin
has a pull-high resistor. The PWM output are pin-shared with pins PD0 and PD1
selected via a configuration option.
OSC1
OSC2
I
OCrystal or RC
OSC1, OSC2 are connected to an external RC network or external crystal, deter-
mined by configuration option, for the internal system clock. If the RC system
clock option is selected, pin OSC2 can be used to measure the system clock at
1/4 frequency.
RES I ¾Schmitt Trigger reset input. Active low.
VDD ¾¾ Positive power supply
VSS ¾¾ Negative power supply, ground
Note: 1. Each pin on PA can be programmed through a configuration option to have a wake-up function.
2. Individual pins can be selected to have a pull-high resistor.
3. Pins PC1~PC4 exist but are not bonded out on the 20-pin and 24-pin package.
Pins PB4~PB7 exist but are not bonded out on the 20-pin package.
4. Unbonded pins should be setup as outputs or as inputs with pull-high resistors to conserve power.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V Storage Temperature ............................-50°Cto125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V Operating Temperature...........................-40°Cto85°C
IOL Total ..............................................................150mA IOH Total............................................................-100mA
Total Power Dissipation .....................................500mW
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings²may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
HT46R46/C46/R47/C47/R48A/C48A/R49
Rev. 1.41 5 December 30, 2008

D.C. Characteristics Ta=25°C
Symbol Parameter
Test Conditions
Min. Typ. Max. Unit
VDD Conditions
VDD Operating Voltage
¾fSYS=4MHz 2.2 ¾5.5 V
¾fSYS=8MHz 3.3 ¾5.5 V
IDD1 Operating Current
(Crystal OSC)
3V No load, fSYS=4MHz
ADC disable
¾0.6 1.5 mA
5V ¾24mA
IDD2 Operating Current
(RC OSC)
3V No load, fSYS=4MHz
ADC disable
¾0.8 1.5 mA
5V ¾2.5 4 mA
IDD3 Operating Current
(Crystal OSC, RC OSC) 5V No load, fSYS=8MHz ADC disable ¾48mA
ISTB1 Standby Current
(WDT Enabled)
3V No load,
system HALT
¾¾ 5mA
5V ¾¾10 mA
ISTB2 Standby Current
(WDT Disabled)
3V No load,
system HALT
¾¾ 1mA
5V ¾¾ 2mA
VIL1 Input Low Voltage for I/O Ports,
TMR and INT ¾¾ 0¾0.3VDD V
VIH1 Input High Voltage for I/O Ports,
TMR and INT ¾¾
0.7VDD ¾VDD V
VIL2 Input Low Voltage (RES) ¾¾ 0¾0.4VDD V
VIH2 Input High Voltage (RES) ¾¾
0.9VDD ¾VDD V
VLVR Low Voltage Reset ¾¾ 2.7 3.0 3.3 V
IOL I/O Port Sink Current
3V VOL=0.1VDD 48
¾mA
5V VOL=0.1VDD 10 20 ¾mA
IOH I/O Port Source Current
3V VOH=0.9VDD -2-4¾mA
5V VOH=0.9VDD -5-10 ¾mA
RPH Pull-high Resistance
3V ¾20 60 100 kW
5V ¾10 30 50 kW
VAD A/D Input Voltage ¾¾ 0¾VDD V
EAD A/D Conversion Error ¾¾ ¾±0.5 ±1LSB
IADC Additional Power Consumption
if A/D Converter is Used
3V
¾
¾0.5 1 mA
5V ¾1.5 3 mA
HT46R46/C46/R47/C47/R48A/C48A/R49
Rev. 1.41 6 December 30, 2008

A.C. Characteristics Ta=25°C
Symbol Parameter
Test Conditions
Min. Typ. Max. Unit
VDD Conditions
fSYS System Clock
¾2.2V~5.5V 400 ¾4000 kHz
¾3.3V~5.5V 400 ¾8000 kHz
fTIMER Timer I/P Frequency
(TMR)
¾2.2V~5.5V 0 ¾4000 kHz
¾3.3V~5.5V 0 ¾8000 kHz
tWDTOSC Watchdog Oscillator Period
3V ¾45 90 180 ms
5V ¾32 65 130 ms
tWDT1 Watchdog Time-out Period
(RC) ¾¾ 215 ¾216 tWDTOSC
tWDT2 Watchdog Time-out Period
(System Clock) ¾¾ 217 ¾218 tSYS
tRES External Reset Low Pulse Width ¾¾ 1¾¾ms
tSST System Start-up Timer Period ¾Wake-up from HALT ¾1024 ¾*tSYS
tLVR Low Voltage Reset Time ¾¾0.25 1 2 ms
tINT Interrupt Pulse Width ¾¾ 1¾¾ms
tAD1 A/D Clock Period -
HT46R46 ¾¾ 0.5 ¾¾ms
tAD2 A/D Clock Period -
HT46R47/HT46R48A/HT46R49 ¾¾ 1¾¾ms
tADC1 A/D Conversion Time -
HT46R46 ¾¾ ¾
64 ¾tAD1
tADC2 A/D Conversion Time -
HT46R47/HT46R48A/HT46R49 ¾¾ ¾
76 ¾tAD2
tADCS1 A/D Sampling Time -
HT46R46 ¾¾ ¾
32 ¾tAD1
tADCS2 A/D Sampling Time -
HT46R47/HT46R48A/HT46R49 ¾¾ ¾
32 ¾tAD2
Note: *tSYS=1/fSYS
HT46R46/C46/R47/C47/R48A/C48A/R49
Rev. 1.41 7 December 30, 2008

HT46R46/C46/R47/C47/R48A/C48A/R49
Rev. 1.41 8 December 30, 2008
System Architecture
A key factor in the high-performance features of the
Holtek range of Cost-Effective A/D Type
microcontrollers is attributed to the internal system ar-
chitecture. The range of devices take advantage of the
usual features found within RISC microcontrollers pro-
viding increased speed of operation and enhanced per-
formance. The pipelining scheme is implemented in
such a way that instruction fetching and instruction exe-
cution are overlapped, hence instructions are effectively
executed in one cycle, with the exception of branch or
call instructions. An 8-bit wide ALU is used in practically
all operations of the instruction set. It carries out arith-
metic operations, logic operations, rotation, increment,
decrement, branch decisions, etc. The internal data
path is simplified by moving data through the Accumula-
tor and the ALU. Certain internal registers are imple-
mented in the Data Memory and can be directly or
indirectly addressed. The simple addressing methods of
these registers along with additional architectural fea-
tures ensure that a minimum of external components is
required to provide a functional I/O and A/D control sys-
tem with maximum reliability and flexibility. This makes
these devices suitable for low-cost, high-volume pro-
duction for controller applications requiring from 1K up
to 4K words of Program Memory and 64 to 128 bytes of
Data Memory storage.
Clocking and Pipelining
The main system clock, derived from either a Crys-
tal/Resonator or RC oscillator is subdivided into four in-
ternally generated non-overlapping clocks, T1~T4. The
Program Counter is incremented at the beginning of the
T1 clock during which time a new instruction is fetched.
The remaining T2~T4 clocks carry out the decoding and
execution functions. In this way, one T1~T4 clock cycle
forms one instruction cycle. Although the fetching and
execution of instructions takes place in consecutive in-
struction cycles, the pipelining structure of the
microcontroller ensures that instructions are effectively
executed in one instruction cycle. The exception to this
are instructions where the contents of the Program
Counter are changed, such as subroutine calls or
jumps, in which case the instruction will take one more
instruction cycle to execute.
When the RC oscillator is used, OSC2 is freed for use as
a T1 phase clock synchronizing pin. This T1 phase clock
has a frequency of fSYS/4 with a 1:3 high/low duty cycle.
For instructions involving branches, such as jump or call
instructions, two machine cycles are required to com-
plete instruction execution. An extra cycle is required as
the program takes one cycle to first obtain the actual
jump or call address and then another cycle to actually
execute the branch. The requirement for this extra cycle
should be taken into account by programmers in timing
sensitive applications
F e t c h I n s t . ( P C )
E x e c u t e I n s t . ( P C - 1 ) F e t c h I n s t . ( P C + 1 )
E x e c u t e I n s t . ( P C ) F e t c h I n s t . ( P C + 2 )
E x e c u t e I n s t . ( P C + 1 )
P C P C + 1 P C + 2
O s c i l l a t o r C l o c k
( S y s t e m C l o c k )
P h a s e C l o c k T 1
P r o g r a m C o u n t e r
P h a s e C l o c k T 2
P h a s e C l o c k T 3
P h a s e C l o c k T 4
P i p e l i n i n g
System Clocking and Pipelining
F e t c h I n s t . 1 E x e c u t e I n s t . 1
F e t c h I n s t . 2
F l u s h P i p e l i n e
1
2
3
4
5
6D E L A Y :
M O V A , [ 1 2 H ]
C A L L D E L A Y
C P L [ 1 2 H ]
:
:
N O P
E x e c u t e I n s t . 2
F e t c h I n s t . 3
F e t c h I n s t . 6 E x e c u t e I n s t . 6
F e t c h I n s t . 7
Instruction Fetching

HT46R46/C46/R47/C47/R48A/C48A/R49
Rev. 1.41 9 December 30, 2008
Program Counter
During program execution, the Program Counter is used
to keep track of the address of the next instruction to be
executed. It is automatically incremented by one each
time an instruction is executed except for instructions,
such as ²JMP²or ²CALL²that demand a jump to a
non-consecutive Program Memory address. For the
Cost-Effective A/D Type series of microcontrollers, note
that the Program Counter width varies with the Program
Memory capacity depending upon which device is se-
lected. However, it must be noted that only the lower 8
bits, known as the Program Counter Low Register, are
directly addressable by user.
When executing instructions requiring jumps to
non-consecutive addresses such as a jump instruction,
a subroutine call, interrupt or reset, etc., the
microcontroller manages program control by loading the
required address into the Program Counter. For condi-
tional skip instructions, once the condition has been
met, the next instruction, which has already been
fetched during the present instruction execution, is dis-
carded and a dummy cycle takes its place while the cor-
rect instruction is obtained.
The lower byte of the Program Counter, known as the
Program Counter Low register or PCL, is available for
program control and is a readable and writable register.
By transferring data directly into this register, a short
program jump can be executed directly, however, as
only this low byte is available for manipulation, the
jumps are limited to the present page of memory, that is
256 locations. When such program jumps are executed
it should also be noted that a dummy cycle will be in-
serted.
The lower byte of the Program Counter is fully accessi-
ble under program control. Manipulating the PCL might
cause program branching, so an extra cycle is needed
to pre-fetch. Further information on the PCL register can
be found in the Special Function Register section.
Mode
Program Counter Bits
b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Initial Reset 000000000000
External Interrupt 000000000100
Timer/Event Counter
Overflow 000000001000
A/D Converter Interrupt 000000001100
Skip Program Counter + 2
Loading PCL PC11 PC10 PC9 PC8 @7 @6 @5 @4 @3 @2 @1 @0
Jump, Call Branch #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0
Return from Subroutine S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
Program Counter
Note: PC11~PC8: Current Program Counter bits
@7~@0: PCL bits
#11~#0: Instruction code address bits
S11~S0: Stack register bits
For the HT46R49, the Program Counter is 12 bits wide, i.e. from b11~b0.
For the HT46R47 and HT46R48A, the Program Counter is 11 bits wide, i.e. From
b10~b0, therefore the b11 column in the table is not applicable.
For the HT46R46, the Program Counter is 10 bits wide, i.e. from b9~b0, therefore the b11 and
b10 the columns in the table are not applicable.

HT46R46/C46/R47/C47/R48A/C48A/R49
Rev. 1.41 10 December 30, 2008
Stack
This is a special part of the memory which is used to
save the contents of the Program Counter only. The
stack can have either 4 or 6 levels depending upon
which device is selected and is neither part of the data
nor part of the program space, and is neither readable
nor writable. The activated level is indexed by the Stack
Pointer, SP, and is neither readable nor writable. At a
subroutine call or interrupt acknowledge signal, the con-
tents of the Program Counter are pushed onto the stack.
At the end of a subroutine or an interrupt routine, sig-
naled by a return instruction, RET or RETI, the Program
Counter is restored to its previous value from the stack.
After a device reset, the Stack Pointer will point to the
top of the stack.
If the stack is full and an enabled interrupt takes place,
the interrupt request flag will be recorded but the ac-
knowledge signal will be inhibited. When the Stack
Pointer is decremented, by RET or RETI, the interrupt
will be serviced. This feature prevents stack overflow al-
lowing the programmer to use the structure more easily.
However, when the stack is full, a CALL subroutine in-
struction can still be executed which will result in a stack
overflow. Precautions should be taken to avoid such
cases which might cause unpredictable program
branching.
Note: For the HT46R46, 4 levels of stack are available
and for the HT46R47,HT46R48A and
HT46R49, 6 levels of stack are available.
Arithmetic and Logic Unit -ALU
The arithmetic-logic unit or ALU is a critical area of the
microcontroller that carries out arithmetic and logic op-
erations of the instruction set. Connected to the main
microcontroller data bus, the ALU receives related in-
struction codes and performs the required arithmetic or
logical operations after which the result will be placed in
the specified register. As these ALU calculation or oper-
ations may result in carry, borrow or other status
changes, the status register will be correspondingly up-
dated to reflect these changes. The ALU supports the
following functions:
·Arithmetic operations: ADD, ADDM, ADC, ADCM,
SUB, SUBM, SBC, SBCM, DAA
·Logic operations: AND, OR, XOR, ANDM, ORM,
XORM, CPL, CPLA
·Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA,
RLC
·Increment and Decrement INCA, INC, DECA, DEC
·Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ,
SIZA, SDZA, CALL, RET, RETI
Program Memory
The Program Memory is the location where the user code
or program is stored. For microcontrollers, two types of
Program Memory are usually supplied. The first type is
the One-Time Programmable, OTP, memory where us-
ers can program their application code into the device.
Devices with OTP memory are denoted by having an ²R²
within their device name. By using the appropriate pro-
gramming tools, OTP devices offer users the flexibility to
freely develop their applications which may be useful
during debug or for products requiring frequent upgrades
or program changes. OTP devices are also applicable for
use in applications that require low or medium volume
production runs. The other type of memory is the mask
ROM memory, denoted by having a ²C²within the device
name. These devices offer the most cost effective solu-
tions for high volume products.
Structure
The Program Memory has a capacity of 1K by 14, 2K by
14 or 4K by 15 bits depending upon which device is se-
lected. The Program Memory is addressed by the Pro-
gram Counter and also contains data, table information
and interrupt entries. Table data, which can be setup in
any location within the Program Memory, is addressed
by separate table pointer registers.
Special Vectors
Within the Program Memory, certain locations are re-
served for special usage such as reset and interrupts.
·Location 000H
This vector is reserved for use by the device reset for
program initialisation. After a device reset is initiated, the
program will jump to this location and begin execution.
·Location 004H
This vector is used by the external interrupt. If the ex-
ternal interrupt pin on the device goes low, the pro-
gram will jump to this location and begin execution if
the external interrupt is enabled and the stack is not
full.
·Location 008H
This internal vector is used by the Timer/Event Coun-
ter. If a counter overflow occurs, the program will jump
to this location and begin execution if the timer/event
counter interrupt is enabled and the stack is not full.
·Location 00CH
This internal vector is used by the A/D converter.
When an A/D conversion cycle is complete, the pro-
gram will jump to this location and begin execution if
the A/D interrupt is enabled and the stack is not full.
P r o g r a m C o u n t e r
S t a c k L e v e l 1
S t a c k L e v e l 2
S t a c k L e v e l 3
S t a c k L e v e l N
P r o g r a m
M e m o r y
T o p o f S t a c k
S t a c k
P o i n t e r
B o t t o m o f S t a c k

HT46R46/C46/R47/C47/R48A/C48A/R49
Rev. 1.41 11 December 30, 2008
Look-up Table
Any location within the Program Memory can be defined
as a look-up table where programmers can store fixed
data. To use the look-up table, the table pointer must
first be setup by placing the lower order address of the
look up data to be retrieved in the table pointer register,
TBLP. This register defines the lower 8-bit address of
the look-up table.
After setting up the table pointer, the table data can be
retrieved from the current Program Memory page or last
Program Memory page using the ²TABRDC[m]²or
²TABRDL [m]²instructions, respectively. When these in-
structions are executed, the lower order table byte from
the Program Memory will be transferred to the user de-
fined Data Memory register [m] as specified in the in-
struction. The higher order table data byte from the
Program Memory will be transferred to the TBLH special
register. Any unused bits in this transferred higher order
byte will be read as ²0².
The following diagram illustrates the addressing/data
flow of the look-up table:
Table Program Example
The following example shows how the table pointer and
table data is defined and retrieved from the HT46R47
microcontroller. This example uses raw table data lo-
cated in the last page which is stored there using the
ORG statement. The value at this ORG statement is
²700H²which refers to the start address of the last page
within the 2K Program Memory of the HT46R47
microcontroller. The table pointer is setup here to have
an initial value of ²06H². This will ensure that the first
data read from the data table will be at the Program
Memory address ²706H²or 6 locations after the start of
the last page. Note that the value for the table pointer is
referenced to the first address of the present page if the
²TABRDC [m]²instruction is being used. The high byte
of the table data which in this case is equal to zero will
be transferred to the TBLH register automatically when
the ²TABRDL [m]²instruction is executed.
3 F F H
N o t I m p l e m e n t e d
1 5 b i t s
1 4 b i t s1 4 b i t s
8 0 0 H
F F F H
0 1 4 H
I n i t i a l i s a t i o n
V e c t o r
E x t e r n a l
I n t e r r u p t V e c t o r
I n i t i a l i s a t i o n
V e c t o r
E x t e r n a l
I n t e r r u p t V e c t o r
T i m e r / E v e n t C o u n t e r
I n t e r r u p t V e c t o r
I n i t i a l i s a t i o n
V e c t o r
E x t e r n a l
I n t e r r u p t V e c t o r
T i m e r / E v e n t C o u n t e r
I n t e r r u p t V e c t o r
H T 4 6 R 4 7
H T 4 6 R 4 8 A H T 4 6 R 4 9H T 4 6 R 4 6
A / D C o n v e r t e r
I n t e r r u p t V e c t o r
A / D C o n v e r t e r
I n t e r r u p t V e c t o r
A / D C o n v e r t e r
I n t e r r u p t V e c t o r
T i m e r / E v e n t C o u n t e r
I n t e r r u p t V e c t o r
000H
004H
008H
0 0 C H
010H
3 0 0 H
7 F F H
4 0 0 H
Program Memory Structure
P r o g r a m
M e m o r y
P r o g r a m C o u n t e r
H i g h B y t e
T B L P
T B L H S p e c i f i e d b y [ m ]
T a b l e C o n t e n t s H i g h B y t e T a b l e C o n t e n t s L o w B y t e

HT46R46/C46/R47/C47/R48A/C48A/R49
Rev. 1.41 12 December 30, 2008
tempreg1 db ? ; temporary register #1
tempreg2 db ? ; temporary register #2
:
:
mov a,06h ; initialise table pointer - note that this address
; is referenced
mov tblp,a ; to the last page or present page
:
:
tabrdl tempreg1 ; transfers value in table referenced by table pointer
; to tempregl
; data at prog. memory address ²706H²transferred to
; tempreg1 and TBLH
dec tblp ; reduce value of table pointer by one
tabrdl tempreg2 ; transfers value in table referenced by table pointer
; to tempreg2
; data at prog.memory address ²705H²transferred to
; tempreg2 and TBLH
; in this example the data ²1AH²is transferred to
; tempreg1 and data ²0FH²to register tempreg2
; the value ²00H²will be transferred to the high byte
; register TBLH
:
:
org 700h ; sets initial address of last page (for HT46R47)
Dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
:
Because the TBLH register is a read-only register and
cannot be restored, care should be taken to ensure its
protection if both the main routine and Interrupt Service
Routine use table read instructions. If using the table
read instructions, the Interrupt Service Routines may
change the value of the TBLH and subsequently cause
errors if used again by the main routine. As a rule it is
recommended that simultaneous use of the table read
instructions should be avoided. However, in situations
where simultaneous use cannot be avoided, the inter-
rupts should be disabled prior to the execution of any
main routine table-read instructions. Note that all table
related instructions require two instruction cycles to
complete their operation.
Data Memory
The Data Memory is a volatile area of 8-bit wide RAM
internal memory and is the location where temporary in-
formation is stored. Divided into two sections, the first of
these is an area of RAM where special function registers
are located. These registers have fixed locations and
are necessary for correct operation of the device. Many
of these registers can be read from and written to di-
rectly under program control, however, some remain
protected from user manipulation. The second area of
Data Memory is reserved for general purpose use. All
locations within this area are read and write accessible
under program control.
Instruction
Table Location Bits
b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
TABRDC [m] PC11 PC10 PC9 PC8 @7 @6 @5 @4 @3 @2 @1 @0
TABRDL [m]1111@7@6@5@4@3@2@1@0
Table Location
Note: PC11~PC8: Current Program Counter bits
@7~@0: Table Pointer TBLP bits
For the HT46R49 the Table address location is 12 bits, i.e. from b11~b0.
For the HT46R47 and HT46R48A, the Table address location is 11 bits, i.e. from b10~b0.
For the HT46R46, the Table address location is 10 bits, i.e. from b9~b0.

HT46R46/C46/R47/C47/R48A/C48A/R49
Rev. 1.41 13 December 30, 2008
Structure
The two sections of Data Memory, the Special Purpose
and General Purpose Data Memory are located at con-
secutive locations. All are implemented in RAM and are
8 bits wide but the length of each memory section is dic-
tated by the type of microcontroller chosen. The start
address of the Data Memory for all devices is the ad-
dress ²00H². Registers which are common to all
microcontrollers, such as ACC, PCL, etc., have the
same Data Memory address.
General Purpose Data Memory
All microcontroller programs require an area of
read/write memory where temporary data can be stored
and retrieved for use later. It is this area of RAM memory
that is known as General Purpose Data Memory. This
area of Data Memory is fully accessible by the user pro-
gram for both read and write operations. By using the
²SET [m].i²and ²CLR [m].i²instructions individual bits
can be set or reset under program control giving the
user a large range of flexibility for bit manipulation in the
Data Memory.
Special Purpose Data Memory
This area of Data Memory is where registers, necessary
for the correct operation of the microcontroller, are
stored. Most of the registers are both readable and
writable but some are protected and are readable only,
the details of which are located under the relevant Spe-
cial Function Register section. Note that for locations
that are unused, any read instruction to these addresses
will return the value ²00H².
Special Function Registers
To ensure successful operation of the microcontroller,
certain internal registers are implemented in the Data
Memory area. These registers ensure correct operation
of internal functions such as timers, interrupts, etc., as
well as external functions such as I/O data control and
A/D converter operation. The location of these registers
within the Data Memory begins at the address 00H. Any
unused Data Memory locations between these special
function registers and the point where the General Pur-
pose Memory begins is reserved for future expansion
purposes, attempting to read data from these locations
will return a value of 00H.
Indirect Addressing Register -IAR
The IAR register, located at Data Memory address
²00H², is not physically implemented. This special regis-
ter allows what is known as indirect addressing, which
permits data manipulation using Memory Pointers in-
stead of the usual direct memory addressing method
where the actual memory address is defined. Any ac-
tions on the IAR register will result in corresponding
read/write operations to the memory location specified
by the Memory Pointer MP. Reading the IAR register in-
directly will return a result of ²00H²and writing to the
register indirectly will result in no operation.
Memory Pointer -MP
One Memory Pointer, known as MP, is physically imple-
mented in Data Memory. The Memory Pointer can be
written to and manipulated in the same way as normal
registers providing an easy way of addressing and
tracking data. When using any operation on the indirect
addressing register IAR, it is actually the address speci-
fied by the Memory Pointer that the microcontroller will
be directed to.
For devices with 64 or 88 bytes of RAM Data Memory,
bit 7 of the Memory Pointer is not implemented. How-
ever, it must be noted that when the Memory Pointer for
these devices is read, bit 7 will be read as high.
G e n e r a l P u r p o s e
D a t a M e m o r y
S p e c i a l P u r p o s e
D a t a M e m o r y
00H
40H
B F H
3 F H
G e n e r a l P u r p o s e
D a t a M e m o r y
S p e c i a l P u r p o s e
D a t a M e m o r y
00H
40H
7 F H
3 F H
H T 4 6 R 4 6 a n d H T 4 6 R 4 7
H T 4 6 R 4 9
G e n e r a l P u r p o s e
D a t a M e m o r y
S p e c i a l P u r p o s e
D a t a M e m o r y
00H
28H
7 F H
27H
H T 4 6 R 4 8 A
Data Memory Structure
Note: Most of the Data Memory bits can be directly manipulated using the ²SET [m].i²and ²CLR [m].i²with the excep-
tion of a few dedicated bits. The Data Memory can also be accessed through the memory pointer register MP.

HT46R46/C46/R47/C47/R48A/C48A/R49
Rev. 1.41 14 December 30, 2008
The following example shows how to clear a section of four RAM locations already defined as locations adres1 to
adres4.
data .section ¢data¢
adres1 db ?
adres2 db ?
adres3 db ?
adres4 db ?
block db ?
code .section at 0 ¢code¢
org 00h
start:
mov a,04h ; setup size of block
mov block,a
mov a,offset adres1 ; Accumulator loaded with first RAM address
mov mp,a ; setup memory pointer with first RAM address
loop:
clr IAR ; clear the data at address defined by MP
inc mp ; increment memory pointer
sdz block ; check if last memory location has been cleared
jmp loop
continue:
The important point to note here is that in the example shown above, no reference is made to specific RAM addresses.
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0 A H
0 B H
0 C H
0 D H
0 E H
0 F H
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1 A H
1 B H
1 C H
1 D H
1 E H
1 F H
20H
2 1 H
22H
2 3 H : n u s e d , r e a d a s " 0 0 "
I A R
M P
A C C
P C L
T B L P
T B L H
S T A T S
I N T C
T M R
T M R C
P A
P A C
P B
P B C
P D
P D C
P W M
A D R
A D C R
A C S R
H T 4 6 R 4 6
I A R
M P
A C C
P C L
T B L P
T B L H
S T A T S
I N T C
T M R
T M R C
P A
P A C
P B
P B C
P D
P D C
P W M
A D R L
A D R H
A D C R
A C S R
H T 4 6 R 4 7
I A R
M P
A C C
P C L
T B L P
T B L H
S T A T S
I N T C
T M R
T M R C
P A
P A C
P B
P B C
P C
P C C
P D
P D C
P W M
A D R L
A D R H
A D C R
A C S R
H T 4 6 R 4 8 A
I A R
M P
A C C
P C L
T B L P
T B L H
S T A T S
I N T C
T M R
T M R C
P A
P A C
P B
P B C
P C
P C C
P D
P D C
P W M 0
P W M 1
A D R L
A D R H
A D C R
A C S R
H T 4 6 R 4 9
Special Purpose Data Memory

HT46R46/C46/R47/C47/R48A/C48A/R49
Rev. 1.41 15 December 30, 2008
Accumulator -ACC
The Accumulator is central to the operation of any
microcontroller and is closely related with operations
carried out by the ALU. The Accumulator is the place
where all intermediate results from the ALU are stored.
Without the Accumulator it would be necessary to write
the result of each calculation or logical operation such
as addition, subtraction, shift, etc., to the Data Memory
resulting in higher programming and timing overheads.
Data transfer operations usually involve the temporary
storage function of the Accumulator; for example, when
transferring data between one user defined register and
another, it is necessary to do this by passing the data
through the Accumulator as no direct transfer between
two registers is permitted.
Program Counter Low Register -PCL
To provide additional program control functions, the low
byte of the Program Counter is made accessible to pro-
grammers by locating it within the Special Purpose area
of the Data Memory. By manipulating this register, direct
jumps to other program locations are easily imple-
mented. Loading a value directly into this PCL register
will cause a jump to the specified Program Memory lo-
cation, however, as the register is only 8-bit wide, only
jumps within the current Program Memory page are per-
mitted. When such operations are used, note that a
dummy cycle will be inserted.
Look-up Table Registers -TBLP, TBLH
These two special function registers are used to control
operation of the look-up table which is stored in the Pro-
gram Memory. TBLP is the table pointer and indicates
the location where the table data is located. Its value
must be setup before any table read commands are ex-
ecuted. Its value can be changed, for example using the
²INC²or ²DEC²instructions, allowing for easy table data
pointing and reading. TBLH is the location where the
high order byte of the table data is stored after a table
read data instruction has been executed. Note that the
lower order table data byte is transferred to a user de-
fined location.
Status Register -STATUS
This 8-bit register contains the zero flag (Z), carry flag
(C), auxiliary carry flag (AC), overflow flag (OV), power
down flag (PDF), and watchdog time-out flag (TO).
These arithmetic/logical operation and system manage-
ment flags are used to record the status and operation of
the microcontroller.
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
will not change the TO or PDF flag. In addition, opera-
tions related to the status register may give different re-
sults due to the different instruction operations. The TO
flag can be affected only by a system power-up, a WDT
time-out or by executing the ²CLR WDT²or ²HALT²in-
struction. The PDF flag is affected only by executing the
²HALT²or ²CLR WDT²instruction or during a system
power-up.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
¨Cis set if an operation results in a carry during an
addition operation or if a borrow does not take place
during a subtraction operation; otherwise C is
cleared. C is also affected by a rotate through carry
instruction.
¨AC is set if an operation results in a carry out of the
low nibbles in addition, or no borrow from the high
nibble into the low nibble in subtraction; otherwise
AC is cleared.
¨Zis set if the result of an arithmetic or logical opera-
tion is zero; otherwise Z is cleared.
¨OV is set if an operation results in a carry into the
highest-order bit but not a carry out of the high-
est-order bit, or vice versa; otherwise OV is cleared.
¨PDF is cleared by a system power-up or executing
the ²CLR WDT²instruction. PDF is set by executing
the ²HALT²instruction.
¨TO is cleared by a system power-up or executing
the ²CLR WDT²or ²HALT²instruction. TO is set by
a WDT time-out.
T O P D F O V Z A C C
S T A T U S R e g i t e r
A r i t h m e t i c / L o g i c O p e r a t i o n F l a g
C a r r y f l a g
A u x i l i a r y c a r r y f l a g
Z e r o f l a g
O v e r f l o w f l a g
S y t e m M a n a g e m e n t F l a g
P o w e r d o w n f l a g
W a t c h d o g t i m e - o u t f l a g
N o t i m p l e m e n t e d , r e a d a s " 0 "
b 7 b 0
Status Register

HT46R46/C46/R47/C47/R48A/C48A/R49
Rev. 1.41 16 December 30, 2008
In addition, on entering an interrupt sequence or execut-
ing a subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status registers are important and if the subroutine
can corrupt the status register, precautions must be
taken to correctly save it.
Interrupt Control Register -INTC
This 8-bit register, known as the INTC register, controls
the operation of both external and internal timer inter-
rupts. By setting various bits within this register using
standard bit manipulation instructions, the enable/disable
function of each interrupt can be independently con-
trolled. A master interrupt bit within this register, the EMI
bit, acts like a global enable/disable and is used to set all
of the interrupt enable bits on or off. This bit is cleared
when an interrupt routine is entered to disable further in-
terrupt and is set by executing the ²RETI²instruction.
Timer/Event Counter Registers -TMR, TMRC
All devices possess a single internal 8-bit count-up
timer. An associated register known as TMR is the loca-
tion where the timer¢s 8-bit value is located. This register
can also be preloaded with fixed data to allow different
time intervals to be setup. An associated control regis-
ter, known as TMRC, contains the setup information for
this timer, which determines in what mode the timer is to
be used as well as containing the timer on/off control
function.
Input/Output Ports and Control Registers
Within the area of Special Function Registers, the I/O
registers and their associated control registers play a
prominent role. All I/O ports have a designated register
correspondingly labeled as PA, PB, PC and PD. These
labeled I/O registers are mapped to specific addresses
within the Data Memory as shown in the Data Memory
table, which are used to transfer the appropriate output
or input data on that port. With each I/O port there is an
associated control register labeled PAC, PBC, PCC and
PDC, also mapped to specific addresses with the Data
Memory. The control register specifies which pins of that
port are set as inputs and which are set as outputs. To
setup a pin as an input, the corresponding bit of the con-
trol register must be set high, for an output it must be set
low. During program initialization, it is important to first
setup the control registers to specify which pins are out-
puts and which are inputs before reading data from or
writing data to the I/O ports. One flexible feature of these
registers is the ability to directly program single bits us-
ing the ²SET [m].i²and ²CLR [m].i²instructions. The
ability to change I/O pins from output to input and vice
versa by manipulating specific bits of the I/O control reg-
isters during normal program operation is a useful fea-
ture of these devices.
Pulse Width Modulator Registers -
PWM, PWM0, PWM1
Each device in the Cost-Effective A/D Type
microcontroller range contains either one or two Pulse
Width Modulators. Each one has its own related inde-
pendent control register. For devices with a single PWM
function this is register is known as PWM, while for de-
vices with two PWM functions, their control register
names are PWM0 and PWM1. The 8-bit contents of
these registers, defines the duty cycle value for the
modulation cycle of the corresponding Pulse Width
Modulator.
A/D Converter Registers -
ADR, ADRL, ADRH, ADCR, ACSR
Each device in the Cost-Effective A/D Type
microcontroller range contains a 4-channel 8-bit or 9-bit
A/D converter. The correct operation of the A/D requires
the use of one or two data registers, a control register
and a clock source register. For the HT46R46 device,
which has an 8-bit A/D converter, there is a single data
register, known as ADR. For the other devices, which
contain a 9-bit A/D converter, there are two data regis-
ters, a high byte data register known as ADRH, and a
low byte data register known as ADRL. These are the
register locations where the digital value is placed after
the completion of an analog to digital conversion cycle.
The channel selection and configuration of the A/D con-
verter is setup via the control register ADCR while the
A/D clock frequency is defined by the clock source reg-
ister, ACSR.

HT46R46/C46/R47/C47/R48A/C48A/R49
Rev. 1.41 17 December 30, 2008
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on
their I/O ports. With the input or output designation of ev-
ery pin fully under user program control, pull-high op-
tions for all ports and wake-up options on certain pins,
the user is provided with an I/O structure to meet the
needs of a wide range of application possibilities.
Depending upon which device or package is chosen,
the microcontroller range provides from 13 to 23
bidirectional input/output lines labeled with port names
PA, PB, PC and PD. These I/O ports are mapped to the
RAM Data Memory with specific addresses as shown in
the Special Purpose Data Memory table. All of these I/O
ports can be used for input and output operations. For
input operation, these ports are non-latching, which
means the inputs must be ready at the T2 rising edge of
instruction ²MOV A,[m]², where m denotes the port ad-
dress. For output operation, all the data is latched and
remains unchanged until the output latch is rewritten.
Pull-high Resistors
Many product applications require pull-high resistors for
their switch inputs usually requiring the use of an exter-
nal resistor. To eliminate the need for these external re-
sistors, all I/O pins, when configured as an input have
the capability of being connected to an internal pull-high
resistor. These pull-high resistors are selectable via
configuration options and are implemented using a
weak PMOS transistor.
Port A Wake-up
Each device has a HALT instruction enabling the
microcontroller to enter a Power Down Mode and pre-
serve power, a feature that is important for battery and
other low-power applications. Various methods exist to
wake-up the microcontroller, one of which is to change
the logic condition on one of the Port A pins from high to
low. After a ²HALT²instruction forces the microcontroller
into entering a HALT condition, the processor will re-
main idle or in a low-power state until the logic condition
of the selected wake-up pin on Port A changes from high
to low. This function is especially suitable for applica-
tions that can be woken up via external switches. Note
that each pin on Port A can be selected individually to
have this wake-up feature.
I/O Port Control Registers
Each I/O port has its own control register PAC, PBC,
PCC and PDC, to control the input/output configuration.
With this control register, each CMOS output or input
with or without pull-high resistor structures can be re-
configured dynamically under software control. Each pin
of the I/O ports is directly mapped to a bit in its associ-
ated port control register. For the I/O pin to function as
an input, the corresponding bit of the control register
must be written as a ²1². This will then allow the logic
state of the input pin to be directly read by instructions.
When the corresponding bit of the control register is
written as a ²0², the I/O pin will be setup as a CMOS out-
put. If the pin is currently setup as an output, instructions
can still be used to read the output register. However, it
should be noted that the program will in fact only read
the status of the output data latch and not the actual
logic status of the output pin.
Pin-shared Functions
The flexibility of the microcontroller range is greatly en-
hanced by the use of pins that have more than one func-
tion. Limited numbers of pins can force serious design
constraints on designers but by supplying pins with
multi-functions, many of these difficulties can be over-
come. For some pins, the chosen function of the
multi-function I/O pins is set by configuration options
while for others the function is set by application pro-
gram control.
·External Interrupt Input
The external interrupt pin INT is pin-shared with the
I/O pin PA5. For applications not requiring an external
interrupt input, the pin-shared external interrupt pin
can be used as a normal I/O pin, however to do this,
the external interrupt enable bits in the INTC register
must be disabled.
·External Timer Clock Input
The external timer pin TMR is pin-shared with the I/O
pin PA4. To configure it to operate as a timer input, the
corresponding control bits in the timer control register
must be correctly set. For applications that do not re-
quire an external timer input, the pin can be used as a
normal I/O pin. Note that if used as a normal I/O pin
the timer mode control bits in the timer control register
must select the timer mode, which has an internal
clock source, to prevent the input pin from interfering
with the timer operation.
·PFD Output
Each device contains a PFD function whose single
output is pin-shared with PA3. The output function of
this pin is chosen via a configuration option and re-
mains fixed after the device is programmed. Note that
the corresponding bit of the port control register,
PAC.3, must setup the pin as an output to enable the
PFD output. If the PAC port control register has setup
the pin as an input, then the pin will function as a nor-
mal logic input with the usual pull-high option, even if
the PFD configuration option has been selected.

HT46R46/C46/R47/C47/R48A/C48A/R49
Rev. 1.41 18 December 30, 2008
·PWM Outputs
All devices contain one or two PWM outputs pin
shared with pins PD0 and PD1. The PWM output
functions are chosen via configuration options and re-
main fixed after the device is programmed. Note that
the corresponding bit or bits of the port control regis-
ter, PDC, must setup the pin as an output to enable
the PWM output. If the PDC port control register has
setup the pin as an input, then the pin will function as a
normal logic input with the usual pull-high option, even
if the PWM configuration option has been selected.
·A/D Inputs
Each device has four A/D converter inputs. All of
these analog inputs are pin-shared with I/O pins on
Port B. If these pins are to be used as A/D inputs and
not as normal I/O pins then the corresponding bits in
the A/D Converter Control Register, ADCR, must be
properly set. There are no configuration options asso-
ciated with the A/D function. If used as I/O pins, then
full pull-high resistor configuration options remain,
however if used as A/D inputs then any pull-high resis-
tor options associated with these pins will be automat-
ically disconnected.
VD D
M
X
W a k e - u p O p t i o n
S y s t e m W a k e - u p
R e a d D a t a R e g i s t e r
C o n t r o l B i t P u l l - H i g h
O p t i o n
D a t a B u s
W r i t e C o n t r o l R e g i s t e r
C h i p R e s e t
R e a d C o n t r o l R e g i s t e r
W r i t e D a t a R e g i s t e r
D a t a B i t
I / O P i n
W e a k
P u l l - u p
DQ
C K SQ
DQ
C K SQ
P A o n l y
Non-pin-shared Function Input/Output Ports
VD D
M
X
R e a d D a t a R e g i s t e r
C o n t r o l B i t P u l l - H i g h
O p t i o n
D a t a B u s
W r i t e C o n t r o l R e g i s t e r
C h i p R e s e t
R e a d C o n t r o l R e g i s t e r
W r i t e D a t a R e g i s t e r
D a t a B i t
I N T f o r P A 5 o n l y
T M R f o r P A 4 o n l y
P A 4 / T M R
P A 5 / I N T
W a k e - u p O p t i o n
S y s t e m W a k e - u p
W e a k
P u l l - u p
DQ
C K SQ
DQ
C K SQ
PA4/PA5 Input/Output Ports

HT46R46/C46/R47/C47/R48A/C48A/R49
Rev. 1.41 19 December 30, 2008
VD D
M
X
R e a d D a t a R e g i s t e r
C o n t r o l B i t P u l l - H i g h
O p t i o n
D a t a B u s
W r i t e C o n t r o l R e g i s t e r
C h i p R e s e t
R e a d C o n t r o l R e g i s t e r
W r i t e D a t a R e g i s t e r
D a t a B i t
P B 0 / A N 0 ~ P B 3 / A N 3
A C S 2 ~ A C S 0
T o A / D C o n v e r t e r
P C R 2
P C R 1
P C R 0
W e a k
P u l l - u p
A n a l o g
I n p u t
S e l e c t o r
DQ
C K SQ
DQ
C K SQ
PB Input/Output Ports
VD D
P F D o r P W M W a v e f o r m
M
X
R e a d D a t a R e g i s t e r
C o n t r o l B i t P u l l - H i g h
O p t i o n
D a t a B u s
W r i t e C o n t r o l R e g i s t e r
C h i p R e s e t
R e a d C o n t r o l R e g i s t e r
W r i t e D a t a R e g i s t e r
D a t a B i t
P F D / P W M O p t i o n
M
X
W e a k
P u l l - u p
DQ
C K SQ
DQ
C K SQ
P A 3 / P F D
P D 0 / P W M
P D 0 / P W M 0
P D 1 / P W M 1 ( H T 4 6 R 4 9 2 8 - p i n p a c k a g e o n l y )
PA3/PFD and PD/PWM Input/Output Ports

HT46R46/C46/R47/C47/R48A/C48A/R49
Rev. 1.41 20 December 30, 2008
I/O Pin Structures
The following diagrams illustrate the I/O pin internal
structures. As the exact logical construction of the I/O
pin may differ from these drawings, they are supplied as
a guide only to assist with the functional understanding
of the I/O pins.
Programming Considerations
Within the user program, one of the first things to con-
sider is port initialization. After a reset, all of the I/O data
and port control registers will be set high. This means
that all I/O pins will default to an input state, the level of
which depends on the other connected circuitry and
whether pull-high options have been selected. If the port
control registers, PAC, PBC, PCC and PDC, are then
programmed to setup some pins as outputs, these out-
put pins will have an initial high output value unless the
associated port data registers, PA, PB, PC and PD, are
first programmed. Selecting which pins are inputs and
which are outputs can be achieved byte-wide by loading
the correct values into the appropriate port control regis-
ter or by programming individual bits in the port control
register using the ²SET [m].i²and ²CLR [m].i²instruc-
tions. Note that when using these bit control instruc-
tions, a read-modify-write operation takes place. The
microcontroller must first read in the data on the entire
port, modify it to the required new bit values and then re-
write this data back to the output ports.
Port A has the additional capability of providing wake-up
functions. When the device is in the Power Down Mode,
various methods are available to wake the device up.
One of these is a high to low transition of any of the Port
A pins. Single or multiple pins on Port A can be setup to
have this function.
Note that some devices have different package types
which may result in some I/O pins not being bonded out.
If these pins are setup as inputs they may oscillate and
increase power consumption, especially notable if the
device is in the Power Down Mode. It is therefore recom-
mended that any unbonded pins should be setup as out-
puts, or if setup as inputs, then they should be
connected to pull-high resistors.
Timer/Event Counters
The provision of timers form an important part of any
microcontroller giving the designer a means of carrying
out time related functions. Each device contains an in-
ternal 8-bit count-up timer. With three operating modes,
the timers can be configured to operate as a general
timer, external event counter or as a pulse width mea-
surement device. The provision of an internal 8-stage
prescaler to the timer clock circuitry gives added range
to the timer.
There are two registers related to the Timer/Event
Counter, TMR and TMRC. The TMR register is the reg-
ister that contains the actual timing value. Writing to
TMR places an initial starting value in the Timer/Event
Counter preload register while reading TMR retrieves
the contents of the Timer/Event Counter. The TMRC
register is a Timer/Event Counter control register, which
defines the timer options, and determines how the timer
is to be used. The timer clock source can be configured
to come from the internal system clock source or from
an external clock on shared pin PA4/TMR.
Configuring the Timer/Event Counter Input Clock
Source
The internal timer¢s clock source can originate from ei-
ther the system clock or from an external clock source.
The system clock input timer source is used when the
timer is in the timer mode or in the pulse width measure-
ment mode. The internal timer clock also passes
through a prescaler, the value of which is conditioned by
the bits PSC0, PSC1 and PSC2.
An external clock source is used when the timer is in the
event counting mode, the clock source being provided
on pin-shared pin PA4/TMR. Depending upon the condi-
tion of the TE bit, each high to low, or low to high transi-
tion on the PA4/TMR pin will increment the counter by
one.
T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4
W r i t e t o P o r t R e a d f r o m P o r t
S y s t e m C l o c k
P o r t D a t a
Read/Write Timing
P A 4 / T M R I n p u t
T E
T i m e r / E v e n t C o u n t e r
M o d e C o n t r o l
T O N
P r e l o a d R e g i s t e r
T i m e r / E v e n t C o u n t e r
D a t a B u s
R e l o a d
O v e r f l o w
t o I n t e r r u p t
2
8 - S t a g e P r e s c a l e r
P S C 2 ~ P S C 0
(1/1~1/128)
8 - B i t T i m e r / E v e n t C o u n t e r
T M 1 T M 0
fSYS
P F D
¸
8-bit Timer/Event Counter Structure