Holtek HT46R46 User manual

HT46R46/C46/R47/C47/R48A/C48A/R49
Cost-Effective A/D Type 8-Bit MCU
Rev. 1.41 1 December 30, 2008
General Description
The Cost-Effective A/D Type MCU Devices are a series
of 8-bit high performance RISC architecture
microcontrollers, designed especially for applications
that interface directly to analog signals, such as those
from sensors. All devices include an integrated
multi-channel Analog to Digital Converter in addition to
one or two Pulse Width Modulation outputs. The usual
Holtek MCU features such as power down and wake-up
functions, oscillator options, programmable frequency
divider, etc. combine to ensure user applications require
a minimum of external components.
The benefits of integrated A/D and PWM functions, in
addition to low power consumption, high performance,
I/O flexibility and low-cost, provide these devices with
the versatility to suit a wide range of application possibil-
ities such as sensor signal processing, motor driving, in-
dustrial control, consumer products, subsystem
controllers, etc. Many features are common to all de-
vices, however, they differ in areas such as I/O pin
count, Program Memory capacity, A/D resolution, stack
capacity and package types.
Features
·Operating voltage:
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
·13 to 23 bidirectional I/O lines
·External interrupt input shared with an I/O line
·8-bit programmable Timer/Event Counter with over-
flow interrupt and 7-stage prescaler
·On-chip crystal and RC oscillator
·Watchdog Timer function
·PFD for audio frequency generation
·Power down and wake-up functions to reduce power
consumption
·Up to 0.5ms instruction cycle with 8MHz system clock
at VDD=5V
·4 or 6-level subroutine nesting
·4 channels 8 or 9-bit resolution A/D converter
·1 or 2 channel 8-bit PWM output shared with I/O lines
·Bit manipulation instruction
·Table read instructions
·63 powerful instructions
·All instructions executed in one or two machine
cycles
·Low voltage reset function
·Range of packaging types

Part No. VDD Program
Memory
Data
Memory I/O Timer Int. A/D PWM Stack Package Types
HT46R46
HT46C46
2.2V~
5.5V 1K´14 64´813 8-bit´138-bit´4 8-bit´1416NSOP, 18DIP/SOP, 20SSOP
HT46R47
HT46C47
2.2V~
5.5V 2K´14 64´813 8-bit´139-bit´4 8-bit´1616NSOP, 18DIP/SOP, 20SSOP
HT46R48A
HT46C48A
2.2V~
5.5V 2K´14 88´819 8-bit´139-bit´4 8-bit´1620DIP/SOP, 24SKDIP/SOP/SSOP
HT46R49 2.2V~
5.5V 4K´15 128´823 8-bit´139-bit´4 8-bit´2620DIP/SOP, 24/28SKDIP/SOP
Note: Part numbers including ²C²are mask version devices, ²R²are OTP devices.
For devices that exist in two package formats, the table reflects the situation for the larger package.
Block Diagram
Note: This block diagram represents the OTP devices, for the mask devices there is no Device Programming
Circuitry.
HT46R46/C46/R47/C47/R48A/C48A/R49
Rev. 1.41 2 December 30, 2008
T i m i n g
G e n e r a t o r
S y s t e m R C /
X ' t a l O s c i l l a t o r I n s t r u c t i o n
D ecoder
I n s t r u c t i o n
R e g i s t e r
W D T
O s c i l l a t o r
D a t a
M e m o r y
A d d r e s s D e c o d e r
M e m o r y
P o i n t e r
M X A C C
Look-up
T a b l e
R e g i s t e r
R e s e t &
L V R
C o n f i g .
R e g i s t e r
T i m e r /
C ounter
C o n f i g .
R e g i s t e r
I n t e r r u p t
C i r c u i t
C o n f i g .
R e g i s t e r
I/O
P o r t s
D e v i c e
P r o g r a m m i n g
C i r c u i t r y
C o n f i g u r a t i o n
O p t i o n
P r o g r a m
M e m o r y
A d d r e s s D e c o d e r
S t a c k
S t a c k P o i n t e r
P r o g r a m
C o u n t e r
Look-up
T a b l e
P o i n t e r
T o P r o g r a m
M e m o r y
A L
S h i f t e r
MX
C o n f i g .
R e g i s t e r
P W M
P F D
A / D
C o n v e r t e r
Device Types
Devices which have the letter ²R²within their part number, indicate that they are OTP devices offering the advantages
of easy and effective program updates, using the Holtek range of development and programming tools. These devices
provide the designer with the means for fast and low-cost product development cycles. Devices which have the letter
²C²within their part number indicate that they are mask version devices. These devices offer a complementary device
for applications that are at a mature state in their design process and have high volume and low cost demands.
Fully pin and functionally compatible with their OTP sister devices, the mask version devices provide the ideal substi-
tute for products which have gone beyond their development cycle and are facing cost-down demands.
In this datasheet, for convenience, when describing device functions, only the OTP types are mentioned by name,
however the same described functions also apply to the Mask type devices.
Selection Table
Most features are common to all devices, the main feature distinguishing them are Program Memory capacity, I/O
count, A/D resolution, stack capacity and package types. The following table summarises the main features of each de-
vice.

Pin Assignment
Pin Description
HT46R46, HT46R47
Pin Name I/O Configuration
Option Description
PA0~PA2
PA3/PFD
PA4/TMR
PA5/INT
PA6~PA7
I/O
Pull-high
Wake-up
PA3 or PFD
Bidirectional 8-bit input/output port. Each individual pin on this port can be config-
ured as a wake-up input by a configuration option. Software instructions determine
if the pin is a CMOS output or Schmitt Trigger input. Configuration options deter-
mine which pins on the port have pull-high resistors. Pins PA3, PA4 and PA5 are
pin-shared with PFD, TMR and INT, respectively.
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
I/O Pull-high
Bidirectional 4-bit input/output port. Software instructions determine if the pin is a
CMOS output or Schmitt Trigger input. Configuration options determine which pins
on the port have pull-high resistors. PB is pin-shared with the A/D input pins. The
A/D inputs are selected via software instructions. Once selected as an A/D input,
the I/O function and pull-high resistor options are disabled automatically.
PD0/PWM I/O Pull-high
PD0 or PWM
Bidirectional 1-bit input/output port. Software instructions determine if the pin is a
CMOS output or Schmitt Trigger input.
A configuration option determines if this pin has a pull-high resistor. The PWM out-
put is pin-shared with pin PD0 selected via a configuration option.
OSC1
OSC2
I
O
Crystal
or RC
OSC1, OSC2 are connected to an external RC network or external crystal, deter-
mined by configuration option, for the internal system clock. If the RC system clock op-
tion is selected, pin OSC2 can be used to measure the system clock at 1/4 frequency.
RES I ¾Schmitt Trigger reset input. Active low.
VDD ¾¾
Positive power supply
VSS ¾¾
Negative power supply, ground
Note: 1. Each pin on PA can be programmed through a configuration option to have a wake-up function.
2. Individual pins can be selected to have a pull-high resistor.
3. Pins PB2/AN2~PB3/AN3 exist but are not bonded out on the 16-pin package.
4. unbonded pins should be setup as outputs or as inputs with pull-high resistors to conserve power.
HT46R46/C46/R47/C47/R48A/C48A/R49
Rev. 1.41 3 December 30, 2008
H T 4 6 R 4 6 / H T 4 6 C 4 6
H T 4 6 R 4 7 / H T 4 6 C 4 7
2 0 S S O P - A
P A 4 / T M R
P A 5 / I N T
P A 6
P A 7
O S C 2
O S C 1
V D D
R E S
P D 0 / P W M
N C
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
1
2
3
4
5
6
7
8
9
1 0
P A 3 / P F D
P A 2
P A 1
P A 0
P B 3 / A N 3
N C
P B 2 / A N 2
P B 1 / A N 1
P B 0 / A N 0
V S S
H T 4 6 R 4 6 / H T 4 6 C 4 6
H T 4 6 R 4 7 / H T 4 6 C 4 7
1 8 D I P - A / S O P - A
P A 4 / T M R
P A 5 / I N T
P A 6
P A 7
O S C 2
O S C 1
V D D
R E S
P D 0 / P W M
P A 3 / P F D
P A 2
P A 1
P A 0
P B 3 / A N 3
P B 2 / A N 2
P B 1 / A N 1
P B 0 / A N 0
V S S
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
1 0
1
2
3
4
5
6
7
8
9
H T 4 6 R 4 8 A / H T 4 6 C 4 8 A
2 0 D I P - A / S O P - A
P B 5
P A 4 / T M R
P A 5 / I N T
P A 6
P A 7
O S C 2
O S C 1
V D D
R E S
P D 0 / P W M
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
1
2
3
4
5
6
7
8
9
1 0
P B 4
P A 3 / P F D
P A 2
P A 1
P A 0
P B 3 / A N 3
P B 2 / A N 2
P B 1 / A N 1
P B 0 / A N 0
V S S
H T 4 6 R 4 8 A / H T 4 6 C 4 8 A
2 4 S K D I P - A / S O P - A / S S O P - A
PB5
PB4
P A 3 / P F D
PA2
PA1
PA0
P B 3 / A N 3
P B 2 / A N 2
P B 1 / A N 1
P B 0 / A N 0
VSS
P C 0
PB6
P B 7
P A 4 / T M R
P A 5 / I N T
PA6
PA7
O S C 2
O S C 1
V D D
R E S
P D 0 / P W M
P C 1
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
H T 4 6 R 4 9
2 8 S K D I P - A / S O P - A
PB6
PB7
P A 4 / T M R
P A 5 / I N T
PA6
PA7
O S C 2
O S C 1
V D D
R E S
P D 1 / P W M 1
P D 0 / P W M 0
P C 4
P C 3
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
PB5
PB4
P A 3 / P F D
PA2
PA1
PA0
P B 3 / A N 3
P B 2 / A N 2
P B 1 / A N 1
P B 0 / A N 0
VSS
P C 0
P C 1
PC 2
PB5
PB4
P A 3 / P F D
PA2
PA1
PA0
P B 3 / A N 3
P B 2 / A N 2
P B 1 / A N 1
P B 0 / A N 0
VSS
P C 0
PB6
PB7
P A 4 / T M R
P A 5 / I N T
PA6
PA7
O S C 2
O S C 1
V D D
R E S
P D 1 / P W M 1
P D 0 / P W M 0
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
H T 4 6 R 4 9
2 4 S K D I P - B / S O P - B
H T 4 6 R 4 6 / H T 4 6 C 4 6
H T 4 6 R 4 7 / H T 4 6 C 4 7
1 6 N S O P - A
P A 4 / T M R
P A 5 / I N T
P A 6
P A 7
O S C 2
O S C 1
V D D
R E S
P A 3 / P F D
P A 2
P A 1
P A 0
P B 1 / A N 1
P B 0 / A N 0
V S S
1 6
1 5
1 4
1 3
1 2
1 1
1 0
9
1
2
3
4
5
6
7
8
P D 0 / P W M
H T 4 6 R 4 9
2 0 D I P - A / S O P - A
P A 4 / T M R
P A 5 / I N T
P A 6
P A 7
O S C 2
O S C 1
V D D
R E S
P D 1 / P W M 1
P D 0 / P W M 0
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
1
2
3
4
5
6
7
8
9
1 0
P A 3 / P F D
P A 2
P A 1
P A 0
P B 3 / A N 3
P B 2 / A N 2
P B 1 / A N 1
P B 0 / A N 0
V S S
P C 0

HT46R48A
Pin Name I/O Configuration
Option Description
PA0~PA2
PA3/PFD
PA4/TMR
PA5/INT
PA6~PA7
I/O
Pull-high
Wake-up
PA3 or PFD
Bidirectional 8-bit input/output port. Each individual pin on this port can be config-
ured as a wake-up input by a configuration option. Software instructions determine
if the pin is a CMOS output or Schmitt Trigger input. Configuration options deter-
mine which pins on the port have pull-high resistors. Pins PA3, PA4 and PA5 are
pin-shared with PFD, TMR and INT, respectively.
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4~PB7
I/O Pull-high
Bidirectional 8-bit input/output port. Software instructions determine if the pin is a
CMOS output or Schmitt Trigger input. Configuration options determine which pins
on the port have pull-high resistors. PB is pin-shared with the A/D input pins. The
A/D inputs are selected via software instructions. Once selected as an A/D input,
the I/O function and pull-high resistor options are disabled automatically.
PC0~PC1 I/O Pull-high
Bidirectional 2-bit input/output port. Software instructions determine if the pin is a
CMOS output or Schmitt Trigger input. Configuration options determine which pins
on the port have pull-high resistors.
PD0/PWM I/O Pull-high
I/O or PWM
Bidirectional 1-bit input/output port. Software instructions determine if the pin is a
CMOS output or Schmitt Trigger input. Configuration option determines if this pin
has a pull-high resistor. The PWM output is pin-shared with pin PD0 selected via a
configuration option.
OSC1
OSC2
I
OCrystal or RC
OSC1, OSC2 are connected to an external RC network or external crystal, deter-
mined by configuration option, for the internal system clock. If the RC system clock
option is selected, pin OSC2 can be used to measure the system clock at 1/4 fre-
quency.
RES I ¾Schmitt Trigger reset input. Active low.
VDD ¾¾ Positive power supply
VSS ¾¾ Negative power supply, ground
Note: 1. Each pin on PA can be programmed through a configuration option to have a wake-up function.
2. Individual pins can be selected to have a pull-high resistor.
3. Pins PB4~PB7 exist but are not bonded out on the 20-pin package.
4. Unbonded pins should be setup as outputs or as inputs with pull-high resistors to conserve power.
HT46R46/C46/R47/C47/R48A/C48A/R49
Rev. 1.41 4 December 30, 2008

HT46R49
Pin Name I/O Configuration
Option Description
PA0~PA2
PA3/PFD
PA4/TMR
PA5/INT
PA6~PA7
I/O
Pull-high
Wake-up
PA3 or PFD
Bidirectional 8-bit input/output port. Each individual pin on this port can be config-
ured as a wake-up input by a configuration option. Software instructions deter-
mine if the pin is a CMOS output or Schmitt Trigger input. Configuration options
determine which pins on the port have pull-high resistors. Pins PA3, PA4 and PA5
are pin-shared with PFD, TMR and INT, respectively.
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4~PB7
I/O Pull-high
Bidirectional 8-bit input/output port. Software instructions determine if the pin is a
CMOS output or Schmitt Trigger input. Configuration options determine which
pins on the port have pull-high resistors. PB is pin-shared with the A/D input pins.
The A/D inputs are selected via software instructions. Once selected as an A/D in-
put, the I/O function and pull-high resistor options are disabled automatically.
PC0~PC4 I/O Pull-high
Bidirectional 5-bit input/output port. Software instructions determine if the pin is a
CMOS output or Schmitt Trigger input. Configuration options determine which
pins on the port have pull-high resistors.
PD0/PWM0
PD1/PWM1 I/O Pull-high I/O or PWM
Bidirectional 2-bit input/output port. Software instructions determine if the pin is a
CMOS output or Schmitt Trigger input. Configuration option determines if this pin
has a pull-high resistor. The PWM output are pin-shared with pins PD0 and PD1
selected via a configuration option.
OSC1
OSC2
I
OCrystal or RC
OSC1, OSC2 are connected to an external RC network or external crystal, deter-
mined by configuration option, for the internal system clock. If the RC system
clock option is selected, pin OSC2 can be used to measure the system clock at
1/4 frequency.
RES I ¾Schmitt Trigger reset input. Active low.
VDD ¾¾ Positive power supply
VSS ¾¾ Negative power supply, ground
Note: 1. Each pin on PA can be programmed through a configuration option to have a wake-up function.
2. Individual pins can be selected to have a pull-high resistor.
3. Pins PC1~PC4 exist but are not bonded out on the 20-pin and 24-pin package.
Pins PB4~PB7 exist but are not bonded out on the 20-pin package.
4. Unbonded pins should be setup as outputs or as inputs with pull-high resistors to conserve power.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V Storage Temperature ............................-50°Cto125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V Operating Temperature...........................-40°Cto85°C
IOL Total ..............................................................150mA IOH Total............................................................-100mA
Total Power Dissipation .....................................500mW
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings²may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
HT46R46/C46/R47/C47/R48A/C48A/R49
Rev. 1.41 5 December 30, 2008

D.C. Characteristics Ta=25°C
Symbol Parameter
Test Conditions
Min. Typ. Max. Unit
VDD Conditions
VDD Operating Voltage
¾fSYS=4MHz 2.2 ¾5.5 V
¾fSYS=8MHz 3.3 ¾5.5 V
IDD1 Operating Current
(Crystal OSC)
3V No load, fSYS=4MHz
ADC disable
¾0.6 1.5 mA
5V ¾24mA
IDD2 Operating Current
(RC OSC)
3V No load, fSYS=4MHz
ADC disable
¾0.8 1.5 mA
5V ¾2.5 4 mA
IDD3 Operating Current
(Crystal OSC, RC OSC) 5V No load, fSYS=8MHz ADC disable ¾48mA
ISTB1 Standby Current
(WDT Enabled)
3V No load,
system HALT
¾¾ 5mA
5V ¾¾10 mA
ISTB2 Standby Current
(WDT Disabled)
3V No load,
system HALT
¾¾ 1mA
5V ¾¾ 2mA
VIL1 Input Low Voltage for I/O Ports,
TMR and INT ¾¾ 0¾0.3VDD V
VIH1 Input High Voltage for I/O Ports,
TMR and INT ¾¾
0.7VDD ¾VDD V
VIL2 Input Low Voltage (RES) ¾¾ 0¾0.4VDD V
VIH2 Input High Voltage (RES) ¾¾
0.9VDD ¾VDD V
VLVR Low Voltage Reset ¾¾ 2.7 3.0 3.3 V
IOL I/O Port Sink Current
3V VOL=0.1VDD 48
¾mA
5V VOL=0.1VDD 10 20 ¾mA
IOH I/O Port Source Current
3V VOH=0.9VDD -2-4¾mA
5V VOH=0.9VDD -5-10 ¾mA
RPH Pull-high Resistance
3V ¾20 60 100 kW
5V ¾10 30 50 kW
VAD A/D Input Voltage ¾¾ 0¾VDD V
EAD A/D Conversion Error ¾¾ ¾±0.5 ±1LSB
IADC Additional Power Consumption
if A/D Converter is Used
3V
¾
¾0.5 1 mA
5V ¾1.5 3 mA
HT46R46/C46/R47/C47/R48A/C48A/R49
Rev. 1.41 6 December 30, 2008

A.C. Characteristics Ta=25°C
Symbol Parameter
Test Conditions
Min. Typ. Max. Unit
VDD Conditions
fSYS System Clock
¾2.2V~5.5V 400 ¾4000 kHz
¾3.3V~5.5V 400 ¾8000 kHz
fTIMER Timer I/P Frequency
(TMR)
¾2.2V~5.5V 0 ¾4000 kHz
¾3.3V~5.5V 0 ¾8000 kHz
tWDTOSC Watchdog Oscillator Period
3V ¾45 90 180 ms
5V ¾32 65 130 ms
tWDT1 Watchdog Time-out Period
(RC) ¾¾ 215 ¾216 tWDTOSC
tWDT2 Watchdog Time-out Period
(System Clock) ¾¾ 217 ¾218 tSYS
tRES External Reset Low Pulse Width ¾¾ 1¾¾ms
tSST System Start-up Timer Period ¾Wake-up from HALT ¾1024 ¾*tSYS
tLVR Low Voltage Reset Time ¾¾0.25 1 2 ms
tINT Interrupt Pulse Width ¾¾ 1¾¾ms
tAD1 A/D Clock Period -
HT46R46 ¾¾ 0.5 ¾¾ms
tAD2 A/D Clock Period -
HT46R47/HT46R48A/HT46R49 ¾¾ 1¾¾ms
tADC1 A/D Conversion Time -
HT46R46 ¾¾ ¾
64 ¾tAD1
tADC2 A/D Conversion Time -
HT46R47/HT46R48A/HT46R49 ¾¾ ¾
76 ¾tAD2
tADCS1 A/D Sampling Time -
HT46R46 ¾¾ ¾
32 ¾tAD1
tADCS2 A/D Sampling Time -
HT46R47/HT46R48A/HT46R49 ¾¾ ¾
32 ¾tAD2
Note: *tSYS=1/fSYS
HT46R46/C46/R47/C47/R48A/C48A/R49
Rev. 1.41 7 December 30, 2008

HT46R46/C46/R47/C47/R48A/C48A/R49
Rev. 1.41 8 December 30, 2008
System Architecture
A key factor in the high-performance features of the
Holtek range of Cost-Effective A/D Type
microcontrollers is attributed to the internal system ar-
chitecture. The range of devices take advantage of the
usual features found within RISC microcontrollers pro-
viding increased speed of operation and enhanced per-
formance. The pipelining scheme is implemented in
such a way that instruction fetching and instruction exe-
cution are overlapped, hence instructions are effectively
executed in one cycle, with the exception of branch or
call instructions. An 8-bit wide ALU is used in practically
all operations of the instruction set. It carries out arith-
metic operations, logic operations, rotation, increment,
decrement, branch decisions, etc. The internal data
path is simplified by moving data through the Accumula-
tor and the ALU. Certain internal registers are imple-
mented in the Data Memory and can be directly or
indirectly addressed. The simple addressing methods of
these registers along with additional architectural fea-
tures ensure that a minimum of external components is
required to provide a functional I/O and A/D control sys-
tem with maximum reliability and flexibility. This makes
these devices suitable for low-cost, high-volume pro-
duction for controller applications requiring from 1K up
to 4K words of Program Memory and 64 to 128 bytes of
Data Memory storage.
Clocking and Pipelining
The main system clock, derived from either a Crys-
tal/Resonator or RC oscillator is subdivided into four in-
ternally generated non-overlapping clocks, T1~T4. The
Program Counter is incremented at the beginning of the
T1 clock during which time a new instruction is fetched.
The remaining T2~T4 clocks carry out the decoding and
execution functions. In this way, one T1~T4 clock cycle
forms one instruction cycle. Although the fetching and
execution of instructions takes place in consecutive in-
struction cycles, the pipelining structure of the
microcontroller ensures that instructions are effectively
executed in one instruction cycle. The exception to this
are instructions where the contents of the Program
Counter are changed, such as subroutine calls or
jumps, in which case the instruction will take one more
instruction cycle to execute.
When the RC oscillator is used, OSC2 is freed for use as
a T1 phase clock synchronizing pin. This T1 phase clock
has a frequency of fSYS/4 with a 1:3 high/low duty cycle.
For instructions involving branches, such as jump or call
instructions, two machine cycles are required to com-
plete instruction execution. An extra cycle is required as
the program takes one cycle to first obtain the actual
jump or call address and then another cycle to actually
execute the branch. The requirement for this extra cycle
should be taken into account by programmers in timing
sensitive applications
F e t c h I n s t . ( P C )
E x e c u t e I n s t . ( P C - 1 ) F e t c h I n s t . ( P C + 1 )
E x e c u t e I n s t . ( P C ) F e t c h I n s t . ( P C + 2 )
E x e c u t e I n s t . ( P C + 1 )
P C P C + 1 P C + 2
O s c i l l a t o r C l o c k
( S y s t e m C l o c k )
P h a s e C l o c k T 1
P r o g r a m C o u n t e r
P h a s e C l o c k T 2
P h a s e C l o c k T 3
P h a s e C l o c k T 4
P i p e l i n i n g
System Clocking and Pipelining
F e t c h I n s t . 1 E x e c u t e I n s t . 1
F e t c h I n s t . 2
F l u s h P i p e l i n e
1
2
3
4
5
6D E L A Y :
M O V A , [ 1 2 H ]
C A L L D E L A Y
C P L [ 1 2 H ]
:
:
N O P
E x e c u t e I n s t . 2
F e t c h I n s t . 3
F e t c h I n s t . 6 E x e c u t e I n s t . 6
F e t c h I n s t . 7
Instruction Fetching

HT46R46/C46/R47/C47/R48A/C48A/R49
Rev. 1.41 9 December 30, 2008
Program Counter
During program execution, the Program Counter is used
to keep track of the address of the next instruction to be
executed. It is automatically incremented by one each
time an instruction is executed except for instructions,
such as ²JMP²or ²CALL²that demand a jump to a
non-consecutive Program Memory address. For the
Cost-Effective A/D Type series of microcontrollers, note
that the Program Counter width varies with the Program
Memory capacity depending upon which device is se-
lected. However, it must be noted that only the lower 8
bits, known as the Program Counter Low Register, are
directly addressable by user.
When executing instructions requiring jumps to
non-consecutive addresses such as a jump instruction,
a subroutine call, interrupt or reset, etc., the
microcontroller manages program control by loading the
required address into the Program Counter. For condi-
tional skip instructions, once the condition has been
met, the next instruction, which has already been
fetched during the present instruction execution, is dis-
carded and a dummy cycle takes its place while the cor-
rect instruction is obtained.
The lower byte of the Program Counter, known as the
Program Counter Low register or PCL, is available for
program control and is a readable and writable register.
By transferring data directly into this register, a short
program jump can be executed directly, however, as
only this low byte is available for manipulation, the
jumps are limited to the present page of memory, that is
256 locations. When such program jumps are executed
it should also be noted that a dummy cycle will be in-
serted.
The lower byte of the Program Counter is fully accessi-
ble under program control. Manipulating the PCL might
cause program branching, so an extra cycle is needed
to pre-fetch. Further information on the PCL register can
be found in the Special Function Register section.
Mode
Program Counter Bits
b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Initial Reset 000000000000
External Interrupt 000000000100
Timer/Event Counter
Overflow 000000001000
A/D Converter Interrupt 000000001100
Skip Program Counter + 2
Loading PCL PC11 PC10 PC9 PC8 @7 @6 @5 @4 @3 @2 @1 @0
Jump, Call Branch #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0
Return from Subroutine S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
Program Counter
Note: PC11~PC8: Current Program Counter bits
@7~@0: PCL bits
#11~#0: Instruction code address bits
S11~S0: Stack register bits
For the HT46R49, the Program Counter is 12 bits wide, i.e. from b11~b0.
For the HT46R47 and HT46R48A, the Program Counter is 11 bits wide, i.e. From
b10~b0, therefore the b11 column in the table is not applicable.
For the HT46R46, the Program Counter is 10 bits wide, i.e. from b9~b0, therefore the b11 and
b10 the columns in the table are not applicable.

HT46R46/C46/R47/C47/R48A/C48A/R49
Rev. 1.41 10 December 30, 2008
Stack
This is a special part of the memory which is used to
save the contents of the Program Counter only. The
stack can have either 4 or 6 levels depending upon
which device is selected and is neither part of the data
nor part of the program space, and is neither readable
nor writable. The activated level is indexed by the Stack
Pointer, SP, and is neither readable nor writable. At a
subroutine call or interrupt acknowledge signal, the con-
tents of the Program Counter are pushed onto the stack.
At the end of a subroutine or an interrupt routine, sig-
naled by a return instruction, RET or RETI, the Program
Counter is restored to its previous value from the stack.
After a device reset, the Stack Pointer will point to the
top of the stack.
If the stack is full and an enabled interrupt takes place,
the interrupt request flag will be recorded but the ac-
knowledge signal will be inhibited. When the Stack
Pointer is decremented, by RET or RETI, the interrupt
will be serviced. This feature prevents stack overflow al-
lowing the programmer to use the structure more easily.
However, when the stack is full, a CALL subroutine in-
struction can still be executed which will result in a stack
overflow. Precautions should be taken to avoid such
cases which might cause unpredictable program
branching.
Note: For the HT46R46, 4 levels of stack are available
and for the HT46R47,HT46R48A and
HT46R49, 6 levels of stack are available.
Arithmetic and Logic Unit -ALU
The arithmetic-logic unit or ALU is a critical area of the
microcontroller that carries out arithmetic and logic op-
erations of the instruction set. Connected to the main
microcontroller data bus, the ALU receives related in-
struction codes and performs the required arithmetic or
logical operations after which the result will be placed in
the specified register. As these ALU calculation or oper-
ations may result in carry, borrow or other status
changes, the status register will be correspondingly up-
dated to reflect these changes. The ALU supports the
following functions:
·Arithmetic operations: ADD, ADDM, ADC, ADCM,
SUB, SUBM, SBC, SBCM, DAA
·Logic operations: AND, OR, XOR, ANDM, ORM,
XORM, CPL, CPLA
·Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA,
RLC
·Increment and Decrement INCA, INC, DECA, DEC
·Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ,
SIZA, SDZA, CALL, RET, RETI
Program Memory
The Program Memory is the location where the user code
or program is stored. For microcontrollers, two types of
Program Memory are usually supplied. The first type is
the One-Time Programmable, OTP, memory where us-
ers can program their application code into the device.
Devices with OTP memory are denoted by having an ²R²
within their device name. By using the appropriate pro-
gramming tools, OTP devices offer users the flexibility to
freely develop their applications which may be useful
during debug or for products requiring frequent upgrades
or program changes. OTP devices are also applicable for
use in applications that require low or medium volume
production runs. The other type of memory is the mask
ROM memory, denoted by having a ²C²within the device
name. These devices offer the most cost effective solu-
tions for high volume products.
Structure
The Program Memory has a capacity of 1K by 14, 2K by
14 or 4K by 15 bits depending upon which device is se-
lected. The Program Memory is addressed by the Pro-
gram Counter and also contains data, table information
and interrupt entries. Table data, which can be setup in
any location within the Program Memory, is addressed
by separate table pointer registers.
Special Vectors
Within the Program Memory, certain locations are re-
served for special usage such as reset and interrupts.
·Location 000H
This vector is reserved for use by the device reset for
program initialisation. After a device reset is initiated, the
program will jump to this location and begin execution.
·Location 004H
This vector is used by the external interrupt. If the ex-
ternal interrupt pin on the device goes low, the pro-
gram will jump to this location and begin execution if
the external interrupt is enabled and the stack is not
full.
·Location 008H
This internal vector is used by the Timer/Event Coun-
ter. If a counter overflow occurs, the program will jump
to this location and begin execution if the timer/event
counter interrupt is enabled and the stack is not full.
·Location 00CH
This internal vector is used by the A/D converter.
When an A/D conversion cycle is complete, the pro-
gram will jump to this location and begin execution if
the A/D interrupt is enabled and the stack is not full.
P r o g r a m C o u n t e r
S t a c k L e v e l 1
S t a c k L e v e l 2
S t a c k L e v e l 3
S t a c k L e v e l N
P r o g r a m
M e m o r y
T o p o f S t a c k
S t a c k
P o i n t e r
B o t t o m o f S t a c k