Holtek HT32F12345 User manual

Holtek 32-Bit Microcontroller with Arm®Cortex®-M3 Core
HT32F12345
User Manual
Revision: V1.10 Date: November 28, 2018

Rev. 1.10 2 of 590 November 28, 2018
32-Bit Arm®Cortex®-M3 MCU
HT32F12345
Table of Contents
Table of Contents
1 Introduction........................................................................................................... 27
Overview.............................................................................................................................. 27
Features............................................................................................................................... 28
Device Information............................................................................................................... 32
Block Diagram ..................................................................................................................... 33
2 Document Conventions ....................................................................................... 34
3 System Architecture............................................................................................. 35
Arm®Cortex®-M3 Processor ................................................................................................ 35
Bus Architecture................................................................................................................... 36
Memory Organization .......................................................................................................... 37
Memory Map................................................................................................................................... 38
Embedded Flash Memory............................................................................................................... 41
Embedded SRAM Memory ............................................................................................................. 41
AHB Peripherals ............................................................................................................................. 41
APB Peripherals ............................................................................................................................. 41
4 Flash Memory Controller (FMC) .......................................................................... 42
Introduction .......................................................................................................................... 42
Features............................................................................................................................... 42
Functional Descriptions ....................................................................................................... 43
Flash Memory Map ......................................................................................................................... 43
Flash Memory Architecture ............................................................................................................. 44
Wait State Setting ........................................................................................................................... 44
Booting Conguration ..................................................................................................................... 45
Page Erase ..................................................................................................................................... 46
Mass Erase..................................................................................................................................... 47
Word Programming......................................................................................................................... 48
Option Byte Description .................................................................................................................. 49
Page Erase / Program Protection ................................................................................................... 50
Security Protection.......................................................................................................................... 51
Register Map ....................................................................................................................... 52
Register Descriptions........................................................................................................... 53
Flash Target Address Register – TADR .......................................................................................... 53
Flash Write Data Register – WRDR ............................................................................................... 54
Flash Operation Command Register – OCMR ............................................................................... 55
Flash Operation Control Register – OPCR..................................................................................... 56
Flash Operation Interrupt Enable Register – OIER ........................................................................ 57
Flash Operation Interrupt and Status Register – OISR .................................................................. 58
Flash Page Erase / program Protection Status Register – PPSR .................................................. 59
Flash Security Protection Status Register – CPSR ........................................................................ 60

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Table of Contents Table of Contents
Flash Vector Mapping Control Register – VMCR ........................................................................... 61
Flash Manufacturer and Device ID Register – MDID...................................................................... 62
Flash Page Number Status Register – PNSR ................................................................................ 63
Flash Page Size Status Register – PSSR ...................................................................................... 64
Device ID Register – DID................................................................................................................ 65
Flash Pre-fetch Control Register – CFCR ...................................................................................... 66
SRAM Booting Vector Register n – SBVTn, n = 0 ~ 3 .................................................................... 67
Custom ID Register n – CIDRn, n = 0 ~ 3 ...................................................................................... 68
5 Power Control Unit (PWRCU) .............................................................................. 69
Introduction .......................................................................................................................... 69
Features............................................................................................................................... 70
Functional Descriptions ....................................................................................................... 70
Backup Domain .............................................................................................................................. 70
VDD Power Domain.......................................................................................................................... 71
1.5 V Power Domain....................................................................................................................... 73
Operation Modes ............................................................................................................................ 73
Register Map ....................................................................................................................... 75
Register Descriptions........................................................................................................... 76
Backup Domain Status Register – BAKSR..................................................................................... 76
Backup Domain Control Register – BAKCR ................................................................................... 77
Backup Domain Test Register – BAKTEST .................................................................................... 79
Low Voltage / Brown Out Detect Control and Status Register – LVDCSR ..................................... 79
Backup Register n – BAKREGn, n = 0 ~ 9 ..................................................................................... 81
6 Clock Control Unit (CKCU) .................................................................................. 82
Introduction .......................................................................................................................... 82
Features............................................................................................................................... 82
Functional Descriptions ....................................................................................................... 84
High Speed External Crystal Oscillator (HSE)................................................................................ 84
High Speed Internal RC Oscillator (HSI) ........................................................................................ 85
Auto Trimming of High Speed Internal RC Oscillator (HSI) ............................................................ 85
Phase Locked Loop – PLL.............................................................................................................. 87
USB Phase Locked Loop – USB PLL............................................................................................. 88
Low Speed External Crystal Oscillator – LSE................................................................................. 90
Low Speed Internal RC Oscillator – LSI ......................................................................................... 90
Clock Ready Flag ........................................................................................................................... 90
System Clock (CK_SYS) Selection ................................................................................................ 91
HSE Clock Monitor ......................................................................................................................... 91
Clock Output Capability .................................................................................................................. 92
Register Map ....................................................................................................................... 92
Register Descriptions........................................................................................................... 93
Global Clock Conguration Register – GCFGR.............................................................................. 93
Global Clock Control Register – GCCR.......................................................................................... 94

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Table of Contents
Global Clock Status Register – GCSR ........................................................................................... 96
Global Clock Interrupt Register – GCIR.......................................................................................... 97
PLL Conguration Register – PLLCFGR ........................................................................................ 99
PLL Control Register – PLLCR..................................................................................................... 100
AHB Conguration Register – AHBCFGR .................................................................................... 101
AHB Clock Control Register – AHBCCR ..................................................................................... 102
APB Conguration Register – APBCFGR..................................................................................... 104
APB Clock Control Register 0 – APBCCR0.................................................................................. 105
APB Clock Control Register 1 – APBCCR1.................................................................................. 106
Clock Source Status Register – CKST ......................................................................................... 108
APB Peripheral Clock Selection Register 0 – APBPCSR0 .......................................................... 109
APB Peripheral Clock Selection Register 1 – APBPCSR1 ...........................................................111
HSI Control Register – HSICR ......................................................................................................112
HSI Auto Trimming Counter Register – HSIATCR ........................................................................113
Low Power Control Register – LPCR ..........................................................................................114
MCU Debug Control Register – MCUDBGCR ..............................................................................115
7 Reset Control Unit (RSTCU) .............................................................................. 117
Introduction ........................................................................................................................ 117
Functional Descriptions ..................................................................................................... 117
Power On Reset ............................................................................................................................117
System Reset ................................................................................................................................118
AHB and APB Unit Reset...............................................................................................................118
Register Map ..................................................................................................................... 118
Register Descriptions......................................................................................................... 119
Global Reset Status Register – GRSR ..........................................................................................119
AHB Peripheral Reset Register – AHBPRSTR............................................................................. 120
APB Peripheral Reset Register 0 – APBPRSTR0 ........................................................................ 121
APB Peripheral Reset Register 1 – APBPRSTR1 ........................................................................ 122
8 General Purpose I/O (GPIO)............................................................................... 124
Introduction ........................................................................................................................ 124
Features............................................................................................................................. 125
Functional Descriptions ..................................................................................................... 125
Default GPIO Pin Conguration.................................................................................................... 125
General Purpose I/O – GPIO........................................................................................................ 125
GPIO Locking Mechanism ............................................................................................................ 127
Register Map ..................................................................................................................... 127
Register Descriptions......................................................................................................... 128
Port A Data Direction Control Register – PADIRCR ..................................................................... 128
Port A Input Function Enable Control Register – PAINER............................................................ 129
Port A Pull-Up Selection Register – PAPUR ................................................................................. 129
Port A Pull-Down Selection Register – PAPDR ............................................................................ 130
Port A Open Drain Selection Register – PAODR.......................................................................... 131

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Table of Contents Table of Contents
Port A Output Current Drive Selection Register – PADRVR ......................................................... 131
Port A Lock Register – PALOCKR ................................................................................................ 132
Port A Data Input Register – PADINR........................................................................................... 133
Port A Output Data Register – PADOUTR .................................................................................... 133
Port A Output Set / Reset Control Register – PASRR .................................................................. 134
Port A Output Reset Register – PARR.......................................................................................... 135
Port B Data Direction Control Register – PBDIRCR..................................................................... 135
Port B Input Function Enable Control Register – PBINER ........................................................... 136
Port B Pull-Up Selection Register – PBPUR ................................................................................ 136
Port B Pull-Down Selection Register – PBPDR............................................................................ 137
Port B Open Drain Selection Register – PBODR ......................................................................... 137
Port B Output Current Drive Selection Register – PBDRVR ........................................................ 138
Port B Lock Register – PBLOCKR................................................................................................ 138
Port B Data Input Register – PBDINR .......................................................................................... 139
Port B Output Data Register – PBDOUTR ................................................................................... 140
Port B Output Set / Reset Control Register – PBSRR.................................................................. 141
Port B Output Reset Register – PBRR ......................................................................................... 142
Port C Data Direction Control Register – PCDIRCR .................................................................... 142
Port C Input Function Enable Control Register – PCINER ........................................................... 143
Port C Pull-Up Selection Register – PCPUR ................................................................................ 143
Port C Pull-Down Selection Register – PCPDR ........................................................................... 144
Port C Open Drain Selection Register – PCODR ......................................................................... 145
Port C Output Current Drive Selection Register – PCDRVR ........................................................ 145
Port C Lock Register – PCLOCKR ............................................................................................... 146
Port C Data Input Register – PCDINR.......................................................................................... 147
Port C Output Data Register – PCDOUTR ................................................................................... 148
Port C Output Set / Reset Control Register – PCSRR ................................................................. 149
Port C Output Reset Register – PCRR......................................................................................... 150
Port D Data Direction Control Register – PDDIRCR .................................................................... 150
Port D Input Function Enable Control Register – PDINER ........................................................... 151
Port D Pull-Up Selection Register – PDPUR ................................................................................ 152
Port D Pull-Down Selection Register – PDPDR ........................................................................... 153
Port D Open Drain Selection Register – PDODR ......................................................................... 154
Port D Output Current Drive Selection Register – PDDRVR ........................................................ 154
Port D Lock Register – PDLOCKR ............................................................................................... 155
Port D Data Input Register – PDDINR.......................................................................................... 156
Port D Output Data Register – PDDOUTR ................................................................................... 156
Port D Output Set / Reset Control Register – PDSRR ................................................................. 157
Port D Output Reset Register – PDRR......................................................................................... 158
9 Alternate Function Input / Output Control Unit (AFIO).................................... 159
Introduction ........................................................................................................................ 159
Features............................................................................................................................. 160
Functional Descriptions ..................................................................................................... 160
External Interrupt Pin Selection .................................................................................................... 160

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Alternate Function......................................................................................................................... 161
Lock Mechanism .......................................................................................................................... 161
Register Map ..................................................................................................................... 161
Register Descriptions......................................................................................................... 162
EXTI Source Selection Register 0 – ESSR0 ................................................................................ 162
EXTI Source Selection Register 1 – ESSR1 ................................................................................ 163
GPIO x Conguration Low Register – GPxCFGLR, x = A, B, C, D............................................... 164
GPIO x Conguration High Register – GPxCFGHR, x = A, B, C, D ............................................. 165
10 Nested Vectored Interrupt Controller (NVIC).................................................. 166
Introduction ........................................................................................................................ 166
Features............................................................................................................................. 169
Functional Descriptions ..................................................................................................... 169
SysTick Calibration ....................................................................................................................... 169
Register Map ..................................................................................................................... 169
11 External Interrupt / Event Controller (EXTI).................................................... 171
Introduction ........................................................................................................................ 171
Features............................................................................................................................. 171
Functional Descriptions ..................................................................................................... 172
Wakeup Event Management......................................................................................................... 172
External Interrupt / Event Line Mapping ....................................................................................... 173
Interrupt and De-bounce............................................................................................................... 173
Register Map ..................................................................................................................... 174
Register Descriptions......................................................................................................... 175
EXTI Interrupt Conguration Register n – EXTICFGRn, n = 0 ~ 15 ............................................. 175
EXTI Interrupt Control Register – EXTICR ................................................................................... 176
EXTI Interrupt Edge Flag Register – EXTIEDGEFLGR................................................................ 176
EXTI Interrupt Edge Status Register – EXTIEDGESR ................................................................. 177
EXTI Interrupt Software Set Command Register – EXTISSCR.................................................... 177
EXTI Interrupt Wakeup Control Register – EXTIWAKUPCR ........................................................ 178
EXTI Interrupt Wakeup Polarity Register – EXTIWAKUPPOLR ................................................... 179
EXTI Interrupt Wakeup Flag Register – EXTIWAKUPFLG........................................................... 179
12 Analog to Digital Converter (ADC) .................................................................. 180
Introduction ........................................................................................................................ 180
Features............................................................................................................................. 181
Functional Descriptions ..................................................................................................... 182
ADC Clock Setup.......................................................................................................................... 182
Regular and High Priority Channel Selection ............................................................................... 182
Conversion Modes........................................................................................................................ 182
Start Conversion on External Event.............................................................................................. 187
High Priority Group Management ................................................................................................. 188
Sampling Time Setting.................................................................................................................. 188

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Table of Contents Table of Contents
Data Format and Alignment.......................................................................................................... 190
Analog Watchdog.......................................................................................................................... 190
Interrupts....................................................................................................................................... 190
PDMA Request ............................................................................................................................ 191
Register Map ..................................................................................................................... 191
Register Descriptions......................................................................................................... 193
ADC Reset Register – ADCRST................................................................................................... 193
ADC Regular Conversion Mode Register – ADCCONV ............................................................... 194
ADC High Priority Conversion Mode Register – ADCHCONV...................................................... 195
ADC Regular Conversion List Register 0 – ADCLST0 ................................................................. 196
ADC Regular Conversion List Register 1 – ADCLST1 ................................................................. 197
ADC Regular Conversion List Register 2 – ADCLST2 ................................................................. 198
ADC High Priority Conversion List Register – ADCHLST............................................................. 199
ADC Input Offset Register n – ADCOFRn, n = 0 ~ 11 .................................................................. 200
ADC Input Sampling Time Register n – ADCSTRn, n = 0 ~ 11 .................................................... 201
ADC Regular Conversion Data Register y – ADCDRy, y = 0 ~ 11................................................ 201
ADC High Priority Conversion Data Register y – ADCHDRy, y = 0 ~ 3........................................ 202
ADC Regular Trigger Control Register – ADCTCR....................................................................... 203
ADC Regular Trigger Source Register – ADCTSR ....................................................................... 204
ADC High Priority Trigger Control Register – ADCHTCR ............................................................. 205
ADC High Priority Trigger Source Register – ADCHTSR ............................................................. 206
ADC Watchdog Control Register – ADCWCR .............................................................................. 207
ADC Watchdog Lower Threshold Register – ADCLTR ................................................................. 208
ADC Watchdog Upper Threshold Register – ADCUTR ................................................................ 208
ADC Interrupt Enable Register – ADCIER.................................................................................... 209
ADC Interrupt Raw Status Register – ADCIRAW ......................................................................... 210
ADC Interrupt Status Register – ADCISR......................................................................................211
ADC Interrupt Clear Register – ADCICLR .................................................................................... 213
ADC DMA Request Register – ADCDMAR................................................................................... 214
13 Comparator (CMP) ............................................................................................ 215
Introduction ........................................................................................................................ 215
Features............................................................................................................................. 215
Functional Descriptions ..................................................................................................... 216
Comparator Inputs and Output ..................................................................................................... 216
Comparator Reference Voltage .................................................................................................... 216
Interrupts and Wakeup.................................................................................................................. 217
Power Mode and Hysteresis......................................................................................................... 218
Comparator Write-Protected mechanism ..................................................................................... 218
Register Map ..................................................................................................................... 218
Register Descriptions......................................................................................................... 219
Comparator Control Register n – CMPCRn, n = 0 ~ 1 ................................................................. 219
Comparator Voltage Reference Value Register n – CVRVALRn, n = 0 ~ 1 .................................. 221
Comparator Interrupt Enable Register n – CMPIERn, n = 0 ~ 1................................................... 222
Comparator Transition Flag Register n – CMPTFRn, n = 0 ~ 1.................................................... 223

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14 General-Purpose Timer (GPTM) ...................................................................... 224
Introduction ........................................................................................................................ 224
Features............................................................................................................................. 225
Functional Descriptions ..................................................................................................... 225
Counter Mode ............................................................................................................................... 225
Clock Controller ............................................................................................................................ 227
Trigger Controller.......................................................................................................................... 228
Slave Controller ............................................................................................................................ 230
Master Controller .......................................................................................................................... 232
Channel Controller........................................................................................................................ 232
Input Stage ................................................................................................................................... 235
Output Stage................................................................................................................................. 236
Update Management .................................................................................................................... 240
Quadrature Decoder ..................................................................................................................... 240
Digital Filter................................................................................................................................... 242
Clearing the CHxOREF when ETIF is high................................................................................... 243
Single Pulse Mode........................................................................................................................ 244
Asymmetric PWM Mode ............................................................................................................... 246
Time Interconnection .................................................................................................................... 246
Trigger ADC Start.......................................................................................................................... 249
PDMA Request ............................................................................................................................. 249
Register Map ..................................................................................................................... 250
Register Descriptions......................................................................................................... 251
Timer Counter Conguration Register – CNTCFR ....................................................................... 251
Timer Mode Conguration Register – MDCFR............................................................................. 252
Timer Trigger Conguration Register – TRCFR............................................................................ 255
Timer Counter Register – CTR ..................................................................................................... 257
Channel 0 Input Conguration Register – CH0ICFR .................................................................... 258
Channel 1 Input Conguration Register – CH1ICFR .................................................................... 259
Channel 2 Input Conguration Register – CH2ICFR .................................................................... 260
Channel 3 Input Conguration Register – CH3ICFR .................................................................... 262
Channel 0 Output Conguration Register – CH0OCFR ............................................................... 263
Channel 1 Output Conguration Register – CH1OCFR ............................................................... 265
Channel 2 Output Conguration Register – CH2OCFR ............................................................... 266
Channel 3 Output Conguration Register – CH3OCFR ............................................................... 268
Channel Control Register – CHCTR............................................................................................. 270
Channel Polarity Conguration Register – CHPOLR.................................................................... 271
Timer PDMA/Interrupt Control Register – DICTR......................................................................... 272
Timer Event Generator Register – EVGR..................................................................................... 273
Timer Interrupt Status Register – INTSR...................................................................................... 275
Timer Counter Register – CNTR................................................................................................... 277
Timer Prescaler Register – PSCR ................................................................................................ 277
Timer Counter Reload Register – CRR ........................................................................................ 278
Channel 0 Capture / Compare Register – CH0CCR .................................................................... 278

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Channel 1 Capture / Compare Register – CH1CCR .................................................................... 279
Channel 2 Capture / Compare Register – CH2CCR .................................................................... 280
Channel 3 Capture / Compare Register – CH3CCR .................................................................... 281
Channel 0 Asymmetric Compare Register – CH0ACR................................................................. 282
Channel 1 Asymmetric Compare Register – CH1ACR................................................................. 282
Channel 2 Asymmetric Compare Register – CH2ACR................................................................. 283
Channel 3 Asymmetric Compare Register – CH3ACR................................................................. 283
15 Basic Function Timer (BFTM).......................................................................... 284
Introduction ........................................................................................................................ 284
Features............................................................................................................................. 284
Functional Description ....................................................................................................... 285
Repetitive Mode............................................................................................................................ 285
One Shot Mode............................................................................................................................. 286
Trigger ADC Start.......................................................................................................................... 287
Register Map ..................................................................................................................... 287
Register Descriptions......................................................................................................... 288
BFTM Control Register – BFTMCR .............................................................................................. 288
BFTM Status Register – BFTMSR................................................................................................ 289
BFTM Counter Register – BFTMCNTR ........................................................................................ 289
BFTM Compare Value Register – BFTMCMPR ........................................................................... 290
16 Motor Control Timer (MCTM) ........................................................................... 291
Introduction ........................................................................................................................ 291
Features............................................................................................................................. 292
Functional Descriptions ..................................................................................................... 293
Counter Mode ............................................................................................................................... 293
Clock Controller ............................................................................................................................ 296
Trigger Controller.......................................................................................................................... 297
Slave Controller ............................................................................................................................ 298
Master Controller .......................................................................................................................... 300
Channel Controller........................................................................................................................ 301
Input Stage ................................................................................................................................... 303
Output Stage................................................................................................................................. 304
Update Management .................................................................................................................... 313
Quadrature Decoder ..................................................................................................................... 315
Digital Filter................................................................................................................................... 317
Clearing CHxOREF when ETIF is high......................................................................................... 317
Single Pulse Mode........................................................................................................................ 318
Asymmetric PWM Mode ............................................................................................................... 320
Timer Interconnection ................................................................................................................... 320
Trigger ADC Start.......................................................................................................................... 324
Lock Level Table ........................................................................................................................... 324
PDMA Request ............................................................................................................................. 325

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Register Map ..................................................................................................................... 326
Register Descriptions......................................................................................................... 327
Timer Counter Conguration Register – CNTCFR ....................................................................... 327
Timer Mode Conguration Register – MDCFR............................................................................. 328
Timer Trigger Conguration Register – TRCFR............................................................................ 331
Timer Counter Register – CTR ..................................................................................................... 333
Channel 0 Input Conguration Register – CH0ICFR .................................................................... 334
Channel 1 Input Conguration Register – CH1ICFR .................................................................... 335
Channel 2 Input Conguration Register – CH2ICFR .................................................................... 336
Channel 3 Input Conguration Register – CH3ICFR .................................................................... 338
Channel 0 Output Conguration Register – CH0OCFR ............................................................... 339
Channel 1 Output Conguration Register – CH1OCFR ............................................................... 341
Channel 2 Output Conguration Register – CH2OCFR ............................................................... 342
Channel 3 Output Conguration Register – CH3OCFR ............................................................... 344
Channel Control Register – CHCTR............................................................................................. 345
Channel Polarity Conguration Register – CHPOLR.................................................................... 347
Channel Break Conguration Register – CHBRKCFR ................................................................. 348
Channel Break Control Register – CHBRKCTR ........................................................................... 349
Timer PDMA / Interrupt Control Register – DICTR ....................................................................... 352
Timer Event Generator Register – EVGR..................................................................................... 353
Timer Interrupt Status Register – INTSR...................................................................................... 355
Timer Counter Register – CNTR................................................................................................... 357
Timer Prescaler Register – PSCR ................................................................................................ 358
Timer Counter Reload Register – CRR ........................................................................................ 358
Timer Repetition Register – REPR ............................................................................................... 359
Channel 0 Capture / Compare Register – CH0CCR .................................................................... 359
Channel 1 Capture / Compare Register – CH1CCR .................................................................... 360
Channel 2 Capture / Compare Register – CH2CCR .................................................................... 361
Channel 3 Capture / Compare Register – CH3CCR .................................................................... 362
Channel 0 Asymmetric Compare Register – CH0ACR................................................................. 363
Channel 1 Asymmetric Compare Register – CH1ACR................................................................. 363
Channel 2 Asymmetric Compare Register – CH2ACR................................................................. 364
Channel 3 Asymmetric Compare Register – CH3ACR................................................................. 364
17 Real Time Clock (RTC) ..................................................................................... 365
Introduction ........................................................................................................................ 365
Features............................................................................................................................. 365
Functional Descriptions ..................................................................................................... 366
RTC Related Register Reset ........................................................................................................ 366
Reading RTC Register.................................................................................................................. 366
Low Speed Clock Conguration ................................................................................................... 366
RTC Counter Operation................................................................................................................ 366
Interrupt and Wakeup Control....................................................................................................... 367
RTCOUT Output Pin Conguration............................................................................................... 367