Holtek HT32F54231 User manual

Holtek 32-Bit Microcontroller with Arm®Cortex®-M0+ Core
HT32F54231/HT32F54241
HT32F54243/HT32F54253
User Manual
Revision: V1.00 Date: January 28, 2022

Rev. 1.00 2 of 576 January 28, 2022
32-Bit Arm®Cortex®-M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
Table of Contents
Table of Contents
1 Introduction........................................................................................................... 25
Overview.............................................................................................................................. 25
Features............................................................................................................................... 25
Device Information............................................................................................................... 30
Block Diagram ..................................................................................................................... 31
2 Document Conventions ....................................................................................... 33
3 System Architecture............................................................................................. 34
Arm®Cortex®-M0+ Processor .............................................................................................. 34
Bus Architecture................................................................................................................... 35
Memory Organization .......................................................................................................... 36
Memory Map................................................................................................................................... 37
Embedded Flash Memory............................................................................................................... 42
Embedded SRAM Memory ............................................................................................................. 42
AHB Peripherals ............................................................................................................................. 42
APB Peripherals ............................................................................................................................. 42
4 Flash Memory Controller (FMC) .......................................................................... 43
Introduction .......................................................................................................................... 43
Features............................................................................................................................... 43
Functional Descriptions ....................................................................................................... 44
Flash Memory Map ......................................................................................................................... 44
Flash Memory Architecture ............................................................................................................. 45
Wait State Setting ........................................................................................................................... 45
Booting Conguration ..................................................................................................................... 46
Page Erase ..................................................................................................................................... 46
Mass Erase..................................................................................................................................... 48
Word Programming......................................................................................................................... 49
Option Byte Description .................................................................................................................. 50
Page Erase/Program Protection ..................................................................................................... 51
Security Protection.......................................................................................................................... 52
Register Map ....................................................................................................................... 53
Register Descriptions........................................................................................................... 54
Flash Target Address Register – TADR .......................................................................................... 54
Flash Write Data Register – WRDR ............................................................................................... 55
Flash Operation Command Register – OCMR ............................................................................... 56
Flash Operation Control Register – OPCR..................................................................................... 57
Flash Operation Interrupt Enable Register – OIER ........................................................................ 58
Flash Operation Interrupt and Status Register – OISR .................................................................. 59
Flash Page Erase/Program Protection Status Register – PPSR.................................................... 61
Flash Security Protection Status Register – CPSR ........................................................................ 62

Rev. 1.00 3 of 576 January 28, 2022
32-Bit Arm®Cortex®-M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
Table of Contents Table of Contents
Flash Vector Mapping Control Register – VMCR ........................................................................... 63
Flash Manufacturer and Device ID Register – MDID...................................................................... 64
Flash Page Number Status Register – PNSR ................................................................................ 65
Flash Page Size Status Register – PSSR ...................................................................................... 66
Device ID Register – DIDR ............................................................................................................. 66
Flash Pre-fetch Control Register – CFCR ...................................................................................... 67
Custom ID Register n – CIDRn (n = 0 ~ 3) ..................................................................................... 68
5 Power Control Unit (PWRCU) .............................................................................. 69
Introduction .......................................................................................................................... 69
Features............................................................................................................................... 70
Functional Descriptions ....................................................................................................... 70
VDD Power Domain.......................................................................................................................... 70
VCORE Power Domain....................................................................................................................... 72
Operation Modes ............................................................................................................................ 72
Register Map ....................................................................................................................... 74
Register Descriptions........................................................................................................... 75
Power Control Status Register – PWRSR ...................................................................................... 75
Power Control Register – PWRCR ................................................................................................. 76
Low Voltage / Brown Out Detect Control and Status Register – LVDCSR ..................................... 78
Power Control LDO Status Register – PWRLDOSR ...................................................................... 79
6 Clock Control Unit (CKCU) .................................................................................. 80
Introduction .......................................................................................................................... 80
Features............................................................................................................................... 82
Functional Descriptions ....................................................................................................... 82
High Speed External Crystal Oscillator – HSE ............................................................................... 82
High Speed Internal RC Oscillator – HSI........................................................................................ 83
Auto Trimming of High Speed Internal RC Oscillator – HSI............................................................ 83
Phase Locked Loop – PLL.............................................................................................................. 85
Low Speed External Crystal Oscillator – LSE................................................................................. 86
Low Speed Internal RC Oscillator – LSI ......................................................................................... 87
Clock Ready Flag ........................................................................................................................... 87
System Clock (CK_SYS) Selection ................................................................................................ 87
HSE Clock Monitor ......................................................................................................................... 88
Clock Output Capability .................................................................................................................. 88
Register Map ....................................................................................................................... 89
Register Descriptions........................................................................................................... 90
Global Clock Conguration Register – GCFGR.............................................................................. 90
Global Clock Control Register – GCCR.......................................................................................... 91
Global Clock Status Register – GCSR ........................................................................................... 92
Global Clock Interrupt Register – GCIR.......................................................................................... 93
PLL Conguration Register – PLLCFGR ........................................................................................ 94
PLL Control Register – PLLCR....................................................................................................... 95

Rev. 1.00 4 of 576 January 28, 2022
32-Bit Arm®Cortex®-M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
Table of Contents
AHB Conguration Register – AHBCFGR ...................................................................................... 96
AHB Clock Control Register – AHBCCR ........................................................................................ 97
APB Conguration Register – APBCFGR....................................................................................... 99
APB Clock Control Register 0 – APBCCR0.................................................................................. 100
APB Clock Control Register 1 – APBCCR1.................................................................................. 102
Clock Source Status Register – CKST ......................................................................................... 104
APB Peripheral Clock Selection Register 0 – APBPCSR0........................................................... 105
APB Peripheral Clock Selection Register 1 – APBPCSR1........................................................... 107
HSI Control Register – HSICR...................................................................................................... 109
HSI Auto Trimming Counter Register – HSIATCR .........................................................................110
APB Peripheral Clock Selection Register 2 – APBPCSR2............................................................111
MCU Debug Control Register – MCUDBGCR...............................................................................112
7 Reset Control Unit (RSTCU) .............................................................................. 115
Introduction ........................................................................................................................ 115
Functional Descriptions ..................................................................................................... 115
Power-On Reset ............................................................................................................................115
System Reset ................................................................................................................................116
AHB and APB Unit Reset...............................................................................................................116
Register Map ..................................................................................................................... 116
Register Descriptions......................................................................................................... 117
Global Reset Status Register – GRSR ..........................................................................................117
AHB Peripheral Reset Register – AHBPRSTR..............................................................................118
APB Peripheral Reset Register 0 – APBPRSTR0 .........................................................................119
APB Peripheral Reset Register 1 – APBPRSTR1 ........................................................................ 121
8 General Purpose I/O (GPIO)............................................................................... 123
Introduction ........................................................................................................................ 123
Features............................................................................................................................. 124
Functional Descriptions ..................................................................................................... 124
Default GPIO Pin Conguration.................................................................................................... 124
General Purpose I/O – GPIO........................................................................................................ 124
GPIO Locking Mechanism ............................................................................................................ 126
Register Map ..................................................................................................................... 126
Register Descriptions......................................................................................................... 128
Port A Data Direction Control Register – PADIRCR ..................................................................... 128
Port A Input Function Enable Control Register – PAINER ............................................................ 129
Port A Pull-Up Selection Register – PAPUR ................................................................................. 130
Port A Pull-Down Selection Register – PAPDR ............................................................................ 131
Port A Open-Drain Selection Register – PAODR.......................................................................... 132
Port A Drive Current Selection Register – PADRVR..................................................................... 133
Port A Lock Register – PALOCKR ................................................................................................ 134
Port A Data Input Register – PADINR........................................................................................... 135
Port A Output Data Register – PADOUTR .................................................................................... 135

Rev. 1.00 5 of 576 January 28, 2022
32-Bit Arm®Cortex®-M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
Table of Contents Table of Contents
Port A Output Set/Reset Control Register – PASRR .................................................................... 136
Port A Output Reset Register – PARR.......................................................................................... 137
Port B Data Direction Control Register – PBDIRCR..................................................................... 137
Port B Input Function Enable Control Register – PBINER ........................................................... 138
Port B Pull-Up Selection Register – PBPUR ................................................................................ 139
Port B Pull-Down Selection Register – PBPDR............................................................................ 140
Port B Open-Drain Selection Register – PBODR ......................................................................... 141
Port B Drive Current Selection Register – PBDRVR .................................................................... 142
Port B Lock Register – PBLOCKR................................................................................................ 143
Port B Data Input Register – PBDINR .......................................................................................... 144
Port B Output Data Register – PBDOUTR ................................................................................... 144
Port B Output Set/Reset Control Register – PBSRR.................................................................... 145
Port B Output Reset Register – PBRR ......................................................................................... 146
Port C Data Direction Control Register – PCDIRCR .................................................................... 147
Port C Input Function Enable Control Register – PCINER ........................................................... 148
Port C Pull-Up Selection Register – PCPUR ................................................................................ 149
Port C Pull-Down Selection Register – PCPDR ........................................................................... 150
Port C Open-Drain Selection Register – PCODR......................................................................... 151
Port C Drive Current Selection Register – PCDRVR.................................................................... 152
Port C Lock Register – PCLOCKR ............................................................................................... 153
Port C Data Input Register – PCDINR.......................................................................................... 154
Port C Output Data Register – PCDOUTR ................................................................................... 155
Port C Output Set/Reset Control Register – PCSRR ................................................................... 156
Port C Output Reset Register – PCRR......................................................................................... 157
Port D Data Direction Control Register – PDDIRCR .................................................................... 158
Port D Input Function Enable Control Register – PDINER ........................................................... 159
Port D Pull-Up Selection Register – PDPUR ................................................................................ 160
Port D Pull-Down Selection Register – PDPDR ........................................................................... 161
Port D Open-Drain Selection Register – PDODR......................................................................... 162
Port D Drive Current Selection Register – PDDRVR.................................................................... 163
Port D Lock Register – PDLOCKR ............................................................................................... 164
Port D Data Input Register – PDDINR.......................................................................................... 165
Port D Output Data Register – PDDOUTR ................................................................................... 165
Port D Output Set/Reset Control Register – PDSRR ................................................................... 166
Port D Output Reset Register – PDRR......................................................................................... 167
9 Alternate Function Input/Output Control Unit (AFIO)...................................... 168
Introduction ........................................................................................................................ 168
Features............................................................................................................................. 169
Functional Descriptions ..................................................................................................... 169
External Interrupt Pin Selection .................................................................................................... 169
Alternate Function......................................................................................................................... 170
Lock Mechanism .......................................................................................................................... 170
Register Map ..................................................................................................................... 170
Register Descriptions......................................................................................................... 171

Rev. 1.00 6 of 576 January 28, 2022
32-Bit Arm®Cortex®-M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
Table of Contents
EXTI Source Selection Register 0 – ESSR0 ................................................................................ 171
EXTI Source Selection Register 1 – ESSR1 ................................................................................ 172
GPIO Port x Conguration Low Register – GPxCFGLR, x = A, B, C, D ....................................... 173
GPIO Port x Conguration High Register – GPxCFGHR, x = A, B, C, D...................................... 174
10 Nested Vectored Interrupt Controller (NVIC).................................................. 175
Introduction ........................................................................................................................ 175
Features............................................................................................................................. 176
Functional Descriptions ..................................................................................................... 177
SysTick Calibration ....................................................................................................................... 177
Register Map ..................................................................................................................... 177
11 External Interrupt/Event Controller (EXTI)......................................................... 178
Introduction ........................................................................................................................ 178
Features............................................................................................................................. 178
Functional Descriptions ..................................................................................................... 179
Wakeup Event Management......................................................................................................... 179
External Interrupt/Event Line Mapping ......................................................................................... 179
Interrupt and Debounce ................................................................................................................ 180
Register Map ..................................................................................................................... 181
Register Descriptions......................................................................................................... 182
EXTI Interrupt n Conguration Register – EXTICFGRn, n = 0 ~ 15 ............................................. 182
EXTI Interrupt Control Register – EXTICR ................................................................................... 183
EXTI Interrupt Edge Flag Register – EXTIEDGEFLGR................................................................ 184
EXTI Interrupt Edge Status Register – EXTIEDGESR ................................................................. 185
EXTI Interrupt Software Set Command Register – EXTISSCR.................................................... 185
EXTI Interrupt Wakeup Control Register – EXTIWAKUPCR ........................................................ 186
EXTI Interrupt Wakeup Polarity Register – EXTIWAKUPPOLR ................................................... 187
EXTI Interrupt Wakeup Flag Register – EXTIWAKUPFLG........................................................... 187
12 Analog to Digital Converter (ADC) .................................................................. 188
Introduction ........................................................................................................................ 188
Features............................................................................................................................. 189
Functional Descriptions ..................................................................................................... 190
ADC Clock Setup.......................................................................................................................... 190
Channel Selection......................................................................................................................... 190
Conversion Mode.......................................................................................................................... 190
Start Conversion on External Event.............................................................................................. 193
Sampling Time Setting.................................................................................................................. 194
Data Format.................................................................................................................................. 194
Analog Watchdog.......................................................................................................................... 194
Interrupts....................................................................................................................................... 195
PDMA Request (HT32F54243/HT32F54253 only) ....................................................................... 195
Voltage Reference Generator ....................................................................................................... 195

Rev. 1.00 7 of 576 January 28, 2022
32-Bit Arm®Cortex®-M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
Table of Contents Table of Contents
VDDA Voltage Monitor ..................................................................................................................... 196
Register Map ..................................................................................................................... 196
Register Descriptions......................................................................................................... 197
ADC Conversion Control Register – ADCCR ............................................................................... 197
ADC Conversion List Register 0 – ADCLST0............................................................................... 199
ADC Conversion List Register 1 – ADCLST1............................................................................... 200
ADC Input Sampling Time Register – ADCSTR ........................................................................... 201
ADC Conversion Data Register y – ADCDRy, y = 0 ~ 7 ............................................................... 202
ADC Trigger Control Register – ADCTCR .................................................................................... 203
ADC Trigger Source Register – ADCTSR..................................................................................... 204
ADC Watchdog Control Register – ADCWCR .............................................................................. 205
ADC Watchdog Threshold Register – ADCTR.............................................................................. 206
ADC Interrupt Enable Register – ADCIER.................................................................................... 207
ADC Interrupt Raw Status Register – ADCIRAW ......................................................................... 208
ADC Interrupt Status Register – ADCISR..................................................................................... 209
ADC Interrupt Clear Register – ADCICLR .................................................................................... 210
ADC DMA Request Register – ADCDMAR....................................................................................211
Voltage Reference Control Register – VREFCR .......................................................................... 212
Voltage Reference Value Register – VREFVALR ......................................................................... 213
13 Comparator (CMP) (HT32F54243/HT32F54253 only) ..................................... 214
Introduction ........................................................................................................................ 214
Features............................................................................................................................. 214
Functional Descriptions ..................................................................................................... 215
Comparator Inputs and Output ..................................................................................................... 215
Comparator Voltage Reference .................................................................................................... 215
Interrupts and Wakeup.................................................................................................................. 216
Power Mode and Hysteresis......................................................................................................... 217
Comparator Write-Protected Mechanism ..................................................................................... 217
Register Map ..................................................................................................................... 217
Register Descriptions......................................................................................................... 218
Comparator Control Register n – CMPCRn, n = 0 or 1 ................................................................ 218
Comparator Voltage Reference Value Register n – CVRVALRn, n = 0 or 1................................. 220
Comparator Interrupt Enable Register n – CMPIERn, n = 0 or 1 ................................................. 221
Comparator Transition Flag Register n – CMPTFRn, n = 0 or 1 .................................................. 222
14 General-Purpose Timer (GPTM) ...................................................................... 223
Introduction ........................................................................................................................ 223
Features............................................................................................................................. 224
Functional Descriptions ..................................................................................................... 224
Counter Mode ............................................................................................................................... 224
Clock Controller ............................................................................................................................ 226
Trigger Controller.......................................................................................................................... 228
Slave Controller ............................................................................................................................ 229

Rev. 1.00 8 of 576 January 28, 2022
32-Bit Arm®Cortex®-M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
Table of Contents
Master Controller .......................................................................................................................... 231
Channel Controller........................................................................................................................ 232
Input Stage ................................................................................................................................... 234
Quadrature Decoder ..................................................................................................................... 236
Output Stage................................................................................................................................. 237
Update Management .................................................................................................................... 241
Single Pulse Mode........................................................................................................................ 242
Asymmetric PWM Mode ............................................................................................................... 244
Timer Interconnection ................................................................................................................... 244
Trigger Peripherals Start............................................................................................................... 247
PDMA Request (HT32F54243/HT32F54253 only) ....................................................................... 247
Register Map ..................................................................................................................... 248
Register Descriptions......................................................................................................... 249
Timer Counter Conguration Register – CNTCFR ....................................................................... 249
Timer Mode Conguration Register – MDCFR............................................................................. 250
Timer Trigger Conguration Register – TRCFR............................................................................ 253
Timer Control Register – CTR ...................................................................................................... 254
Channel 0 Input Conguration Register – CH0ICFR.................................................................... 255
Channel 1 Input Conguration Register – CH1ICFR.................................................................... 256
Channel 2 Input Conguration Register – CH2ICFR.................................................................... 258
Channel 3 Input Conguration Register – CH3ICFR.................................................................... 259
Channel 0 Output Conguration Register – CH0OCFR ............................................................... 261
Channel 1 Output Conguration Register – CH1OCFR ............................................................... 263
Channel 2 Output Conguration Register – CH2OCFR ............................................................... 265
Channel 3 Output Conguration Register – CH3OCFR ............................................................... 267
Channel Control Register – CHCTR............................................................................................. 269
Channel Polarity Conguration Register – CHPOLR.................................................................... 270
Timer PDMA/Interrupt Control Register – DICTR......................................................................... 271
Timer Event Generator Register – EVGR..................................................................................... 272
Timer Interrupt Status Register – INTSR...................................................................................... 274
Timer Counter Register – CNTR................................................................................................... 276
Timer Prescaler Register – PSCR ................................................................................................ 277
Timer Counter-Reload Register – CRR ........................................................................................ 278
Channel 0 Capture/Compare Register – CH0CCR ...................................................................... 279
Channel 1 Capture/Compare Register – CH1CCR ...................................................................... 280
Channel 2 Capture/Compare Register – CH2CCR ...................................................................... 281
Channel 3 Capture/Compare Register – CH3CCR ...................................................................... 282
Channel 0 Asymmetric Compare Register – CH0ACR................................................................. 283
Channel 1 Asymmetric Compare Register – CH1ACR................................................................. 283
Channel 2 Asymmetric Compare Register – CH2ACR................................................................. 284
Channel 3 Asymmetric Compare Register – CH3ACR................................................................. 284
15 Motor Control Timer (MCTM) ........................................................................... 285
Introduction ........................................................................................................................ 285
Features............................................................................................................................. 286

Rev. 1.00 9 of 576 January 28, 2022
32-Bit Arm®Cortex®-M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
Table of Contents Table of Contents
Functional Descriptions ..................................................................................................... 287
Counter Mode ............................................................................................................................... 287
Clock Controller ............................................................................................................................ 291
Trigger Controller.......................................................................................................................... 292
Slave Controller ............................................................................................................................ 293
Master Controller .......................................................................................................................... 295
Channel Controller........................................................................................................................ 296
Input Stage ................................................................................................................................... 299
Output Stage................................................................................................................................. 301
Update Management .................................................................................................................... 312
Single Pulse Mode........................................................................................................................ 314
Asymmetric PWM Mode ............................................................................................................... 316
Timer Interconnection ................................................................................................................... 317
Trigger Peripheral Start................................................................................................................. 321
Lock Level Table ........................................................................................................................... 321
PDMA Request (HT32F54243/HT32F54253 only) ....................................................................... 322
Register Map ..................................................................................................................... 323
Register Descriptions......................................................................................................... 324
Timer Counter Conguration Register – CNTCFR ....................................................................... 324
Timer Mode Conguration Register – MDCFR............................................................................. 325
Timer Trigger Conguration Register – TRCFR............................................................................ 328
Timer Control Register – CTR ...................................................................................................... 329
Channel 0 Input Conguration Register – CH0ICFR.................................................................... 330
Channel 1 Input Conguration Register – CH1ICFR.................................................................... 332
Channel 2 Input Conguration Register – CH2ICFR.................................................................... 334
Channel 3 Input Conguration Register – CH3ICFR.................................................................... 336
Channel 0 Output Conguration Register – CH0OCFR ............................................................... 338
Channel 1 Output Conguration Register – CH1OCFR ............................................................... 340
Channel 2 Output Conguration Register – CH2OCFR ............................................................... 342
Channel 3 Output Conguration Register – CH3OCFR ............................................................... 344
Channel Control Register – CHCTR............................................................................................. 346
Channel Polarity Conguration Register – CHPOLR.................................................................... 348
Channel Break Conguration Register – CHBRKCFR ................................................................. 349
Channel Break Control Register – CHBRKCTR ........................................................................... 350
Timer PDMA/Interrupt Control Register – DICTR......................................................................... 352
Timer Event Generator Register – EVGR..................................................................................... 354
Timer Interrupt Status Register – INTSR...................................................................................... 356
Timer Counter Register – CNTR................................................................................................... 358
Timer Prescaler Register – PSCR ................................................................................................ 359
Timer Counter-Reload Register – CRR ........................................................................................ 360
Timer Repetition Register – REPR ............................................................................................... 360
Channel 0 Capture/Compare Register – CH0CCR ...................................................................... 361
Channel 1 Capture/Compare Register – CH1CCR ...................................................................... 361
Channel 2 Capture/Compare Register – CH2CCR ...................................................................... 362
Channel 3 Capture/Compare Register – CH3CCR ...................................................................... 363

Rev. 1.00 10 of 576 January 28, 2022
32-Bit Arm®Cortex®-M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
Table of Contents
Channel 0 Asymmetric Compare Register – CH0ACR................................................................. 364
Channel 1 Asymmetric Compare Register – CH1ACR................................................................. 364
Channel 2 Asymmetric Compare Register – CH2ACR................................................................. 365
Channel 3 Asymmetric Compare Register – CH3ACR................................................................. 365
16 Single-Channel Timer (SCTM) ......................................................................... 366
Introduction ........................................................................................................................ 366
Features............................................................................................................................. 367
Functional Descriptions ..................................................................................................... 367
Counter Mode ............................................................................................................................... 367
Clock Controller ............................................................................................................................ 368
Trigger Controller.......................................................................................................................... 369
Slave Controller ............................................................................................................................ 370
Channel Controller........................................................................................................................ 372
Input Stage ................................................................................................................................... 374
Output Stage................................................................................................................................. 375
Update Management .................................................................................................................... 377
Register Map ..................................................................................................................... 378
Register Descriptions......................................................................................................... 379
Timer Counter Conguration Register – CNTCFR ....................................................................... 379
Timer Mode Conguration Register – MDCFR............................................................................. 380
Timer Trigger Conguration Register – TRCFR............................................................................ 381
Timer Control Register – CTR ...................................................................................................... 382
Channel Input Conguration Register – CHICFR......................................................................... 383
Channel Output Conguration Register – CHOCFR .................................................................... 385
Channel Control Register – CHCTR............................................................................................. 386
Channel Polarity Conguration Register – CHPOLR.................................................................... 387
Timer Interrupt Control Register – DICTR .................................................................................... 388
Timer Event Generator Register – EVGR..................................................................................... 389
Timer Interrupt Status Register – INTSR...................................................................................... 390
Timer Counter Register – CNTR................................................................................................... 391
Timer Prescaler Register – PSCR ................................................................................................ 391
Timer Counter-Reload Register – CRR ........................................................................................ 392
Channel Capture/Compare Register – CHCCR ........................................................................... 393
17 Basic Function Timer (BFTM).......................................................................... 394
Introduction ........................................................................................................................ 394
Features............................................................................................................................. 394
Functional Description ....................................................................................................... 395
Repetitive Mode............................................................................................................................ 395
One Shot Mode............................................................................................................................. 396
Trigger ADC Start ......................................................................................................................... 396
Register Map ..................................................................................................................... 397
Register Descriptions......................................................................................................... 397

Rev. 1.00 11 of 576 January 28, 2022
32-Bit Arm®Cortex®-M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
Table of Contents Table of Contents
BFTM Control Register – BFTMCR .............................................................................................. 397
BFTM Status Register – BFTMSR................................................................................................ 398
BFTM Counter Value Register – BFTMCNTR .............................................................................. 399
BFTM Compare Value Register – BFTMCMPR ........................................................................... 399
18 Real Time Clock (RTC) ..................................................................................... 400
Introduction ........................................................................................................................ 400
Features............................................................................................................................. 400
Functional Descriptions ..................................................................................................... 401
RTC Related Register Reset ........................................................................................................ 401
Reading RTC Register.................................................................................................................. 401
Low Speed Clock Conguration ................................................................................................... 401
RTC Counter Operation................................................................................................................ 402
Interrupt and Wakeup Control....................................................................................................... 402
RTCOUT Output Pin Conguration............................................................................................... 402
Register Map ..................................................................................................................... 404
Register Descriptions......................................................................................................... 404
RTC Counter Register – RTCCNT................................................................................................ 404
RTC Compare Register – RTCCMP............................................................................................. 405
RTC Control Register – RTCCR................................................................................................... 406
RTC Status Register – RTCSR..................................................................................................... 408
RTC Interrupt and Wakeup Enable Register – RTCIWEN............................................................ 409
19 Watchdog Timer (WDT) .................................................................................... 410
Introduction ........................................................................................................................ 410
Features............................................................................................................................. 411
Functional Description ....................................................................................................... 411
Register Map ..................................................................................................................... 413
Register Descriptions......................................................................................................... 413
Watchdog Timer Control Register – WDTCR ............................................................................... 413
Watchdog Timer Mode Register 0 – WDTMR0............................................................................. 414
Watchdog Timer Mode Register 1 – WDTMR1............................................................................. 415
Watchdog Timer Status Register – WDTSR ................................................................................. 416
Watchdog Timer Protection Register – WDTPR ........................................................................... 417
Watchdog Timer Clock Selection Register – WDTCSR................................................................ 418
20 Inter-Integrated Circuit (I2C)............................................................................. 419
Introduction ........................................................................................................................ 419
Features............................................................................................................................. 420
Functional Descriptions ..................................................................................................... 420
Two-Wire Serial Interface ............................................................................................................. 420
START and STOP Conditions....................................................................................................... 420
Data Validity.................................................................................................................................. 421
Addressing Format ....................................................................................................................... 421

Rev. 1.00 12 of 576 January 28, 2022
32-Bit Arm®Cortex®-M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
Table of Contents
Data Transfer and Acknowledge................................................................................................... 423
Clock Synchronization .................................................................................................................. 423
Arbitration ..................................................................................................................................... 424
General Call Addressing ............................................................................................................... 424
Bus Error....................................................................................................................................... 424
Address Mask Enable................................................................................................................... 425
Address Snoop ............................................................................................................................. 425
Operation Mode ............................................................................................................................ 425
Conditions of Holding SCL Line.................................................................................................... 429
I2C Timeout Function .................................................................................................................... 430
PDMA Interface (HT32F54243/HT32F54253 only)....................................................................... 430
Register Map ..................................................................................................................... 431
Register Descriptions......................................................................................................... 431
I2C Control Register – I2CCR ....................................................................................................... 431
I2C Interrupt Enable Register – I2CIER ........................................................................................ 433
I2C Address Register – I2CADDR................................................................................................. 434
I2C Status Register – I2CSR......................................................................................................... 435
I2C SCL High Period Generation Register – I2CSHPGR.............................................................. 438
I2C SCL Low Period Generation Register – I2CSLPGR ............................................................... 439
I2C Data Register – I2CDR ........................................................................................................... 440
I2C Target Register – I2CTAR ....................................................................................................... 441
I2C Address Mask Register – I2CADDMR .................................................................................... 442
I2C Address Snoop Register – I2CADDSR................................................................................... 443
I2C Timeout Register – I2CTOUT.................................................................................................. 444
21 Serial Peripheral Interface (SPI) ...................................................................... 445
Introduction ........................................................................................................................ 445
Features............................................................................................................................. 446
Functional Descriptions ..................................................................................................... 446
Master Mode................................................................................................................................. 446
Slave Mode................................................................................................................................... 446
SPI Serial Frame Format .............................................................................................................. 447
SPI Dual Mode.............................................................................................................................. 451
Status Flags.................................................................................................................................. 453
PDMA Interface (HT32F54243/HT32F54253 only)....................................................................... 456
Register Map ..................................................................................................................... 456
Register Descriptions......................................................................................................... 457
SPI Control Register 0 – SPICR0 ................................................................................................. 457
SPI Control Register 1 – SPICR1 ................................................................................................. 459
SPI Interrupt Enable Register – SPIIER ....................................................................................... 461
SPI Clock Prescaler Register – SPICPR ...................................................................................... 462
SPI Data Register – SPIDR .......................................................................................................... 463
SPI Status Register – SPISR........................................................................................................ 464
SPI FIFO Control Register – SPIFCR........................................................................................... 465

Rev. 1.00 13 of 576 January 28, 2022
32-Bit Arm®Cortex®-M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
Table of Contents Table of Contents
SPI FIFO Status Register – SPIFSR ............................................................................................ 466
SPI FIFO Time Out Counter Register – SPIFTOCR..................................................................... 467
22 Universal Synchronous Asynchronous Receiver Transmitter (USART) ..... 468
Introduction ........................................................................................................................ 468
Features............................................................................................................................. 469
Functional Descriptions ..................................................................................................... 469
Serial Data Format........................................................................................................................ 469
Baud Rate Generation .................................................................................................................. 470
Hardware Flow Control ................................................................................................................. 472
IrDA............................................................................................................................................... 473
RS485 Mode................................................................................................................................. 475
Synchronous Master Mode........................................................................................................... 477
Interrupts and Status .................................................................................................................... 479
PDMA Interface (HT32F54243/HT32F54253 only)....................................................................... 479
Register Map ..................................................................................................................... 479
Register Descriptions......................................................................................................... 480
USART Data Register – USRDR.................................................................................................. 480
USART Control Register – USRCR.............................................................................................. 481
USART FIFO Control Register – USRFCR................................................................................... 483
USART Interrupt Enable Register – USRIER ............................................................................... 484
USART Status & Interrupt Flag Register – USRSIFR................................................................... 486
USART Timing Parameter Register – USRTPR ........................................................................... 488
USART IrDA Control Register – IrDACR ...................................................................................... 489
USART RS485 Control Register – RS485CR............................................................................... 490
USART Synchronous Control Register – SYNCR ........................................................................ 491
USART Divider Latch Register – USRDLR................................................................................... 492
USART Test Register – USRTSTR............................................................................................... 493
23 Universal Asynchronous Receiver Transmitter (UART)................................ 494
Introduction ........................................................................................................................ 494
Features............................................................................................................................. 495
Functional Descriptions ..................................................................................................... 495
Serial Data Format........................................................................................................................ 495
Baud Rate Generation .................................................................................................................. 496
Interrupts and Status .................................................................................................................... 497
PDMA Interface (HT32F54243/HT32F54253 only)....................................................................... 498
Register Map ..................................................................................................................... 498
Register Descriptions......................................................................................................... 499
UART Data Register – URDR....................................................................................................... 499
UART Control Register – URCR................................................................................................... 500
UART Interrupt Enable Register – URIER.................................................................................... 501
UART Status & Interrupt Flag Register – URSIFR ....................................................................... 503
UART Divider Latch Register – URDLR ....................................................................................... 504

Rev. 1.00 14 of 576 January 28, 2022
32-Bit Arm®Cortex®-M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
Table of Contents
UART Test Register – URTSTR.................................................................................................... 505
24 Peripheral Direct Memory Access (PDMA)..................................................... 506
Introduction ........................................................................................................................ 506
Features............................................................................................................................. 506
Functional Description ....................................................................................................... 507
AHB Master .................................................................................................................................. 507
PDMA Channel ............................................................................................................................. 507
PDMA Request Mapping .............................................................................................................. 507
Channel Transfer .......................................................................................................................... 508
Channel Priority ............................................................................................................................ 508
Transfer Request .......................................................................................................................... 509
Address Mode............................................................................................................................... 509
Auto-Reload.................................................................................................................................. 510
Transfer Interrupt .......................................................................................................................... 510
Register Map ..................................................................................................................... 511
Register Descriptions......................................................................................................... 512
PDMA Channel n Control Register – PDMACHnCR (n = 0 ~ 5)................................................... 512
PDMA Channel n Source Address Register – PDMACHnSADR (n = 0 ~ 5) ................................ 514
PDMA Channel n Destination Address Register – PDMACHnDADR (n = 0 ~ 5) ......................... 515
PDMA Channel n Transfer Size Register – PDMACHnTSR (n = 0 ~ 5) ....................................... 516
PDMA Channel n Current Transfer Size Register – PDMACHnCTSR (n = 0 ~ 5)........................ 517
PDMA Interrupt Status Register – PDMAISR ............................................................................... 518
PDMA Interrupt Status Clear Register – PDMAISCR................................................................... 519
PDMA Interrupt Enable Register – PDMAIER .............................................................................. 520
25 Divider (DIV) ...................................................................................................... 522
Introduction ........................................................................................................................ 522
Features............................................................................................................................. 522
Functional Descriptions ..................................................................................................... 522
Register Map ..................................................................................................................... 523
Register Descriptions......................................................................................................... 523
Divider Control Register – CR ...................................................................................................... 523
Dividend Data Register – DDR ..................................................................................................... 524
Divisor Data Register – DSR ........................................................................................................ 524
Quotient Data Register – QTR...................................................................................................... 525
Remainder Data Register – RMR ................................................................................................. 525
26 Cyclic Redundancy Check (CRC).................................................................... 526
Introduction ........................................................................................................................ 526
Features............................................................................................................................. 526
Functional Descriptions ..................................................................................................... 527
CRC Computation......................................................................................................................... 527
Byte and Bit Reversal for CRC Computation................................................................................ 527

Rev. 1.00 15 of 576 January 28, 2022
32-Bit Arm®Cortex®-M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
Table of Contents Table of Contents
CRC with PDMA ........................................................................................................................... 528
Register Map ..................................................................................................................... 528
Register Descriptions......................................................................................................... 528
CRC Control Register – CRCCR .................................................................................................. 528
CRC Seed Register – CRCSD ..................................................................................................... 529
CRC Checksum Register – CRCCSR .......................................................................................... 530
CRC Data Register – CRCDR ...................................................................................................... 530
27 LED Controller (LEDC) ..................................................................................... 531
Introduction ........................................................................................................................ 531
Features............................................................................................................................. 532
Functional Description ....................................................................................................... 532
LEDC Basic Setting ...................................................................................................................... 532
LEDC Clock Source Selection ...................................................................................................... 532
LEDC Operational Description...................................................................................................... 532
LEDC Frame Interrupt .................................................................................................................. 537
LEDC Data Update Method .......................................................................................................... 538
Frame Rate Calculation ................................................................................................................ 538
Register Map ..................................................................................................................... 539
Register Descriptions......................................................................................................... 540
LED Control Register – LEDCR.................................................................................................... 540
LED COM Enable Register – LEDCER ........................................................................................ 541
LED Polarity Control Register – LEDPCR .................................................................................... 542
LED Interrupt Enable Register – LEDIER..................................................................................... 543
LED Status Register – LEDSR ..................................................................................................... 544
LED Dead Time Control Register – LEDDTCR ............................................................................ 545
LED Data Register n – LEDDRn (n = 0 ~11) ............................................................................... 546
28 Touch Key.......................................................................................................... 547
Introduction ........................................................................................................................ 547
Features............................................................................................................................. 547
Function Description .......................................................................................................... 547
Manual Mode ................................................................................................................................ 548
Auto Scan Mode ........................................................................................................................... 549
Periodic Auto Scan Mode ............................................................................................................. 549
Touch Key Interrupts.......................................................................................................... 550
Touch Key Scan Operation Flowchart .......................................................................................... 551
Register Map ..................................................................................................................... 554
Register Descriptions......................................................................................................... 555
Touch Key Control Register – TKCR ............................................................................................ 555
Touch Key Counter Register – TKCNTR ...................................................................................... 558
Touch Key Time Slot Counter Reload Register – TKTSCRR ....................................................... 559
Touch Key Interrupt Enable Register – TKIER ............................................................................. 560

Rev. 1.00 16 of 576 January 28, 2022
32-Bit Arm®Cortex®-M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
Table of Contents
Touch Key Status Register – TKSR.............................................................................................. 561
Touch Key Module n Control Register – TKMnCR ....................................................................... 563
TKMn Key Conguration Register – TKMnKCFGR...................................................................... 565
Touch Key Module n Status Register – TKMnSR (n = 0 ~ 3) ....................................................... 567
Touch Key Module n Reference Oscillator Capacitor Register – TKMnROCPR .......................... 568
Touch Key Module n Key 3 Capacitor Register – TKMnK3CPR................................................... 569
Touch Key Module n Key 2 Capacitor Register – TKMnK2CPR................................................... 569
Touch Key Module n Key 1 Capacitor Register – TKMnK1CPR................................................... 570
Touch Key Module n Key 0 Capacitor Register – TKMnK0CPR................................................... 570
Touch Key Module n C/F Counter Register – TKMnCFCNTR...................................................... 571
Touch Key Module n Key 3 Counter Register – TKMnK3CNTR................................................... 572
Touch Key Module n Key 2 Counter Register – TKMnK2CNTR................................................... 572
Touch Key Module n Key 1 Counter Register – TKMnK1CNTR................................................... 573
Touch Key Module n Key 0 Counter Register – TKMnK0CNTR................................................... 573
Touch Key Module n Key 3 Threshold Register – TKMnK3THR .................................................. 574
Touch Key Module n Key 2 Threshold Register – TKMnK2THR .................................................. 574
Touch Key Module n Key 1 Threshold Register – TKMnK1THR .................................................. 575
Touch Key Module n Key 0 Threshold Register – TKMnK0THR .................................................. 575

Rev. 1.00 17 of 576 January 28, 2022
32-Bit Arm®Cortex®-M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
Table of Contents List of Tables
List of Tables
Table 1. Features and Peripheral List ..................................................................................................... 30
Table 2. Document Conventions............................................................................................................. 33
Table 3. HT32F54231/HT32F54241 Register Map................................................................................. 39
Table 4. HT32F54243/HT32F54253 Register Map................................................................................. 40
Table 5. Flash Memory and Option Byte................................................................................................. 45
Table 6. Relationship between Wait State Cycle and HCLK................................................................... 45
Table 7. Booting Modes .......................................................................................................................... 46
Table 8. Option Byte Memory Map ......................................................................................................... 50
Table 9. Access Permission of Protected Main Flash Page.................................................................... 51
Table 10. Access Permission When Security Protection is Enabled....................................................... 52
Table 11. FMC Register Map .................................................................................................................. 53
Table 12. Operation Mode Denitions..................................................................................................... 72
Table 13. Enter/Exit Power Saving Modes.............................................................................................. 73
Table 14. Power Status after System Reset ........................................................................................... 73
Table 15. PWRCU Register Map ............................................................................................................ 74
Table 16. Output Divider 2 Value Mapping.............................................................................................. 85
Table 17. Feedback Divider 2 Value Mapping......................................................................................... 86
Table 18. CKOUT Clock Source ............................................................................................................. 88
Table 19. CKCU Register Map ............................................................................................................... 89
Table 20. RSTCU Register Map ............................................................................................................116
Table 21. AFIO, GPIO and I/O Pad Control Signal True Table.............................................................. 125
Table 22. GPIO Register Map............................................................................................................... 126
Table 23. AFIO Selection for Peripheral Map Example......................................................................... 170
Table 24. AFIO Register Map................................................................................................................ 170
Table 25. Exception Types.................................................................................................................... 175
Table 26. NVIC Register Map ............................................................................................................... 177
Table 27. EXTI Register Map................................................................................................................ 181
Table 28. Data Format in ADCDR [15:0]............................................................................................... 194
Table 29. A/D Converter Register Map ................................................................................................. 196
Table 30. CMP Register Map................................................................................................................ 217
Table 31. Counting Direction and Encoding Signals............................................................................. 237
Table 32. Compare Match Output Setup .............................................................................................. 238
Table 33. GPTM Register Map ............................................................................................................. 248
Table 34. GPTM Internal Trigger Connection ....................................................................................... 253
Table 35. Compare Match Output Setup .............................................................................................. 302
Table 36. Output Control Bits for Complementary Output with a Break Event Occurrence...................311
Table 37. Lock Level Table.................................................................................................................... 321
Table 38. MCTM Register Map ............................................................................................................. 323
Table 39. MCTM Internal Trigger Connection ....................................................................................... 328

Rev. 1.00 18 of 576 January 28, 2022
32-Bit Arm®Cortex®-M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
List of Tables
Table 40. Compare Match Output Setup .............................................................................................. 375
Table 41. SCTM Register Map.............................................................................................................. 378
Table 42. BFTM Register Map .............................................................................................................. 397
Table 43. LSE Startup Mode Operating Current and Startup Time....................................................... 401
Table 44. RTCOUT Output Mode and Active Level Setting .................................................................. 403
Table 45. RTC Register Map................................................................................................................. 404
Table 46. Watchdog Timer Register Map.............................................................................................. 413
Table 47. Conditions of Holding SCL line.............................................................................................. 429
Table 48. I2C Register Map ................................................................................................................... 431
Table 49. I2C Clock Setting Example .................................................................................................... 439
Table 50. SPI Interface Format Setup................................................................................................... 447
Table 51. SPI Mode Fault Trigger Conditions ....................................................................................... 455
Table 52. SPI Master Mode SPI_SEL Pin Status.................................................................................. 455
Table 53. SPI Register Map .................................................................................................................. 456
Table 54. Baud Rate Deviation Error Calculation – CK_USART = 40 MHz.......................................... 471
Table 55. Baud Rate Deviation Error Calculation – CK_USART = 48 MHz.......................................... 471
Table 56. Baud Rate Deviation Error Calculation – CK_USART = 60 MHz.......................................... 471
Table 57. USART Register Map............................................................................................................ 479
Table 58. Baud Rate Deviation Error Calculation – CK_UART = 40 MHz ............................................ 496
Table 59. Baud Rate Deviation Error Calculation – CK_UART = 48 MHz ............................................ 497
Table 60. Baud Rate Deviation Error Calculation – CK_UART = 60 MHz ............................................ 497
Table 61. UART Register Map .............................................................................................................. 498
Table 62. PDMA Channel Assignments ................................................................................................ 508
Table 63. PDMA Address Modes .......................................................................................................... 509
Table 64. PDMA Register Map...............................................................................................................511
Table 65. DIV Register Map.................................................................................................................. 523
Table 66. CRC Register Map ................................................................................................................ 528
Table 67. LED Pixel Data and (SEGx, COMy) Relationship ................................................................. 538
Table 68. LEDC Register Map .............................................................................................................. 539
Table 69. Touch key module Register Map ........................................................................................... 554

Rev. 1.00 19 of 576 January 28, 2022
32-Bit Arm®Cortex®-M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
List of Tables List of Figures
List of Figures
Figure 1. HT32F54231/HT32F54241 Block Diagram ............................................................................. 31
Figure 2. HT32F54243/HT32F54253 Block Diagram ............................................................................. 32
Figure 3. Cortex®-M0+ Block Diagram.................................................................................................... 35
Figure 4. Bus Architecture ...................................................................................................................... 36
Figure 5. HT32F54231/HT32F54241 Memory Map................................................................................ 37
Figure 6. HT32F54243/HT32F54253 Memory Map................................................................................ 38
Figure 7. Flash Memory Controller Block Diagram................................................................................. 43
Figure 8. Flash Memory Map.................................................................................................................. 44
Figure 9. Vector Remapping ................................................................................................................... 46
Figure 10. Page Erase Operation Flowchart .......................................................................................... 47
Figure 11. Mass Erase Operation Flowchart........................................................................................... 48
Figure 12. Word Programming Operation Flowchart .............................................................................. 49
Figure 13. PWRCU Block Diagram......................................................................................................... 69
Figure 14. Power-On Reset / Power-Down Reset Waveform................................................................. 71
Figure 15. CKCU Block Diagram ............................................................................................................ 81
Figure 16. External Crystal, Ceramic and Resonators for HSE.............................................................. 82
Figure 17. HSI Auto Trimming Block Diagram ........................................................................................ 84
Figure 18. PLL Block Diagram ................................................................................................................ 85
Figure 19. External Crystal, Ceramic and Resonators for LSE .............................................................. 86
Figure 20. RSTCU Block Diagram.........................................................................................................115
Figure 21. Power-On Reset Sequence..................................................................................................116
Figure 22. GPIO Block Diagram ........................................................................................................... 123
Figure 23. AFIO/GPIO Control Signal................................................................................................... 125
Figure 24. AFIO Block Diagram ............................................................................................................ 168
Figure 25. EXTI Channel Input Selection ............................................................................................. 169
Figure 26. EXTI Block Diagram ............................................................................................................ 178
Figure 27. EXTI Wakeup Event Management ...................................................................................... 179
Figure 28. EXTI Wakeup Interrupt Service Routine Management........................................................ 180
Figure 29. EXTI Interrupt Debounce Function ...................................................................................... 180
Figure 30. ADC with VREF Block Diagram.............................................................................................. 188
Figure 31. One Shot Conversion Mode ................................................................................................ 191
Figure 32. Continuous Conversion Mode ............................................................................................. 191
Figure 33. Discontinuous Conversion Mode......................................................................................... 193
Figure 34. Voltage Reference Generator Block Diagram ..................................................................... 196
Figure 35. Comparator Block Diagram ................................................................................................. 214
Figure 36. Comparator Voltage Reference Block Diagram................................................................... 215
Figure 37. Comparator Interrupt Signals .............................................................................................. 216
Figure 38. Comparator Wakeup Signals............................................................................................... 216
Figure 39. GPTM Block Diagram.......................................................................................................... 223

Rev. 1.00 20 of 576 January 28, 2022
32-Bit Arm®Cortex®-M0+ MCU
HT32F54231/HT32F54241/HT32F54243/HT32F54253
List of Figures
Figure 40. Up-counting Example .......................................................................................................... 225
Figure 41. Down-counting Example...................................................................................................... 225
Figure 42. Center-aligned Counting Example....................................................................................... 226
Figure 43. GPTM Clock Source Selection ............................................................................................ 227
Figure 44. Trigger Controller Block ....................................................................................................... 228
Figure 45. Slave Controller Diagram .................................................................................................... 229
Figure 46. GPTM in Restart Mode........................................................................................................ 229
Figure 47. GPTM in Pause Mode ......................................................................................................... 230
Figure 48. GPTM in Trigger Mode ........................................................................................................ 230
Figure 49. Master GPTMn and Slave GPTMm/TMm Connection ........................................................ 231
Figure 50. MTO Selection..................................................................................................................... 231
Figure 51. Capture/Compare Block Diagram........................................................................................ 232
Figure 52. Input Capture Mode............................................................................................................. 233
Figure 53. PWM Pulse Width Measurement Example.......................................................................... 234
Figure 54. Channel 0 and Channel 1 Input Stages............................................................................... 234
Figure 55. Channel 2 and Channel 3 Input Stages............................................................................... 235
Figure 56. TI0 Digital Filter Diagram with N = 2.................................................................................... 235
Figure 57. Input Stage and Quadrature Decoder Block Diagram ......................................................... 236
Figure 58. Both TI0 and TI1 Quadrature Decoder Counting................................................................. 237
Figure 59. Output Stage Block Diagram ............................................................................................... 237
Figure 60. Toggle Mode Channel Output Reference Signal (CHxPRE = 0) ......................................... 238
Figure 61. Toggle Mode Channel Output Reference Signal (CHxPRE = 1) ......................................... 239
Figure 62. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode ............ 239
Figure 63. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode ....... 240
Figure 64. PWM Mode Channel Output Reference Signal and Counter in Centre-aligned Mode........ 240
Figure 65. Update Event Setting Diagram ............................................................................................ 241
Figure 66. Single Pulse Mode............................................................................................................... 242
Figure 67. Immediate Active Mode Minimum Delay ............................................................................. 243
Figure 68. Asymmetric PWM Mode versus Center-Aligned Counting Mode ........................................ 244
Figure 69. Pausing PWM0 Using the GPTM CH0OREF Signal ........................................................... 245
Figure 70. Triggering PWM0 with GPTM Update Event ....................................................................... 245
Figure 71. Trigger GPTM and PWM0 with the GPTM CH0 Input ......................................................... 246
Figure 72. GPTM PDMA Mapping Diagram.......................................................................................... 247
Figure 73. MCTM Block Diagram ......................................................................................................... 285
Figure 74. Up-Counting Example ......................................................................................................... 287
Figure 75. Down-Counting Example..................................................................................................... 288
Figure 76. Center-Aligned Counting Example ...................................................................................... 289
Figure 77. Update Event 1 Dependent Repetition Mechanism Example.............................................. 290
Figure 78. MCTM Clock Source Selection............................................................................................ 291
Figure 79. Trigger Controller Block ....................................................................................................... 292
Figure 80. Slave Controller Diagram .................................................................................................... 293