Toshiba TLCS-90 Series Product guide

TOSHIBA AMERICA, INC.

Notice to Potential TLCS-90* Customers:
This Databook contains a preliminary Data Sheet for Toshiba's new TLCS-90 Series 8-bit
Microcontrollers. Although the Data contained therein is generally believed to be current, it is
recommended that you contact you local Toshiba Sales Person or Office to obtain the latest
Specs prior to any actual System Design.
Thus you will be
ensured of having the latest Device Electrical Specs to incorporate into your
System Design Process.
* The TLCS-90 Series currently includes the following devices:
• TM P90C840 N
• TMP80C840F
• TMP90C841 N
• TMP90C841 N
• TMP90C840E
Future TLCS-90 Series Devices will be added to this expanding Family.

a-BIT
MICROCONTROLLER
TLCS 48,90
Additional Literature-Available:
Literature Description
• Microcomputer Products Summary
• 4-Bit Microcontroller
• B-Bit Microcontroller
• B-Bit Microprocessor
• 16-Bit Microprocessor'
• Speech Devices
• Micro Peripherals
Device Families
All CPU Products
TLCS-42. TLCS-4 7/470
TLCS-4B. TLCS-90
TLCS-ZBO. TLCS-85
TLCS-6BOOO
Speech Prod
ucts
Other Micro Peripherals
Plus Various Development System Manuals
November 1988

INDEX
PART 1 TLCS-48 Series
PART 2 TLCS-90 Series
APPENDIX
(TLCS-90)

PART 1
TLCS·48
LSI DEVICES

TOSHIBA
TLCS-48 LSI DEVICE CONTENTS
CONTENTS
TMP8()48A/TMP8035A, TMP8049A/TMP8039A ••••••••••••••••••••••••••••••• MCU48-
TMP8048A/TMP80C35A •••••••••••••••••••••••••••••••••••••••••.•••••••••••• 35
TMP80C49A/TMP80C39A ••••••••••••••••••••••••••••••••••••••••••••••••••••• 59
TMP80C50A/TMP80C40A •••••••••••••••••.•••.•••••••••••.••••••••••••••••••• 83
TMP8048PI/TMP8035PI
107
TMP8049PI-6/TMP8039PI-6 ••••••••.•••••••••••••••••••••••••••••••••••••••• 137
TMP8243P/TMP8243PI •••••••••••••••••••••••••••••.•••••••••••••••••••••••• 167
TJ:.-IP82C43P ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 176
MCU48-i

TOSHIBA
GENERAL DESCRIPTION
TMP 8048A/TMP 80 35A, TMP 8049A/TMP 80 39A
NMOS 8-BIT MICROCONTROLLER (TLCS-48)
TMP8048AP /TMP8035AP
TMP8049AP /TMP8039AP
TMP 804BAT /TMP 80 35 AT
TMP 8049AT /TMP 80 39AT
The TMP804BAP /TMP8049AP, from here on referred to as the TMP8048A except
in case of no need to specify each parts, is a single chip microcontroller
internal 8-bit parallel architecture.
The following basic architectural functions of a computer have been
included in a single chip; an 8-bit CPU, R&~ data memory, ROM program memory,
27 I/O lines and an 8-bit timer/event counter.
The TMP804BA is particularly efficient as a controller. It has extensive
bit handing capability as well as facilities for both binary and BCD arith-
metic.
The TMP 8035A/TMP 8039A is the equivalent of a TMP 8048A/TMP 8049A wi thout
ROM program memory on chip. By using this device with external EPROM or RAM,
software debugging becomes easy.
The TMP 8048AP /TMP B035AP, TMP 8049AP /TMP 8039AP are packaged in a standard
40 pin Dual Inline Plastic Package.
The TMP 8048AT /TMP 8035AT, TMP 8049AT /TMP 8039AT are packaged in the JEDEC
standard type 44pin PLCC (Plastic Leaded Chip Carrier).
FEATURES
· 1.36 us Instruction Cycle
• All instruction 1 or 2 cycles
• Over 90 instructions; 70% single byte
· Easy expandable memory and I/O
Parts Number
TMP8048A
TMP B049A
TMPB03SA
TMPB039A
Program Memory (ROM)
1 k Byte
2 k Byte
MCU48-1
• 27 I/O lines
· Interval Time/Event Counter
• Single level interrupt
• Single SV supply
Data Memory (RAM)
64 Byte
128 Byte
64 Byte
128 Byte

TOSHIBA
TMP 8048A/TMP 80 35A, TMP 8049A/TMP80 39A
PIN CONNECTIONS (Top View)
TO
XTALI
XTAL2
RESET
SS
INT
EA
RD
PSEN
WR
ALE
DBa
DBI
DB2
DB3
DB4
DBs
DB6
DB7
(OV)VSS
EA
RD- ;.:
PSEN
WR
NC
ALE
DBa
DBI
DB2
DB3
!t:
~
~..,
ru
~
~
Vee (+5V)
Tl
P27
P26
P2S
P24
P17
P16
PIS
P14
P13
P12
Pll
PIa
VDD(+SV)
PROG
P23
P22
P21
P
20
P24
P17
P16
PlS
Pl4
NC
PI3
P12
PlI
PIa
VDD
~Ln..cr-U)UO.-4N~~
COCOCOCOU'lZNNNNO
0000> 1l41l41l41l4c::
Il4
MCU48-2

TOSHIBA
TMP8048A/TMP8035A,TMP8049A/TMP8039A
PIN
NAMES AND PIN DESCRIPTION
VSS (Power Supply)
Circuit GND potential
VDD (Power Supply)
+5V during operation Low power standby pin for TMP8048A RAM
VCC (Main Power Supply)
+5V during operation
PROG (Output)
Output strobe for the TXP8243P I/O exapnder
PlO-P17 (Input/Output) Port 1
8-bit quasi-bidirectional port (Internal Pullup
P20-P27 (Input/Output) Port 2
50 kohm).
8-bit quasi~bidrectional port (Internal Pullup = 50 kohm).
P20-P23 Contain the four high order program counter bits during an
external program memory fetch and serve as a 4-bit I/O expander bus for
the TMP 8243P •
DBO-DB7 (Input/Output, 3 State)
True~idirectional port which can be written or read synchronously using
the RD, WR strobes. The port can also be statically latched. Contains
the 8 low order program counter bits during an external program mem~
fetch, and receives the addressed instruction under the control of PSEN.
Also contains the address and data during an external RAM data store
instruction, under control of ALE, RD and WR.
TO (Input/Output)
Input pin testable using the conditional transfer instructions JTO and
JNTO. TO can be designated as a clock output using ENTO CLK instruction.
Tl (Input)
Input pin testable using the JTl and JNTI instruction. Can be designated
the event counter input using the timer/STRT CNT instruction.
INT (Input)
External interrupt input. Initiates an interrupt if interrupt is
enabled. Interrupt is disabled after a reset. Also testable with
conditional jump instruction. (Active Low)
RD (Output)
Output strobe activated during a Bus read. Can be used to enable data
onto the Bus from an external device. Used as a Read Strobe to External
Data Memory (Active Low).
WR (Output)
Output strobe during a Bus write (Active Low). Used as a Write Strobe to
External Data Memory.
MCU48-3

TOSHIBA
BLOCK DIAGRAM
Oscillation
DBO- DB7
Accumulator
Bit Test
Control and Timing Circuit
XTAL
2
XTAL 1 mn rnT EA 55 ALE P'S"EN RD WR PROG
----
....
0
'"
........
O-\"I'l
en
~~
til."
i'
en\"l'l
::s
til nI
::I ::s
"1 )(
,...
~ "1
~~
~
n
til ~~
nI ~
::s ~O-
"1
0 ~
c
... nI C nI en nI
00 n
"1
o 00
~ o ~
"
....
~
"""1
en "1
....
=rill
C""1
C"::s
en
.-
"1
enS
nI til nI
~
en
nlO-
III ....
c:
en til
S
~
nI
,.,
::s ~
nI ....
en
~
., .,
0 ~
,.,
....
~
"1
0
.,
C nI > III 0
C"
""
n 0- ~
C"
nI
'"
I III en
MCU48-4
TMP 8048A/TMP 8035A, TMP 8049A/TMP 8039A
Note
Note
2
Mask ROM
1k X8 (80W)
2k X8 (8049'\)
(Program
Area)
6 RAM
'-----;.."".r I 64 X8 (804M)
128 X8 (8049,\)
Circuit
1)
2)
The lower order 4 bits of
port 2 output latch are
used also for input/out-
put operations with the
I/O expander.
The output latch of port
o is also used for
address output.

TOSHIBA
TMP 8048A/TMP 8035A, TM? 8049A/TMP 8039A
RESET (Input)
Active Low signal which is used to initialize the Processor. Also used
during Power down.
ALE (Outpu t)
Address Latch Enable. This signal occurs once during each cycle and is
useful as a clock output. The negative edge of ALE strobes address into
external data and program memory.
PSEN (Output)
Program Store Enable. This output Qccurs only during a fetch to external
program memory (Active Low).
SS (Input)
Single Step input can be used in conjunction with ALE to "single step"
processor through each instruction when 55 is low the CPU is placed into
a wait state after it has completed the instruction being excuted.
EA (Input)
External Access input which forces all program memory fetchs to reference
external memory. Useful for emulation and debug and essential for
testing and program verification. (Active High).
XTAL 1 (Input)
One side of crystal input for internal oscillator. Also input for
external source.
XTAL 2 (Input)
Other side of crystal input.
FUNCTIONAL DESCRIPTION
1. System Configuration
(1)
• The
following system
functions
of the TMP8048A are described
in detail.
0)
Program Memory
(6)
Stack
(Stack Pointer)
(2)
Data Memory
(7)
Flag 0,
Flag 1
(3)
I/O Port
(8)
Program Status Word (PSW)
(4)
Timer/Counter
(9)
Reset
(5)
Interrupt Control
Circuit
(10)
Oscillator Circuit
Program Memory
• The maximum memory that can be directly addressed by the TMP8048A is
4096 bytes. The first 1024 bytes from location 0 through 1023
(TMP8048A) or the first 2048 bytes from location 0 to 2047 (TMP8049A)
can be internal resident mask ROM. The rest of the 3072 bytes or the
2048 bytes of addressable memory are external to the chip. The
TMP8035A
and TMP8039A have has no internal resident memory; all memory
must be external.
MCU48-S

TOSHIBA
TMP8048A/TMP8035A,TMP8049A/TMP8039A
There are three locations in Program Memory of special importance.
• Location 0
Address
4095
2048
2047
Memo ry Bank 1
Memory Bank 0
Program Memory Area
Activating the Reset line of the processor causes the first instruction
to be fetched from Location O.
• Location 3
Activating the interrupt line of the processor (if interrupt enabled)
causes a jump to subroutine defined by address held in Location 3.
• Location 7
A
timer / counter
enabled) causes
Location 7.
interrupt resul ting from a timer/counter overflow
a jump to a subroutine defined by address held
(if
in
• Program address 0-2047 and 2048-4095 are called memory banks 0 and 1 respec-
tively switching of memory banks is achieved by changing the most
significant bit of the program counter (PC) during execution of an
uncoditional jump instruction or call instruction executed after using SEL
MBO or SEL MBI.
Reset operation automatically selects Bank O.
(2) Data Memory
• Resident Data Memory (volatile RAM) is organized as 64 words (TMP8048A)
or 128 words (TMP8049A) by 8-bits wide •
• The
first 8 locations (0 - 7) of the memory array are designed as
working registers and are directly addressable by several instructions.
By executing a Register Bank switch instruction (SEL RBI) locations 24
-
31 are designated as the working registers in palce of 0 - 7.
MCU48-6

TOSHIBA
TMP 8048A/TMP 8035A, TMP 8049A/TMP 8039A
Addre8S~------------~
121
Data Memory
32
31 -R-;;1~;;;'-Ba-;;kl-
24 RBI
23-----------
8 Level Stack
8
(16 byte)
1"R-;;i-;t~-; -B~;k-O-
o RBO
Internal Data Memory Area
RAM locations 8 - 23 serve a dual role in that they contain the program
counter stack which is a stack 2 bytes wide by 8 levels deep. These
locations store returning addresses from subroutines. If the level of
subroutine nesting is less than the permitted 8, you free up 2 bytes of
RAM for general use for every level of nesting not utilized.
• All 64 (TMP8048A) or 128 (TMP8049A) locations are indirectly
addressable through eitheF of two R&~ Pointer Registers which reside at
RO and R1 of the Register array.
The TMP8048A architecture allows extension of the Data Memory to 256
words.
(3) Input/Output Ports
• The TMP8048A has 27 I/O lines which can be used for either input or
output. These I/O I ines are grouped into 3 ports each having 8
bidirectional lines and 3 "test" inputs which can after program
sequences when tested by conditional jump instructions.
• Ports 1 and 2 are each 8-bits wide and have identical characteristics.
Data written to these ports is statically latched and remains unchanged
unt i 1 rewri t ten. As input ports these lines are non-lat ching, i. e •,
inputs must be present until read by an input instruction.
• All lines of Ports 1 and 2 are called quasi-bidirectional because of a
special output circuit structure (illustrated in Figure 1). Each line
is continuously pulled to a +SV level through a high impedance
res is t i ve devi ce (SOkohm) wh ich is suffi cient to provide t he source
current for a TTL high level yet can be pulled low by a standard TTL
gate thus allowing the same pin to be used for both input and output.
I n order to speed up the "0" to "1" trans i t ion a low impedance device
(5kohm) is swi t ched in momentari ly whenever a "1" is wr i tt en to 1 ine •
When "0" is written to line a low impedance device overecomes the
pullup and provides TTL current sinking capability.
MCU48-7

TOSHIBA
TMP 8048A/TMP 80 35A, TMP 8049A/TMP 80 39A
ANt, ORt
Internal ·Bus---1-..A--f 0 Q
D-Type
Flip-Flop
+SV +5V
CLK Q ~+----~
Write Puls~---+~--------------~
Inter Buffer
IN
SOkn
Fig.l Input/Output Circuit of Port 1, Port 2
SOkn I/O pins
Portl or 2
• Reset initializes all lines to a high impedance "1" state.
• When external data memory area is not addressed during execution of an
internal program, Port 0 (DBO - DB7) becomes a true bidirectional port
(bus) with associated input and output strobes. If bidirectional
feature not needed Bus can serve as either a statically latched output
port or a non-latched input port. However, I/O lines of this port
cannot be intermixed.
• As a static port data is written and latched using the OUTL instruction
and inputted using the INS instruction these two commands generate
pulses on the corresponding RD and WR strobe lines.
• As a bidirectional port the MOVX instructions are used to read and
write the port which generate the RD and ~ strobes.
• When not being written or read, the Bus lines are in a high impedance
sta te.
(4) Timer/Event Counter
• The 8-bit binary up counter can use either of the following frequency
inputs
(1) Internal clock (1/480 of asc frequency)
•••••••••••••• Timer mode
MCU48-8

TOSHIBA TMP 8048A/TMP 8035A, TMP8049A/TMP 8039A
XTAL/lS
(2) External input clock form Tl terminal
(minimum cycle time 3 x ALE cycle)
.........•.• Event Counter mode
The
counter is presettable and readable with two MOV instructions
wh i ch ti- ans fe r the con ten t of the ac cumula t or to the count er and vi ce
versa. The counter content is not affected by a Reset and is
initialized solely by the MOVT, A instruction. The counter is stopped
-by a Reset or STOP TCNT instruction and remains stopped until started
by STRT T instruction or as an event counter by a srRT CNT. One
started the counter will increment to its maximum count (FF) and
overflow to Zero continuing its count until stopped by a STOP TCNT
instruction or RESET.
The increment from maximum count to Zero (overflow) results in the
setting of an overflow flag and the generation of an interrupt request.
When interrupt acknowledged a subroutine call to Location 7 will be
initiated. Location 7 should store the starting address of the timer
or counter service routine. The state of the overflow flag is testable
with the conditional Jump (JTF). The flag is reset by excuting a JTF
or by RESET.
Figure 2 illustrates the concept of the timer circuit.
1/32
Pre-scaler
Cleared on Start Timer
STOP TCNT 0
8-Bi t Timer/
Counter
IT
JTF Instruction
Timer In te rrupt
Request Flip-Flop
r-------~Edge Detector
Read/Write Enable
INT
Titrer Int e rrupt Enab1e
Fig. 2 Concept of Timer Circuit
MCU48-9

TOSHIBA
TMP 8048A/TMP 80 35A, TMP 8049A/TMP 8039A
JTF
Instruction
S
Conditional Jump Logic
Timer
Flag F-F
>--+-_01 R
Re set ---:L~
Timer Overflow
--------~~s Q~----_01
Timer Interrupt
Execution------~~
Reset
INT pin
ALE
Last cycle
of Instruct
EN I
Instruction
Timer
Overflow
R F-F
N TCl:T 1 S ~ Q
Instruction ~
... ...
~~~
R~.s~
Reset----~~----------------~
Instruction
DIS TCNTl
Instruction
RETR
tion
r---~:;--...,External inter-
CLK rupt Recognized
Q
CLR
Execution of Inter-
rupt Call Instruction
Fig. 3 Concept of Interrupt Control Circuit
(5) Interrupt Control Circuit
• There are two distinct types of Interrupts in the TMP8048A.
(1) External Interrupt from the INT terminal
(2) Timer Interrupt caused by timer overflow
MCU48-l0