Holtek HT32F50231 User manual

Holtek 32-Bit Microcontroller with Arm®Cortex®-M0+
HT32F50231/HT32F50241
User Manual
Revision: V1.00 Date: July 31, 2018

Rev. 1.00 2 of 486 July 31, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F50231/HT32F50241
Table of Contents
Table of Contents
1 Introduction........................................................................................................... 21
Overview.............................................................................................................................. 21
Features............................................................................................................................... 22
Device Information............................................................................................................... 25
Block Diagram ..................................................................................................................... 26
2 Document Conventions ....................................................................................... 27
3 System Architecture............................................................................................. 28
Arm®Cortex®-M0+ Processor .............................................................................................. 28
Bus Architecture................................................................................................................... 29
Memory Organization .......................................................................................................... 30
Memory Map................................................................................................................................... 31
Embedded Flash Memory............................................................................................................... 33
Embedded SRAM Memory ............................................................................................................. 33
AHB Peripherals ............................................................................................................................. 33
APB Peripherals ............................................................................................................................. 33
4 Flash Memory Controller (FMC) .......................................................................... 34
Introduction .......................................................................................................................... 34
Features............................................................................................................................... 34
Functional Descriptions ....................................................................................................... 35
Flash Memory Map ......................................................................................................................... 35
Flash Memory Architecture ............................................................................................................. 36
Booting Conguration ..................................................................................................................... 37
Page Erase ..................................................................................................................................... 38
Mass Erase..................................................................................................................................... 39
Word Programming......................................................................................................................... 40
Option Byte Description .................................................................................................................. 41
Page Erase / Program Protection ................................................................................................... 42
Security Protection.......................................................................................................................... 43
Register Map ....................................................................................................................... 44
Register Descriptions........................................................................................................... 45
Flash Target Address Register – TADR .......................................................................................... 45
Flash Write Data Register – WRDR ............................................................................................... 46
Flash Operation Command Register – OCMR ............................................................................... 47
Flash Operation Control Register – OPCR..................................................................................... 48
Flash Operation Interrupt Enable Register – OIER ........................................................................ 49
Flash Operation Interrupt and Status Register – OISR .................................................................. 50
Flash Page Erase / Program Protection Status Register – PPSR.................................................. 52
Flash Security Protection Status Register – CPSR ........................................................................ 53
Flash Vector Mapping Control Register – VMCR ........................................................................... 54

Rev. 1.00 3 of 486 July 31, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F50231/HT32F50241
Table of Contents Table of Contents
Flash Manufacturer and Device ID Register – MDID...................................................................... 55
Flash Page Number Status Register – PNSR ................................................................................ 56
Flash Page Size Status Register – PSSR ...................................................................................... 57
Device ID Register – DIDR ............................................................................................................. 58
Custom ID Register n – CIDRn, n = 0 ~3 ....................................................................................... 59
5 Power Control Unit (PWRCU) .............................................................................. 60
Introduction .......................................................................................................................... 60
Features............................................................................................................................... 61
Functional Descriptions ....................................................................................................... 61
VDD Power Domain.......................................................................................................................... 61
1.5 V Power Domain....................................................................................................................... 63
Operation Modes ............................................................................................................................ 63
Register Map ....................................................................................................................... 64
Register Descriptions........................................................................................................... 65
Power Control Status Register – PWRSR ...................................................................................... 65
Power Control Register – PWRCR ................................................................................................. 66
Low Voltage / Brown Out Detect Control and Status Register – LVDCSR ..................................... 68
6 Clock Control Unit (CKCU) .................................................................................. 70
Introduction .......................................................................................................................... 70
Features............................................................................................................................... 72
Function Descriptions .......................................................................................................... 72
High Speed External Crystal Oscillator – HSE ............................................................................... 72
High Speed Internal RC Oscillator – HSI........................................................................................ 73
Auto Trimming of High Speed Internal RC Oscillator – HSI............................................................ 73
Low Speed External Crystal Oscillator – LSE................................................................................. 75
Low Speed Internal RC Oscillator – LSI ......................................................................................... 75
Clock Ready Flag ........................................................................................................................... 75
System Clock (CK_SYS) Selection ................................................................................................ 75
HSE Clock Monitor ......................................................................................................................... 76
Clock Output Capability .................................................................................................................. 76
Register Map ....................................................................................................................... 77
Register Descriptions........................................................................................................... 78
Global Clock Conguration Register – GCFGR.............................................................................. 78
Global Clock Control Register – GCCR.......................................................................................... 79
Global Clock Status Register – GCSR ........................................................................................... 81
Global Clock Interrupt Register – GCIR.......................................................................................... 82
AHB Conguration Register – AHBCFGR ...................................................................................... 83
AHB Clock Control Register – AHBCCR ........................................................................................ 84
APB Conguration Register – APBCFGR....................................................................................... 85
APB Clock Control Register 0 – APBCCR0.................................................................................... 86
APB Clock Control Register 1 – APBCCR1.................................................................................... 87
Clock Source Status Register – CKST ........................................................................................... 89

Rev. 1.00 4 of 486 July 31, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F50231/HT32F50241
Table of Contents
APB Peripheral Clock Selection Register 0 – APBPCSR0............................................................. 90
APB Peripheral Clock Selection Register 1 – APBPCSR1............................................................. 92
HSI Control Register – HSICR........................................................................................................ 93
HSI Auto Trimming Counter Register – HSIATCR .......................................................................... 94
APB Peripheral Clock Selection Register 2 – APBPCSR2............................................................. 95
MCU Debug Control Register – MCUDBGCR................................................................................ 96
7 Reset Control Unit (RSTCU) ................................................................................ 98
Introduction .......................................................................................................................... 98
Functional Descriptions ....................................................................................................... 99
Power On Reset ............................................................................................................................. 99
System Reset ................................................................................................................................. 99
AHB and APB Unit Reset................................................................................................................ 99
Register Map ..................................................................................................................... 100
Register Descriptions......................................................................................................... 100
Global Reset Status Register – GRSR ......................................................................................... 100
AHB Peripheral Reset Register – AHBPRSTR............................................................................. 101
APB Peripheral Reset Register 0 – APBPRSTR0 ........................................................................ 102
APB Peripheral Reset Register 1 – APBPRSTR1 ........................................................................ 103
8 General Purpose I/O (GPIO)............................................................................... 105
Introduction ........................................................................................................................ 105
Features............................................................................................................................. 106
Functional Descriptions ..................................................................................................... 106
Default GPIO Pin Conguration.................................................................................................... 106
General Purpose I/O – GPIO........................................................................................................ 106
GPIO Locking Mechanism ............................................................................................................ 108
Register Map ..................................................................................................................... 108
Register Descriptions......................................................................................................... 109
Port A Data Direction Control Register – PADIRCR ..................................................................... 109
Port A Input Function Enable Control Register – PAINER .............................................................110
Port A Pull-Up Selection Register – PAPUR ..................................................................................111
Port A Pull-Down Selection Register – PAPDR .............................................................................112
Port A Open-Drain Selection Register – PAODR...........................................................................113
Port A Output Drive Current Selection Register – PADRVR ..........................................................114
Port A Lock Register – PALOCKR .................................................................................................115
Port A Data Input Register – PADINR............................................................................................116
Port A Output Data Register – PADOUTR .....................................................................................116
Port A Output Set / Reset Control Register – PASRR ...................................................................117
Port A Output Reset Register – PARR...........................................................................................118
Port A Sink Current Enhanced Selection Register – PASCER ......................................................118
Port B Data Direction Control Register – PBDIRCR......................................................................119
Port B Input Function Enable Control Register – PBINER ........................................................... 120
Port B Pull-Up Selection Register – PBPUR ................................................................................ 121

Rev. 1.00 5 of 486 July 31, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F50231/HT32F50241
Table of Contents Table of Contents
Port B Pull-Down Selection Register – PBPDR............................................................................ 122
Port B Open-Drain Selection Register – PBODR ......................................................................... 123
Port B Output Drive Current Selection Register – PBDRVR ........................................................ 124
Port B Lock Register – PBLOCKR................................................................................................ 125
Port B Data Input Register – PBDINR .......................................................................................... 126
Port B Output Data Register – PBDOUTR ................................................................................... 126
Port B Output Set / Reset Control Register – PBSRR.................................................................. 127
Port B Output Reset Register – PBRR ......................................................................................... 128
Port B Sink Current Enhanced Selection Register – PBSCER..................................................... 128
Port C Data Direction Control Register – PCDIRCR .................................................................... 129
Port C Input Function Enable Control Register – PCINER ........................................................... 130
Port C Pull-Up Selection Register – PCPUR ................................................................................ 131
Port C Pull-Down Selection Register – PCPDR ........................................................................... 132
Port C Open Drain Selection Register – PCODR ......................................................................... 133
Port C Output Current Drive Selection Register – PCDRVR ........................................................ 134
Port C Lock Register – PCLOCKR ............................................................................................... 135
Port C Data Input Register – PCDINR.......................................................................................... 136
Port C Output Data Register – PCDOUTR ................................................................................... 136
Port C Output Set / Reset Control Register – PCSRR ................................................................. 137
Port C Output Reset Register – PCRR......................................................................................... 138
Port C Sink Current Enhanced Selection Register – PCSCER .................................................... 138
9 Alternate Function Input / Output Control Unit (AFIO).................................... 139
Introduction ........................................................................................................................ 139
Features............................................................................................................................. 140
Functional Descriptions ..................................................................................................... 140
External Interrupt Pin Selection .................................................................................................... 140
Alternate Function......................................................................................................................... 141
Lock Mechanism .......................................................................................................................... 141
Register Map ..................................................................................................................... 141
Register Descriptions......................................................................................................... 142
EXTI Source Selection Register 0 – ESSR0 ................................................................................ 142
EXTI Source Selection Register 1 – ESSR1 ................................................................................ 143
GPIO x Conguration Low Register – GPxCFGLR, x = A, B, C ................................................... 144
GPIO x Conguration High Register – GPxCFGHR, x = A, B, C.................................................. 145
10 Nested Vectored Interrupt Controller (NVIC).................................................. 146
Introduction ........................................................................................................................ 146
Features............................................................................................................................. 147
Function Descriptions ........................................................................................................ 148
SysTick Calibration ....................................................................................................................... 148
Register Map ..................................................................................................................... 148

Rev. 1.00 6 of 486 July 31, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F50231/HT32F50241
Table of Contents
11 External Interrupt / Event Controller (EXTI).................................................... 149
Introduction ........................................................................................................................ 149
Features............................................................................................................................. 149
Function Descriptions ........................................................................................................ 150
Wakeup Event Management......................................................................................................... 150
External Interrupt / Event Line Mapping ....................................................................................... 151
Interrupt and Debounce ................................................................................................................ 151
Register Map ..................................................................................................................... 152
Register Descriptions......................................................................................................... 153
EXTI Interrupt n Conguration Register – EXTICFGRn, n = 0 ~ 15 ............................................. 153
EXTI Interrupt Control Register – EXTICR ................................................................................... 154
EXTI Interrupt Edge Flag Register – EXTIEDGEFLGR................................................................ 155
EXTI Interrupt Edge Status Register – EXTIEDGESR ................................................................. 156
EXTI Interrupt Software Set Command Register – EXTISSCR.................................................... 157
EXTI Interrupt Wakeup Control Register – EXTIWAKUPCR ........................................................ 158
EXTI Interrupt Wakeup Polarity Register – EXTIWAKUPPOLR ................................................... 159
EXTI Interrupt Wakeup Flag Register – EXTIWAKUPFLG........................................................... 160
12 Analog to Digital Converter (ADC) .................................................................. 161
Introduction ........................................................................................................................ 161
Features............................................................................................................................. 162
Function Descriptions ........................................................................................................ 163
ADC Clock Setup.......................................................................................................................... 163
Channel Selection......................................................................................................................... 163
Conversion Mode.......................................................................................................................... 163
Start Conversion on External Event.............................................................................................. 166
Sampling Time Setting.................................................................................................................. 167
Data Format.................................................................................................................................. 167
Analog Watchdog.......................................................................................................................... 167
Interrupts....................................................................................................................................... 168
Register Map ..................................................................................................................... 169
Register Descriptions......................................................................................................... 170
ADC Conversion Control Register – ADCCR ............................................................................... 170
ADC Conversion List Register 0 – ADCLST0 .............................................................................. 172
ADC Conversion List Register 1 – ADCLST1............................................................................... 173
ADC Input Sampling Time Register – ADCSTR........................................................................... 174
ADC Conversion Data Register y – ADCDRy, y = 0 ~ 7 ............................................................... 175
ADC Trigger Control Register – ADCTCR .................................................................................... 176
ADC Trigger Source Register – ADCTSR..................................................................................... 177
ADC Watchdog Control Register – ADCWCR .............................................................................. 178
ADC Watchdog Threshold Register – ADCTR.............................................................................. 180
ADC Interrupt Enable Register – ADCIER................................................................................... 181
ADC Interrupt Raw Status Register – ADCIRAW ......................................................................... 182

Rev. 1.00 7 of 486 July 31, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F50231/HT32F50241
Table of Contents Table of Contents
ADC Interrupt Status Register – ADCISR..................................................................................... 183
ADC Interrupt Clear Register – ADCICLR .................................................................................... 184
13 General-Purpose Timer (GPTM) ...................................................................... 185
Introduction ........................................................................................................................ 185
Features............................................................................................................................. 185
Functional Descriptions ..................................................................................................... 186
Counter Mode ............................................................................................................................... 186
Clock Controller ............................................................................................................................ 189
Trigger Controller.......................................................................................................................... 190
Slave Controller ............................................................................................................................ 191
Master Controller .......................................................................................................................... 193
Channel Controller........................................................................................................................ 194
Input Stage ................................................................................................................................... 197
Quadrature Decoder ..................................................................................................................... 199
Output Stage................................................................................................................................. 201
Update Management .................................................................................................................... 205
Single Pulse Mode........................................................................................................................ 206
Asymmetric PWM Mode ............................................................................................................... 208
Timer Interconnection ................................................................................................................... 209
Trigger ADC Start.......................................................................................................................... 212
Register Map ..................................................................................................................... 212
Register Descriptions......................................................................................................... 213
Timer Counter Conguration Register – CNTCFR ....................................................................... 213
Timer Mode Conguration Register – MDCFR............................................................................. 214
Timer Trigger Conguration Register – TRCFR............................................................................ 217
Timer Counter Register – CTR ..................................................................................................... 218
Channel 0 Input Conguration Register – CH0ICFR .................................................................... 219
Channel 1 Input Conguration Register – CH1ICFR .................................................................... 220
Channel 2 Input Conguration Register – CH2ICFR .................................................................... 222
Channel 3 Input Conguration Register – CH3ICFR .................................................................... 223
Channel 0 Output Conguration Register – CH0OCFR ............................................................... 224
Channel 1 Output Conguration Register – CH1OCFR ............................................................... 226
Channel 2 Output Conguration Register – CH2OCFR ............................................................... 228
Channel 3 Output Conguration Register – CH3OCFR ............................................................... 230
Channel Control Register – CHCTR............................................................................................. 232
Channel Polarity Conguration Register – CHPOLR.................................................................... 233
Timer Interrupt Control Register – DICTR .................................................................................... 234
Timer Event Generator Register – EVGR..................................................................................... 235
Timer Interrupt Status Register – INTSR...................................................................................... 236
Timer Counter Register – CNTR................................................................................................... 238
Timer Prescaler Register – PSCR ................................................................................................ 239
Timer Counter Reload Register – CRR ........................................................................................ 240
Channel 0 Capture / Compare Register – CH0CCR .................................................................... 241

Rev. 1.00 8 of 486 July 31, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F50231/HT32F50241
Table of Contents
Channel 1 Capture / Compare Register – CH1CCR .................................................................... 242
Channel 2 Capture / Compare Register – CH2CCR .................................................................... 243
Channel 3 Capture / Compare Register – CH3CCR .................................................................... 244
Channel 0 Asymmetric Compare Register – CH0ACR................................................................. 245
Channel 1 Asymmetric Compare Register – CH1ACR................................................................. 245
Channel 2 Asymmetric Compare Register – CH2ACR................................................................. 246
Channel 3 Asymmetric Compare Register – CH3ACR................................................................. 246
14 Pulse Width Modulator (PWM)......................................................................... 247
Introduction ........................................................................................................................ 247
Features............................................................................................................................. 248
Functional Descriptions ..................................................................................................... 248
Counter Mode ............................................................................................................................... 248
Clock Controller ............................................................................................................................ 251
Trigger Controller.......................................................................................................................... 252
Slave Controller ............................................................................................................................ 253
Master Controller .......................................................................................................................... 255
Channel Controller........................................................................................................................ 256
Output Stage................................................................................................................................. 256
Update Management .................................................................................................................... 260
Single Pulse Mode........................................................................................................................ 260
Asymmetric PWM Mode ............................................................................................................... 263
Timer Interconnection ................................................................................................................... 263
Trigger Peripherals Start............................................................................................................... 265
Register Map ..................................................................................................................... 266
Register Descriptions......................................................................................................... 267
Timer Counter Conguration Register – CNTCFR ....................................................................... 267
Timer Mode Conguration Register – MDCFR............................................................................. 268
Timer Trigger Conguration Register – TRCFR............................................................................ 271
Timer Counter Register – CTR ..................................................................................................... 272
Channel 0 Output Conguration Register – CH0OCFR ............................................................... 273
Channel 1 Output Conguration Register – CH1OCFR ............................................................... 275
Channel 2 Output Conguration Register – CH2OCFR ............................................................... 277
Channel 3 Output Conguration Register – CH3OCFR ............................................................... 279
Channel Control Register – CHCTR............................................................................................. 281
Channel Polarity Conguration Register – CHPOLR.................................................................... 282
Timer Interrupt Control Register – DICTR .................................................................................... 283
Timer Event Generator Register – EVGR..................................................................................... 284
Timer Interrupt Status Register – INTSR...................................................................................... 285
Timer Counter Register – CNTR................................................................................................... 286
Timer Prescaler Register – PSCR ................................................................................................ 287
Timer Counter Reload Register – CRR ........................................................................................ 287
Channel 0 Compare Register – CH0CR....................................................................................... 288
Channel 1 Compare Register – CH1CR....................................................................................... 288
Channel 2 Compare Register – CH2CR....................................................................................... 289

Rev. 1.00 9 of 486 July 31, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F50231/HT32F50241
Table of Contents Table of Contents
Channel 3 Compare Register – CH3CR....................................................................................... 289
Channel 0 Asymmetric Compare Register – CH0ACR................................................................. 290
Channel 1 Asymmetric Compare Register – CH1ACR................................................................. 290
Channel 2 Asymmetric Compare Register – CH2ACR................................................................. 291
Channel 3 Asymmetric Compare Register – CH3ACR................................................................. 291
15 Basic Function Timer (BFTM).......................................................................... 292
Introduction ........................................................................................................................ 292
Features............................................................................................................................. 292
Functional Description ....................................................................................................... 293
Repetitive Mode............................................................................................................................ 293
One Shot Mode............................................................................................................................. 294
Trigger ADC Start.......................................................................................................................... 294
Register Map ..................................................................................................................... 295
Register Descriptions......................................................................................................... 295
BFTM Control Register – BFTMCR .............................................................................................. 295
BFTM Status Register – BFTMSR................................................................................................ 296
BFTM Counter Value Register – BFTMCNTR .............................................................................. 297
BFTM Compare Value Register – BFTMCMPR ........................................................................... 297
16 Motor Control Timer (MCTM) ........................................................................... 298
Introduction ........................................................................................................................ 298
Features............................................................................................................................. 299
Functional Descriptions ..................................................................................................... 299
Counter Mode ............................................................................................................................... 299
Clock Controller ............................................................................................................................ 303
Trigger Controller.......................................................................................................................... 304
Slave Controller ............................................................................................................................ 305
Master Controller .......................................................................................................................... 307
Channel Controller........................................................................................................................ 308
Input Stage ................................................................................................................................... 309
Output Stage..................................................................................................................................311
Update Management .................................................................................................................... 322
Single Pulse Mode........................................................................................................................ 324
Timer Interconnection ................................................................................................................... 327
Trigger ADC Start.......................................................................................................................... 331
Lock Level Table ........................................................................................................................... 331
Register Map ..................................................................................................................... 331
Register Descriptions......................................................................................................... 332
Timer Counter Conguration Register – CNTCFR ....................................................................... 332
Timer Mode Conguration Register – MDCFR............................................................................. 334
Timer Trigger Conguration Register – TRCFR............................................................................ 337
Timer Control Register – CTR ...................................................................................................... 338
Channel 0 Input Conguration Register – CH0ICFR .................................................................... 339

Rev. 1.00 10 of 486 July 31, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F50231/HT32F50241
Table of Contents
Channel 1 Input Conguration Register – CH1ICFR .................................................................... 340
Channel 2 Input Conguration Register – CH2ICFR .................................................................... 342
Channel 3 Input Conguration Register – CH3ICFR .................................................................... 343
Channel 0 Output Conguration Register – CH0OCFR ............................................................... 345
Channel 1 Output Conguration Register – CH1OCFR ............................................................... 347
Channel 2 Output Conguration Register – CH2OCFR ............................................................... 349
Channel 3 Output Conguration Register – CH3OCFR ............................................................... 351
Channel Control Register – CHCTR............................................................................................. 353
Channel Polarity Conguration Register – CHPOLR.................................................................... 355
Channel Break Conguration Register – CHBRKCFR ................................................................. 356
Channel Break Control Register – CHBRKCTR ........................................................................... 357
Timer Interrupt Control Register – DICTR .................................................................................... 359
Timer Event Generator Register – EVGR..................................................................................... 360
Timer Interrupt Status Register – INTSR...................................................................................... 362
Timer Counter Register – CNTR................................................................................................... 364
Timer Prescaler Register – PSCR ................................................................................................ 365
Timer Counter Reload Register – CRR ........................................................................................ 366
Timer Repetition Register – REPR ............................................................................................... 366
Channel 0 Capture/Compare Register – CH0CCR ...................................................................... 367
Channel 1 Capture/Compare Register – CH1CCR ...................................................................... 368
Channel 2 Capture/Compare Register – CH2CCR ...................................................................... 369
Channel 3 Capture/Compare Register – CH3CCR ...................................................................... 370
Channel 0 Asymmetric Compare Register – CH0ACR................................................................. 371
Channel 1 Asymmetric Compare Register – CH1ACR................................................................. 371
Channel 2 Asymmetric Compare Register – CH2ACR................................................................. 372
Channel 3 Asymmetric Compare Register – CH3ACR................................................................. 372
17 Real Time Clock (RTC) ..................................................................................... 373
Introduction ........................................................................................................................ 373
Features............................................................................................................................. 373
Functional Descriptions ..................................................................................................... 374
RTC Related Register Reset ........................................................................................................ 374
Low Speed Clock Conguration ................................................................................................... 374
RTC Counter Operation................................................................................................................ 374
Interrupt and Wakeup Control....................................................................................................... 374
RTCOUT Output Pin Conguration............................................................................................... 375
Register Map ..................................................................................................................... 376
Register Descriptions......................................................................................................... 376
RTC Counter Register – RTCCNT................................................................................................ 376
RTC Compare Register – RTCCMP............................................................................................. 377
RTC Control Register – RTCCR................................................................................................... 378
RTC Status Register – RTCSR..................................................................................................... 380
RTC Interrupt and Wakeup Enable Register – RTCIWEN........................................................... 381

Rev. 1.00 11 of 486 July 31, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F50231/HT32F50241
Table of Contents Table of Contents
18 Watchdog Timer (WDT) .................................................................................... 382
Introduction ........................................................................................................................ 382
Features............................................................................................................................. 382
Functional Description ....................................................................................................... 383
Register Map ..................................................................................................................... 385
Register Descriptions......................................................................................................... 385
Watchdog Timer Control Register – WDTCR ............................................................................... 385
Watchdog Timer Mode Register 0 – WDTMR0............................................................................. 386
Watchdog Timer Mode Register 1 – WDTMR1............................................................................. 387
Watchdog Timer Status Register – WDTSR ................................................................................. 388
Watchdog Timer Protection Register – WDTPR ........................................................................... 389
Watchdog Timer Clock Selection Register – WDTCSR............................................................... 390
19 Inter-Integrated Circuit (I2C)............................................................................. 391
Introduction ........................................................................................................................ 391
Features............................................................................................................................. 392
Functional Descriptions ..................................................................................................... 392
Two-Wire Serial Interface ............................................................................................................. 392
START and STOP Conditions....................................................................................................... 392
Data Validity.................................................................................................................................. 393
Addressing Format ....................................................................................................................... 394
Data Transfer and Acknowledge................................................................................................... 396
Clock Synchronization .................................................................................................................. 397
Arbitration ..................................................................................................................................... 397
General Call Addressing ............................................................................................................... 398
Bus Error....................................................................................................................................... 398
Address Mask Enable................................................................................................................... 398
Address Snoop ............................................................................................................................. 398
Operation Mode ............................................................................................................................ 398
Conditions of Holding SCL Line.................................................................................................... 404
I2C Timeout Function .................................................................................................................... 405
Register Map ..................................................................................................................... 405
Register Descriptions......................................................................................................... 406
I2C Control Register – I2CCR ....................................................................................................... 406
I2C Interrupt Enable Register – I2CIER ........................................................................................ 407
I2C Address Register – I2CADDR................................................................................................. 409
I2C Status Register – I2CSR......................................................................................................... 410
I2C SCL High Period Generation Register – I2CSHPGR.............................................................. 413
I2C SCL Low Period Generation Register – I2CSLPGR ............................................................... 414
I2C Data Register – I2CDR ........................................................................................................... 415
I2C Target Register – I2CTAR ....................................................................................................... 416
I2C Address Mask Register – I2CADDMR .................................................................................... 417
I2C Address Snoop Register – I2CADDSR................................................................................... 418
I2C Timeout Register – I2CTOUT.................................................................................................. 419

Rev. 1.00 12 of 486 July 31, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F50231/HT32F50241
Table of Contents
20 Serial Peripheral Interface (SPI) ...................................................................... 420
Introduction ........................................................................................................................ 420
Features............................................................................................................................. 421
Function Descriptions ........................................................................................................ 421
Master Mode................................................................................................................................. 421
Slave Mode................................................................................................................................... 421
SPI Serial Frame Format .............................................................................................................. 422
Status Flags.................................................................................................................................. 426
Register Map ..................................................................................................................... 428
Register Descriptions......................................................................................................... 429
SPI Control Register 0 – SPICR0 ................................................................................................. 429
SPI Control Register 1 – SPICR1 ................................................................................................. 431
SPI Interrupt Enable Register – SPIIER ....................................................................................... 432
SPI Clock Prescaler Register – SPICPR ...................................................................................... 433
SPI Data Register – SPIDR .......................................................................................................... 434
SPI Status Register – SPISR........................................................................................................ 435
SPI FIFO Control Register – SPIFCR........................................................................................... 437
SPI FIFO Status Register – SPIFSR ............................................................................................ 438
SPI FIFO Time Out Counter Register – SPIFTOCR..................................................................... 439
21 Universal Synchronous Asynchronous Receiver Transmitter (USART) ..... 440
Introduction ........................................................................................................................ 440
Features............................................................................................................................. 441
Functional Descriptions ..................................................................................................... 441
Serial Data Format........................................................................................................................ 441
Baud Rate Generation .................................................................................................................. 442
Hardware Flow Control ................................................................................................................. 443
IrDA............................................................................................................................................... 444
RS485 Mode................................................................................................................................. 446
Synchronous Master Mode........................................................................................................... 448
Interrupts and Status .................................................................................................................... 450
Register Map ..................................................................................................................... 450
Register Descriptions......................................................................................................... 451
USART Data Register – USRDR.................................................................................................. 451
USART Control Register – USRCR.............................................................................................. 452
USART FIFO Control Register – USRFCR................................................................................... 454
USART Interrupt Enable Register – USRIER ............................................................................... 455
USART Status & Interrupt Flag Register – USRSIFR................................................................... 457
USART Timing Parameter Register – USRTPR ........................................................................... 459
USART IrDA Control Register – IrDACR ...................................................................................... 460
USART RS485 Control Register – RS485CR............................................................................... 461
USART Synchronous Control Register – SYNCR ........................................................................ 462
USART Divider Latch Register – USRDLR................................................................................... 463
USART Test Register – USRTSTR............................................................................................... 464

Rev. 1.00 13 of 486 July 31, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F50231/HT32F50241
Table of Contents Table of Contents
22 Universal Asynchronous Receiver Transmitter (UART)................................ 465
Introduction ........................................................................................................................ 465
Features............................................................................................................................. 466
Function Descriptions ........................................................................................................ 466
Serial Data Format........................................................................................................................ 466
Baud Rate Generation .................................................................................................................. 467
Interrupts and Status .................................................................................................................... 468
Register Map ..................................................................................................................... 468
Register Descriptions......................................................................................................... 469
UART Data Register – URDR....................................................................................................... 469
UART Control Register – URCR................................................................................................... 470
UART Interrupt Enable Register – URIER.................................................................................... 471
UART Status & Interrupt Flag Register – URSIFR ....................................................................... 472
UART Divider Latch Register – URDLR ....................................................................................... 474
UART Test Register – URTSTR.................................................................................................... 475
23 Divider (DIV) ...................................................................................................... 476
Introduction ........................................................................................................................ 476
Features............................................................................................................................. 476
Functional Descriptions ..................................................................................................... 476
Register Map ..................................................................................................................... 477
Register Descriptions......................................................................................................... 477
Divider Control Register – CR ...................................................................................................... 477
Dividend Data Register – DDR ..................................................................................................... 478
Divisor Data Register – DSR ........................................................................................................ 478
Quotient Data Register – QTR...................................................................................................... 479
Remainder Data Register – RMR ................................................................................................. 479
24 Cyclic Redundancy Check (CRC).................................................................... 480
Introduction ....................................................................................................................... 480
Features............................................................................................................................. 480
Functional Descriptions ..................................................................................................... 481
CRC Computation......................................................................................................................... 481
Byte and Bit Reversal for CRC Computation................................................................................ 481
Register Map ..................................................................................................................... 482
Register Descriptions......................................................................................................... 482
CRC Control Register – CRCCR .................................................................................................. 482
CRC Seed Register – CRCSDR................................................................................................... 483
CRC Checksum Register – CRCCSR .......................................................................................... 484
CRC Data Register – CRCDR ...................................................................................................... 485

Rev. 1.00 14 of 486 July 31, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F50231/HT32F50241
List of Tables
List of Tables
Table 1. Features and Peripheral List ..................................................................................................... 25
Table 2. Document Conventions............................................................................................................. 27
Table 3. Register Map............................................................................................................................. 32
Table 4. Flash Memory and Option Byte................................................................................................. 36
Table 5. Booting Modes .......................................................................................................................... 37
Table 6. Option Byte Memory Map ......................................................................................................... 41
Table 7. Access Permission of Protected Main Flash Page.................................................................... 42
Table 8. Access Permission When Security Protection is Enabled......................................................... 43
Table 9. FMC Register Map .................................................................................................................... 44
Table 10. Operation Mode Denitions..................................................................................................... 63
Table 11. Enter / Exit Power Saving Modes............................................................................................ 64
Table 12. Power Status After System Reset ........................................................................................... 64
Table 13. PWRCU Register Map ............................................................................................................ 64
Table 14. CKOUT Clock Source ............................................................................................................. 76
Table 15. CKCU Register Map ............................................................................................................... 77
Table 16. RSTCU Register Map ........................................................................................................... 100
Table 17. AFIO, GPIO and I/O Pad Control Signal True Table.............................................................. 107
Table 18. GPIO Register Map............................................................................................................... 108
Table 19. AFIO Selection for Peripheral Map Example......................................................................... 141
Table 20. AFIO Register Map................................................................................................................ 141
Table 21. Exception Types.................................................................................................................... 146
Table 22. NVIC Register Map ............................................................................................................... 148
Table 23. EXTI Register Map................................................................................................................ 152
Table 24. Data Format in ADCDR [15:0]............................................................................................... 167
Table 25. A/D Converter Register Map ................................................................................................. 169
Table 26. Counting Direction and Encoding Signals............................................................................. 200
Table 27. Compare Match Output Setup .............................................................................................. 201
Table 28. GPTM Register Map ............................................................................................................. 212
Table 29. GPTM Internal Trigger Connection ....................................................................................... 217
Table 30. Compare Match Output Setup .............................................................................................. 257
Table 31. PWM Register Map ............................................................................................................... 266
Table 32. PWM Internal Trigger Connection ......................................................................................... 271
Table 33. BFTM Register Map .............................................................................................................. 295
Table 34. Compare Match Output Setup .............................................................................................. 312
Table 35. Output Control Bits for Complementary Output with a Break Event Occurrence.................. 321
Table 36. Lock Level Table.................................................................................................................... 331
Table 37. MCTM Register Map ............................................................................................................. 331
Table 38. MCTM Internal Trigger Connection ....................................................................................... 337
Table 39. LSE Startup Mode Operating Current and Startup Time....................................................... 374

Rev. 1.00 15 of 486 July 31, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F50231/HT32F50241
List of Tables List of Tables
Table 40. RTCOUT Output Mode and Active Level Setting .................................................................. 375
Table 41. RTC Register Map................................................................................................................. 376
Table 42. Watchdog Timer Register Map.............................................................................................. 385
Table 43. Conditions of Holding SCL line.............................................................................................. 404
Table 44. I2C Register Map ................................................................................................................... 405
Table 45. I2C Clock Setting Example .................................................................................................... 414
Table 46. SPI Interface Format Setup................................................................................................... 422
Table 47. SPI Mode Fault Trigger Conditions ....................................................................................... 427
Table 48. SPI Master Mode SEL Pin Status ......................................................................................... 427
Table 49. SPI Register Map .................................................................................................................. 428
Table 50. Baud Rate Deviation Error Calculation – CK_USART = 20 MHz.......................................... 443
Table 51. Baud Rate Deviation Error Calculation – CK_USART = 10 MHz.......................................... 443
Table 52. USART Register Map............................................................................................................ 450
Table 53. Baud Rate Deviation Error Calculation – CK_UART = 20 MHz ............................................ 467
Table 54. Baud Rate Deviation Error Calculation – CK_UART = 10 MHz ............................................ 468
Table 55. UART Register Map .............................................................................................................. 468
Table 56. DIV Register Map.................................................................................................................. 477
Table 57. CRC Register Map ................................................................................................................ 482

Rev. 1.00 16 of 486 July 31, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F50231/HT32F50241
List of Figures
List of Figures
Figure 1. Block Diagram ......................................................................................................................... 26
Figure 2. Cortex®-M0+ Block Diagram.................................................................................................... 29
Figure 3. Bus Architecture ...................................................................................................................... 30
Figure 4. Memory Map............................................................................................................................ 31
Figure 5. Flash Memory Controller Block Diagram................................................................................. 34
Figure 6. Flash Memory Map.................................................................................................................. 35
Figure 7. Vector Remapping ................................................................................................................... 37
Figure 8. Page Erase Operation Flowchart ............................................................................................ 38
Figure 9. Mass Erase Operation Flowchart ............................................................................................ 39
Figure 10. Word Programming Operation Flowchart .............................................................................. 40
Figure 11. PWRCU Block Diagram......................................................................................................... 60
Figure 12. Power On Reset / Power Down Reset Waveform ................................................................. 62
Figure 13. CKCU Block Diagram ............................................................................................................ 71
Figure 14. External Crystal, Ceramic and Resonators for HSE.............................................................. 72
Figure 15. HSI Auto Trimming Block Diagram ........................................................................................ 74
Figure 16. External Crystal, Ceramic and Resonators for LSE .............................................................. 75
Figure 17. RSTCU Block Diagram.......................................................................................................... 98
Figure 18. Power On Reset Sequence ................................................................................................... 99
Figure 19. GPIO Block Diagram ........................................................................................................... 105
Figure 20. AFIO / GPIO Control Signal................................................................................................. 107
Figure 21. AFIO Block Diagram ............................................................................................................ 139
Figure 22. EXTI Channel Input Selection ............................................................................................. 140
Figure 23. EXTI Block Diagram ............................................................................................................ 149
Figure 24. EXTI Wakeup Event Management ...................................................................................... 150
Figure 25. EXTI Interrupt Debounce Function ...................................................................................... 151
Figure 26. ADC Block Diagram ............................................................................................................ 161
Figure 27. One Shot Conversion Mode ................................................................................................ 164
Figure 28. Continuous Conversion Mode ............................................................................................. 164
Figure 29. Discontinuous Conversion Mode......................................................................................... 166
Figure 30. GPTM Block Diagram.......................................................................................................... 185
Figure 31. Up-counting Example .......................................................................................................... 186
Figure 32. Down-counting Example...................................................................................................... 187
Figure 33. Center-aligned Counting Example....................................................................................... 188
Figure 34. GPTM Clock Source Selection ............................................................................................ 189
Figure 35. Trigger Controller Block ....................................................................................................... 190
Figure 36. Slave Controller Diagram .................................................................................................... 191
Figure 37. GPTM in Restart Mode........................................................................................................ 191
Figure 38. GPTM in Pause Mode ......................................................................................................... 192
Figure 39. GPTM in Trigger Mode ........................................................................................................ 192

Rev. 1.00 17 of 486 July 31, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F50231/HT32F50241
List of Figures List of Figures
Figure 40. Master GPTMn and Slave GPTMm / MCTMm Connection................................................. 193
Figure 41. MTO Selection..................................................................................................................... 193
Figure 42. Capture / Compare Block Diagram...................................................................................... 194
Figure 43. Input Capture Mode............................................................................................................. 195
Figure 44. PWM Pulse Width Measurement Example.......................................................................... 196
Figure 45. Channel 0 and Channel 1 Input Stages............................................................................... 197
Figure 46. Channel 2 and Channel 3 Input Stages............................................................................... 198
Figure 47. TI0 Digital Filter Diagram with N = 2.................................................................................... 198
Figure 48. Input Stage and Quadrature Decoder Block Diagram ......................................................... 199
Figure 49. Both TI0 and TI1 Quadrature Decoder Counting................................................................. 200
Figure 50. Output Stage Block Diagram ............................................................................................... 201
Figure 51. Toggle Mode Channel Output Reference Signal – CHxPRE = 0......................................... 202
Figure 52. Toggle Mode Channel Output Reference Signal – CHxPRE = 1......................................... 202
Figure 53. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode ............ 203
Figure 54. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode ....... 203
Figure 55. PWM Mode Channel Output Reference Signal and Counter in Centre-aligned Mode........ 204
Figure 56. Update Event Setting Diagram ............................................................................................ 205
Figure 57. Single Pulse Mode............................................................................................................... 206
Figure 58. Immediate Active Mode Minimum Delay ............................................................................. 207
Figure 59. Asymmetric PWM Mode versus Center-aligned Counting Mode......................................... 208
Figure 60. Pausing MCTM using the GPTM CH0OREF Signal............................................................ 209
Figure 61. Triggering MCTM with GPTM Update Event ....................................................................... 210
Figure 62. Trigger GPTM and MCTM with the GPTM CH0 Input ..........................................................211
Figure 63. PWM Block Diagram ........................................................................................................... 247
Figure 64. Up-counting Example .......................................................................................................... 248
Figure 65. Down-counting Example...................................................................................................... 249
Figure 66. Center-aligned Counting Example....................................................................................... 250
Figure 67. PWM Clock Selection Source.............................................................................................. 251
Figure 68. Trigger Control Block ........................................................................................................... 252
Figure 69. Slave Controller Diagram .................................................................................................... 253
Figure 70. PWM in Restart Mode ......................................................................................................... 253
Figure 71. PWM in Pause Mode........................................................................................................... 254
Figure 72. PWM in Trigger Mode.......................................................................................................... 254
Figure 73. Master PWMn and Slave PWMm / TMm Connection.......................................................... 255
Figure 74. MTO Selection..................................................................................................................... 255
Figure 75. Compare Block Diagram ..................................................................................................... 256
Figure 76. Output Stage Block Diagram ............................................................................................... 256
Figure 77. Toggle Mode Channel Output Reference Signal (CHxPRE = 0) ......................................... 257
Figure 78. Toggle Mode Channel Output Reference Signal (CHxPRE = 1) ......................................... 258
Figure 79. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode ............ 258
Figure 80. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode ....... 259

Rev. 1.00 18 of 486 July 31, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F50231/HT32F50241
List of Figures
Figure 81. PWM Mode Channel Output Reference Signal and Counter in Centre-aligned Mode........ 259
Figure 82. Update Event Setting Diagram ............................................................................................ 260
Figure 83. Single Pulse Mode............................................................................................................... 261
Figure 84. Immediate Active Mode Minimum Delay ............................................................................. 262
Figure 85. Asymmetric PWM Mode versus Center-aligned Counting Mode......................................... 263
Figure 86. Pausing PWM1 using the PWM0 CH0OREF Signal ........................................................... 264
Figure 87. Triggering PWM1 with PWM0 Update Event....................................................................... 264
Figure 88. Trigger PWM0 and PWM1 with the PWM0 Timer Enable Signal ........................................ 265
Figure 89. BFTM Block Diagram .......................................................................................................... 292
Figure 90. BFTM – Repetitive Mode..................................................................................................... 293
Figure 91. BFTM – One Shot Mode...................................................................................................... 294
Figure 92. BFTM – One Shot Mode Counter Updating ....................................................................... 294
Figure 93. MCTM Block Diagram ......................................................................................................... 298
Figure 94. Up-counting Example .......................................................................................................... 300
Figure 95. Down-counting Example...................................................................................................... 300
Figure 96. Center-aligned Counting Example....................................................................................... 301
Figure 97. Update Event 1 Dependent Repetition Mechanism Example.............................................. 302
Figure 98. MCTM Clock Selection Source............................................................................................ 303
Figure 99. Trigger Controller Block ....................................................................................................... 304
Figure 100. Slave Controller Diagram .................................................................................................. 305
Figure 101. MCTM in Restart Mode ..................................................................................................... 305
Figure 102. MCTM in Pause Mode....................................................................................................... 306
Figure 103. MCTM in Trigger Mode...................................................................................................... 306
Figure 104. Master MCTMn and Slave GPTM Connection .................................................................. 307
Figure 105. MTO Selection................................................................................................................... 307
Figure 106. Capture/Compare Block Diagram...................................................................................... 308
Figure 107. Input Capture Mode........................................................................................................... 308
Figure 108. PWM Pulse Width Measurement Example........................................................................ 309
Figure 109. Channel 0 and Channel 1 Input Stages............................................................................. 310
Figure 110. Channel 2 and Channel 3 Input Stages............................................................................. 310
Figure 111. TI0 Digital Filter Diagram with N = 2 ...................................................................................311
Figure 112. Output Stage Block Diagram ..............................................................................................311
Figure 113. Toggle Mode Channel Output Reference Signal – CHxPRE = 0 ....................................... 312
Figure 114. Toggle Mode Channel Output Reference Signal – CHxPRE = 1 ....................................... 313
Figure 115. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode .......... 313
Figure 116. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode...... 314
Figure 117. PWM Mode 1 Channel Output Reference Signal and Counter in Centre-aligned Counting
Mode...................................................................................................................................................... 314
Figure 118. Dead-time Insertion Performed for Complementary Outputs............................................. 315
Figure 119. MCTM Break Signal Bolck Diagram .................................................................................. 316
Figure 120. MT_BRK Pin Digital Filter Diagram with N = 2 .................................................................. 316

Rev. 1.00 19 of 486 July 31, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F50231/HT32F50241
List of Figures List of Figures
Figure 121. Channel 3 Output with a Break Event Occurrence............................................................ 317
Figure 122. Channel 0 ~2 Complementary Outputs with a Break Event Occurrence........................... 318
Figure 123. Channel 0 ~2 Only One Output Enabled when Break Event Occurs ................................ 319
Figure 124. Hardware Protection When Both CHxO and CHxNO are in Active Condition ................... 320
Figure 125. Update Event 1 Setup Diagram......................................................................................... 322
Figure 126. CHxE, CHxNE and CHxOM Updated by Update Event 2 ................................................. 323
Figure 127. Update Event 2 Setup Diagram......................................................................................... 323
Figure 128. Single Pulse Mode............................................................................................................. 324
Figure 129. Immediate Active Mode Minimum Delay ........................................................................... 325
Figure 130. Asymmetric PWM Mode versus Center-aligned Counting Mode....................................... 326
Figure 131. Pausing GPTM using the MCTM CH0OREF Signal.......................................................... 327
Figure 132. Triggering GPTM with MCTM Update Event 1 .................................................................. 328
Figure 133. Figure 41 Trigger MCTM and GPTM with the MCTM CH0 Input....................................... 329
Figure 134. CH1XOR Input as Hall Sensor Interface ........................................................................... 330
Figure 135. RTC Block Diagram........................................................................................................... 373
Figure 136. Watchdog Timer Block Diagram ....................................................................................... 382
Figure 137. Watchdog Timer Behavior ................................................................................................. 384
Figure 138. I2C Module Block Diagram................................................................................................. 391
Figure 139. START and STOP Condition ............................................................................................. 393
Figure 140. Data Validity....................................................................................................................... 393
Figure 141. 7-bit Addressing Mode....................................................................................................... 394
Figure 142. 10-bit Addressing Write Transmit Mode ............................................................................ 395
Figure 143. 10-bits Addressing Read Receive Mode .......................................................................... 395
Figure 144. I2C Bus Acknowledge ........................................................................................................ 396
Figure 145. Clock Synchronization during Arbitration........................................................................... 397
Figure 146. Two Master Arbitration Procedure ..................................................................................... 397
Figure 147. Master Transmitter Timing Diagram .................................................................................. 399
Figure 148. Master Receiver Timing Diagram ...................................................................................... 401
Figure 149. Slave Transmitter Timing Diagram .................................................................................... 402
Figure 150. Slave Receiver Timing Diagram ........................................................................................ 403
Figure 151. SCL Timing Diagram.......................................................................................................... 414
Figure 152. SPI Block Diagram ............................................................................................................ 420
Figure 153. SPI Single Byte Transfer Timing Diagram – CPOL = 0, CPHA = 0.................................... 422
Figure 154. SPI Continuous Data Transfer Timing Diagram – CPOL = 0, CPHA = 0........................... 423
Figure 155. SPI Single Byte Transfer Timing Diagram – CPOL = 0, CPHA = 1.................................... 423
Figure 156. SPI Continuous Transfer Timing Diagram – CPOL = 0, CPHA = 1.................................... 424
Figure 157. SPI Single Byte Transfer Timing Diagram – CPOL = 1, CPHA = 0.................................... 424
Figure 158. SPI Continuous Transfer Timing Diagram – CPOL = 1, CPHA = 0.................................... 425
Figure 159. SPI Single Byte Transfer Timing Diagram – CPOL = 1, CPHA = 1.................................... 425
Figure 160. SPI Continuous Transfer Timing Diagram – CPOL = 1, CPHA = 1.................................... 425
Figure 161. SPI Multi-Master Slave Environment................................................................................. 427

Rev. 1.00 20 of 486 July 31, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F50231/HT32F50241
List of Figures
Figure 162. USART Block Diagram ...................................................................................................... 440
Figure 163. USART Serial Data Format ............................................................................................... 442
Figure 164. USART Clock CK_USART and Data Frame Timing.......................................................... 442
Figure 165. Hardware Flow Control between 2 USARTs...................................................................... 443
Figure 166. USART RTS Flow Control ................................................................................................. 444
Figure 167. USART CTS Flow Control ................................................................................................. 444
Figure 168. IrDA Modulation and Demodulation................................................................................... 445
Figure 169. USART I/O and IrDA Block Diagram ................................................................................. 446
Figure 170. RS485 Interface and Waveform ........................................................................................ 447
Figure 171. USART Synchronous Transmission Example ................................................................... 448
Figure 172. Figure 11. 8-bit Format USART Synchronous Waveform .................................................. 449
Figure 173. UART Block Diagram......................................................................................................... 465
Figure 174. UART Serial Data Format.................................................................................................. 466
Figure 175. UART Clock CK_UART and Data Frame Timing............................................................... 467
Figure 176. Divider Functional Diagram ............................................................................................... 476
Figure 177. CRC Block Diagram .......................................................................................................... 480
Figure 178. CRC Data Bit and Byte Reversal Example........................................................................ 481