HP 5245L User manual

HEWLE"9PACKARD \-/
CERTIFICATION
The Hewlett-Packard, Company certifies that this instrument was
thoroughly tested and inspected and found to meet its published
specifications when it was shipped from the factory. The Hewlett-
Packard Company f urther certifies that its calibration meesurements
are traceable to the U. S. N ational Bureau of Standards to the extent
allowed by the Bureau's calibration f acility.
WARRANTY AN D ASSISTANC E
All Hewlett-Packard products are warranted against defects in
materials and workmanship. 'fhis warranty applies for one year from
the date of delivery, or, in the case of certain major components listed
in the operating manual, for the specified period. We will repair or
replace products which prove to be defective during the warranty
period. No other warranty is expressed or implied. We are not liable
for consequential damages.
For any assistance contact your nearest Hewlett-Packard Sales and
Service Office. Addresses are provided at the back of this manual.
\-/
\-/

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SERVICE MANUAL
MODEL 5245L
ELECTRONIC COUNTER
SERIALS PREFIXED: 628-
This manualapplies directlyto@ Model 5245L Elec-
tronic Counters having serial prefix number 628.
SERIAL PREFIXES NOT LISTED
For serialprefixes above 628, a change sheetwill be
included with the manual. For serial prefixes below
628, refer to 5245L Operating and Service Manual
serial prefixed 544.
OPTIONS
This manualwith changes described in Section V also
applies to Options 02 and 03.
copyrishr HEWTETT-PACKARO COIIpANy 1966
I5OI PAGE 'IAIII- ROAD, PATO AIIO, CATIFORNIA, U,S.A.
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02349-1 Pilnted: SIPT lg00

Foreword Model 5245L
TIANUAT CONTENT
This is a Service Manual only. Operating instructions
are outlined in a separate Operating Manual. This Ser-
vice Manual is supplied to help you make best use of
your @ Vtodet 5245L Electronic Counter. Seven sections
of information are included as follows:
Section I is an introduction to the counter. This in-
cludes a table of technical specifications.
Section II discusses detailed theory for the circuits
used.
Section III outlines a performance check procedure
to verify operation.
Section tV lists parts for the counter.
SectionV covers available options and manual changes
required to backdate this manual.
Section VI contains adjustment and troubleshooting
procedures which include a self check.
Section VII is the circuit diagrams for the counter.
These include block diagrams, schematic diagrams,
and some waveforms and voltages. )
\-/
HOW TO ORDER
To order anOperating or Service Manual for yourElec-
tronic Counter, contact the nearest Hewlett-Packard
Sales and Service Office. Lists are provided at theback
of this manual. Give complete 8-digit serial number
and name of instrument. Comments and suggestions
concerning this manual are welcome at any Sales and
Service Office.
-!
I1
l
02 349 -1

Model 5245L Table of Contents
TABIE OF CONTENTS
Section
I GENERAL INFORMATION
1-1. Introduction
1-6. Instrument Identification
1-9: Installation and Operation
ru PERFORMANCE CHECK
ry REPLACEABLE PARTS
4-1. Introduction
4-4. Ordering Information .
V OPTIONS AND MANUAL CHANGES
5 - 1. Options
5-3. Option 02 +1248 BCD Code
5-5. Option 03 -1248 BCD Code
5 -9. Specials
5-13. Manual Changes
PRINCIPLES OF OPERATION . . .2-I
2-1. Introduction . .2-l
2-3. The Diode. . .2-L
z-lL. TheTransistor .....2-2
2-25. Basic Operation of Decimal Counter or Decade Divider . .2-4
2-36. Basic Counter Functions . . .2-9
2-44. Time Sequence .2-10
2-4g. OveralldounterOperation .....2-tl
2-5L. Input Switch Assembly A1 .z-tl
2-54. ' Time-Base Switch Assembly A2 .2-13
2-56. Function Switch Assembly A3 . . .2-13
2-58. Mode Switch Assembly A4 .2-L3
2-60. Output Switch Assembly A5 2-L4
2-62. PowerSupply: Rectifier Assembly4.6; Regulator AssemblyA? .2-14
2-70. Decimal Point Assembly A8 . . .z-ts
2-73. Measurement Units Assembly A9 2-15
2-76. Low Frequency Decimal Counter Assembly A10-A14 . . .2-15
2-78. 5 MHz Decimal Counter Assembly A15, A16 . 2-L5
2-80. 50 MHz Decimal Counter Assembly A.1? . . . .z-Ls
2-84. 50 MHz Readout Assembly A18 . .2-18
2-88. Input Amplifier Assembly A19-A20 . . .2-L8
2-91. Function Control Assembly A21 .z-tg
2-95. Gate Control Assembly A22 . . .2-20
2-99. Sampling Control Assembly A23 .2-21
2-105. Oscillator and Oven A24, A25, A26 . . .2-22
z-LlL. Multiplier Assembly A27 .2-22
2-113. 5 MHz Decade Divider Assembly A2B. .2-22
2-tt5. Low-Frequency Decade Divider Assembly A29-A34 2-22
2-Lt7. Time-Base Control Assembly A35 . . .2-23
Page
. . .1-1
. . .1-1
. . .1-1
. . .1-1
.3-1
.4-t
.4-1
.4-l
. 5-1
5-1
5- 14.
5 -16.
6-18.
6- 19.
6 -21.
6-23.
Current Instruments
OIder Instruments
. 5-1
. 5-1
.5-1
.6-1
.5-1
.6-1
.6-1
.6-1
. 6-1
.6-1
.6-2
.6-2
.6-2
.6-2
.6-2
. 6-3
. 6-3
. 6-3
. 6-3
.6-3
.6-3
.7-1
VI ADJUSTMENT AND TROUBLESHOOTING. . . .
6-1. Introduction
6-3. Mai.ntenance
6-?. Test Equipment. . .
6-9. Assembly Connection Identification
6-11. Instrument Cover Removal
6-13. Assembly Location
6-15. Printed Circuit Component Replacement
6-17. Adjustments .
Regulator Assembly A? . . . . .
Input Amplifier A19
Ration Input Amplifier A20
Function Control y',2l. .
6-24. Troubleshooting
6-25. Troubleshooting Aids
6-32. Troubleshooting Procedure
CIRCUIT DIAGRAMS
02349-1 IIl

List of Illustrations
Assembly
Model 5245L
Page
.1-0
. 2-1
. 2-2
. 2-3
. 2-4
. 2-5
. 2-6
. 2-7
. 2-B
.2-10
. 2-t0
. z-tt
. 2-tL
. 2-L2
. 2-L6
. 2-t7
. 2-18
. 2-L9
. 2-20
. 2-2t
. 4-35
. 4-45
. 5-t4
. 5-16
.5-18
. 6-4
. 6-6
. 6-?
.6-8
.6-9
usT oF rrrusTRATtoNS
Figure
1-1. Model 5245L and Accessories
Basic Diode Circuits
Transistor Operation
Basic Transistor Circuits
Basic Operation of Decimal Counter or Decade Divider . .
Basic Four Binary Counter
Counting Sequence of Four Binary Counter
Typical Reset Operation in Four Binary Decimal Counter
Lamp Control
Basic Counter Functions
Standard Frequency Outputs
2-ll. Scaler Operation
2-t.
2-2.
2-3.
2-4.
2-5.
2-6.
2-7.
2-8.
2-9.
2-10.
2-L2. Time Sequence
2-13. Model 5245L Logic Block Diagram
2-14. Decimal Counter and Decade Divider
2-15. 50 MHz Counting Sequence
2-16. 50 MHz Readout and 50 MHz Counter
2-17. Function Control Block Diagram
2-18. Gate Control Block Diagram
2-19. Sampling Control Block Diagram .
4-1. Modular Cabinet Parts
4-2. Mechanical Parts Locations
5-1. DP and MU with +L248 BCD Output (J35-5245L Special)
5-2. DP and MU with -L248 BCD Output (J36-5245L Speciat)
5-3. Remote Control Wiring and Connectors (Special)
6-1. Self Check . . .
6-2. Operating Controls (Front Panel)
6-3. Operating Controls (Rear Panel)
6-4. Top Internal View
6-5. Bottom Internal View
?-1. General Notes for Schematic Diagrams
7-2. Block Diagram
7-3. Al Input Switch
1-4. A2 Time Base Switch
7-5. A3 Function Switch . . .
7-6. A4, A5 Mode Switch, Output Switch
7 -7.
7 -8.
?-9.
?- 10.
?-11.
7 -12.
?- 13.
7 -L4.
?- 15.
7- 16.
7-L7.
?-18.
?- 19.
7 -20.
7 -21.
7-22. A2? Multiplier
7-23. A28 Decade Divider.
7-24. A29-A34 Decade Divider
7-25. A35 Time Base Control
7-26. J6, J11 Connectors
A1? Decimal Counter
A18 Readout (5245L-48)
AlB Readout (05245-6001) Option 02
A18 Readout (05245-6003) Option 03
A19, A20 Input Amplifier
A21 Function Control
A22 Gate Control.
A23 Sampling Control
A24, A25, 4,26 Crystal Oven, Oven Control,
;i";kb;s;;* ::::
Block Diagram
Oscillator . .
46, AT Rectifier, Regulator
A8, A9 Decimal Point, Measurement Units . .
A10-A14 Decimal Counter (5212L-4A)
A10-A14 Decimal Counter (05212-6002, 6003) Option 02,03
A15, 4'16 5 MHz Decimal Counter (05232-6010)
A15, 4'16 Decimal Counter (05232-6002,6003) Option 02, 03 . .
7-2
?-3
7-5
7-7
?-9
7- 11
7-13
7- 15
7 -t7
?- 19
7 -2t
7 -23
7 -25
7 -27
7 -29
?-3 1
7-33
?-35
7 -37
?-39
7 -41
7-43
1-45
7 -47
7-49
7- 51
1V 02349-1

Model 5245L List of Tables
r
I
I
I
I
tIST OF TABTES
Table Page
1-1. Specifications l-2
2-L. Four-Line Code Truth Table 2-7
2-2. Power Supplies 2-L4
2-3. Basic Operation Summary of Four-Binary Counter 2-L5
2-4. Normal Time Base Control 2-23
2-5. Multiplied Period Control 2-23
3-1. Recommended Test Equipment . 3-1
3-2. In-Cabinet Performance Check . 3-2
4-L. Reference Designation Index . . 4-z
4-2. Replaceable Parts . 4-36
4-3. Manufacturer's Code List 4-46
5-1. Option 02 Replacement Assemblies 5-1
5-2. Option 03 Replacement Assemblies 5-1
5-3. L-2-4-B Code Truth Table 5-1
5-4. Reference Designation Index (A18, Option 02) 5-2
5-5. Reference Designation Index (A18, Option 03) . . 5-5
5-6. Reference Designation Index (A15, A16, Options 02 & 03) 5-8
5-?. Reference Designation Index (A10-A14, Options 02 & 03) 5-11
5-8. Reference Designation Index (J35-5245L) 5-15
5-9. Reference Designation Index (J36-5245L) 5-17
6-1. Fuse Replacement 6-1
6-2. Recommended Test Equipment 6-1
6-3. Assembly Designations . 6-2
6-4. Power Supply Voltages 6-3
6-5. Period Average Checks with External Signal . . 6-5
6-6. Assembly Check 6-5
6-1. Troubleshooting "Tree" 6-10
6-8. Self Check. . . 6-15
02349-1

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Se ction I
Figure t -1 Model 5245L
1-0
Figure l,-1. Model 5245L and Accessories
02 349 -1

Model 5245L Section I
,Paragraphs 1-1 to 1-10
SECTION I
CENERAT INFORMATION
I-I. INTRODUCTION.
L.2. DESCRIPTION.
1-3. The HP Model 5245L Electronic Counter is a
high-frequency general-purpose electronic courter.
The Model 5245L measures frequencies from 0 to 50
Mfu, periods from 1 p. sec to 10 seconds, period
averages from 10 to 1001000 periods, the ratio of two
frequencies, andthe multiplied ratio of hvofrequencies.
l-4. The HP Model 5245L provides these additional
features:
a. Decade scaling to 1Og for any frequency to
50 MHz.
b. Standard output frequencies from 0.1 Hz to 10
MHz in decade steps.
c. Four-line, binary-coded-decimal output to drive
digital recorder (HP Model 562A), digital to analog
converter (HP Model 580A/581A), remote readout,
or data processirg; equipment (1-2-2-4 code; L-2-4-8
code available (see Section V).
€. Display storage whichpermits readingto bedis-
played while new count is made.
d. Remote control by external contact closure avail-
able (see Section V).
f. Eight-digit display using rectangular (narrow)
digitat display tube s; decimal point position and meas-
urement units displayed automatically.
g. Operation with plug-in units which extend the
basic range and performance of the counter.
1-5. The Model 5245L features solid state design,
low power consumption, small size (5-1/4 ineh panel
height), lightweight (32 1b), easy conversionforrack
mounting, and modular plug-in circuit boards for
simplif ied maintenance.
I-6. INSTRUMENT IDENTIFICATION.
t-7. EachModel 5245Lis identified bya two-section,
eight-digit (000-00000) serial number on the rear
panel. The five-digit number is an identification
number unique to each instrument, and the three-digit
number is a serial prefix number, used to document
changes.
1-8. AII instruments with the same serial prefix are
the same. The group of instruments to which this
manual applies directly is identified on the title page.
For older instruments (lower serial numbers), make
manual changes listed in Section VL For newer in-
struments, having serial numbers higher than those
listed on the title page, a Manual Change sheet is in-
cluded, describing the required changes. The manual
for an instrument having special electrical modifica-
tion will include an insert sheetdescribing thatmodi-
fication. If a change sheet or special information sheet
is missing, the information can be supplied by any
Hewlett-Packard sales and service office listed at the
back of this manual.
I.9. INSTALLATION AND OPERATION,
1-10. Installation and operation procedures are
covered in Sections tr and III of the Modet 5245L Op-
erating Manual. An explanation of the Counterts con-
trols and connectors and a self-check procedure is
included in SectionVI of this manual (see Figures 6-1,
6-2, and 6-3).
02349-1 1-1

FREQUENC Y MEASUREMENTS
Range: 0 to 50 MHz (dc input). 25 Hzto 50 MHz
(ac input, maximum sensitivity).
Gate Time: l prsec to l0seconds indecade steps.
Accuracy: r 1 count r time base accuracy
Reads In: kllz or MHz with positioned decimal
point; units annunciator in line with digital
display.
Self Check: counts 10 MHz for the gate time
chosen by the time base selector switch.
SCALING
Frequency Range: 0 to 50 MHz.
Factor: by decades up to 109, switch selected
on rear panel.
Input: front panel, Signal Input.
Output: in place of time base output f requencies.
PE RIOD AVERAGE MEASUREMENTS
Range: Single Period 0 to 1 MHz
Multiple Period 0 to 300 kHz
Periods Averaged: 1 period to 105 periods in
decade steps.
Accuracy: t 1 count t time base accuracy r
trigger error. *
Frequency Counted:
1 and 10 period lKz to 10 MHz indecade steps
100 period . 10 Hz to 10 MHz
1, 000 period. 100 Hz to 10 MHz
10, 000 period 1 kHz to 10 MHz
100, 000 period 10 t<IIz to 10 MHz
Reads In: sec, ms, ps, with positioned decimal
point; units annunciator in line with digitaf
display.
SeIf Check: Gate time is 10ps to1 sec (periods
averagedof 100 kHz); counts 100 kHzfromthe
time base.
RATIO MEASUREMENTS
Displays: (ft/tZ) times period multiplier.
Range: f1 - 0 to 50 MHz. fZ - 0 to 1 MHz in
single period. 0 to 300 kHz in multiple period;
periodi averaged 1 to 105 in decade steps.
Sensltivity: 0. 1 v rms, each input.
xTrigger erroris less than +0.370of oneperiod ; periods
averaged for signals rvith40db or better signal-to-noise
ratio.
r* After 72 hours of continuous operation.
Accuracy: + 1 count 9f f1 r trigger error* of fr.
f1 is frequency applied to the decimal countels
(enters Time Base Ext. jack on front panel);
f.2 is frequency applied to decade dividers
(enters Signal Input jack).
Reads In: Dimensionless; positioned decimal
point for number of periods averaged.
SeIf Check: Period Average Setf Check applies.
TIME BASE
Frequency (internal): 1 MHz.
Stability: Aging Rate - less than 3 parts in 109
per 24 hours. r* As a Fupction of Temperature:
lessthan 12 parts in 1010/'C -20'C to +55"C"
As a Function of Line Voltage: Iess than + 5
parts in 1010 for +!\Vs change in line voltage
from 115v or 230 v rms.
Short Term - less than 2 parts in 1010 ,*,
withmeasurement averaging timeof one sec-
ond under constant environmental and line
voltage conditions.
Adjustment: Fine frequency adjustment (range
approximatety 4 parts in 108) and medium
frequency a{justment (range approximately
1 part in 10o) are available from the front
panel through the plug-in hole. Coarse fre-
quencJ adjustment (range approximately 1 part
in 100) is available at the rear of the instru-
ment.
Output Frequencies:
Rear Panel: 0. 1 Hz to 10 MHz in decade
steps; switch selected on rear panel; all fre-
quencies available in manual function without
interruption at reset except 100 Hz, l0 Hz, 1
Hz, and 0" I Hz which are interrupted by
manual reset; 10 kHz to 10 MHz available
continuously in a1l functions; 1 kHz available
continuously for all functions except 100K
period average; stability same as internal time
base; 5 volts p-p rectangular wave with 1000
ohm source impedance at 1 MHz and lower; 1
volt rms sine wavewith 1000 ohm source im-
pedance only at 10 MHz.
Front Panel: 0.1H2 to l MHz in decade steps;
selected by Time Base switch; availability as
defined under Output Frequencies above; sta-
bility same as internal time base; I v p-to-p.
External Standard Frequency: 1 MHz, 1 volt,
rms, into 1000 ohms required at rear panel
BNC connector.
GENERAL
Registrqtion: 8 digits in-line with rectangular
NixieQ tubes and display storage; 99,999, 999
maximum display; total width of B digit display
including illuminated units annunciator and
auto-positioned decimal point indication does
not exceed ? inches.
Section I
Table 1-1 Model 5245L
Table 1-1. Specifications
r-2 02349-1

Model 5245L
02349-1
o5245 -A-5
Section I
Table 1-1
Table 1-1. Specifications (cont'd)
GENERAL (continued)
Display Storage : Holds reading between samples;
switch overrides storage.
Sample Rate: Time following a gate closing dur-
ingwhichthe gate maynot be reopenedis con-
tinuously variable fromless than 0. 2 sec to 5
seconds infrequency mode, independent of gate
time; display can be held indefinitely.
Operating Temperature Range: -20'Cto +65'C.
Connectors: BNC type except for BCD output
and power cable.
Signal Input:
Maximum Sensitivity - 100 mv rms.
Attenuation - Step attenuator provides ranges
of 0. 1, l, and 10 volts rms.
Trigger Level Adjustment - Front panel con-
trol has + 0. 3 volt trigger level range on 0. 1
volt position, r 3 volt range on 1 volt posi-
tion, and t 30 volt range on 10 volt position.
A preset po s it ion automatically centers
trigger level at zero volts for all positions
of attenuator.
Impedance - 1 megohm in parallel with approx-
imately 25 pf, aII ranges.
Coupling - ac ordc, separate BNC connectors.
AC coupling has 600 vdc, 0.022 g,f capacitor
(-3 dB at approximately 7 Hz).
Overload Protection - Diode clamps protect
input circuit for up to 120 volts rms on 0. 1
volt range, 250 volts rms on 1 volt range,
and 500 volts rms on 10 volt range. hrput
resistance under overload conditions (ap-
proximately tentimes minimum sensitivity)
will be greater than 100K ohms on 0. 1 volt
range, and approximately l megohm on
other ranges.
Time Base External Input (Front Panel):
Maximum Sensitivity - 100 mv, rms.
Impedance - 10K ohms, approximately 20 pf.
DC coupled.
Overload - Diode clamps protect input circuit
for up to 120 volts, rms.
Output:
4-line BCD L-2-2-4, r?lr? state positive. 4-
Iine BCD L-2-4-8, available as Option 02
("1" state positive) and Option 03 ("1" state
negative).
"0" State Level: -Bv.
"1." State Level: +18v.
Impedance - 100K, each line.
Ref erence Levels:
Approximately +L7v, 350 ohm source.
Approximately -6. 5v, 1000 ohm source.
Output is suitable for systems use or output
devices such as 6g Model 580A and 5B1A
Digital-to-Analog Converters and includes
the decimal point and measurementunit for
@ slZe. Digital Recorder.
Print Command - +13v to 0v step, dc-coupled.
Cable Connector - Amphenol 50-pin 57-30500,
1 required.
Hold-off Requirement - +15v min., +25v max.
from chassis ground (1000 ohm source).
Weight - Net 32 lbs (L4,4 kg)with blank plug-in;
shipping, 40 lbs (18,2 kg).
Power Supply - 115 or 230 volts +l}Vo, 50 to 60
Hz; 95 watts (50 to 1000 Hz operation, special
order).
Accessories Furnished -@ fOSOgACable, 4 feet
Iong, male BNC connectors. Detachable
power cord, 7-l/2 ft (2040 mm) long, NEMA
plug. Circuit Board Extender.
Dimensions:
rcTES
drfisroi3 n rrcH8 u0 tHrLLrrcrtis)
irt,rrrx*crrr,rcrro q__
- .il c.arrt *'er{ rcluDrlc rrrr,rDD I (a) rc
crr uk *rcNt
@ ra cn rrcss
OPTIONAL AND SPECIAL FEATURES
Option 02: 4-Iine BCD l-2-4-8, "1" state posi-
tive in lieu of L-2-2-4 (identical in other re-
spects to above Output data) for digits only.
Option 03: 4-Iine BCD L-2-4-8, "1" state nega-
tive in lieu of t-2-2-4 (identical in other re-
spects to above Output data) for digits only.
Remote Operation: AII functions which may be
programmed from the front panel controls
(in normal use) may be programmed from a
remote location except for the "Sample Rate"
(as defined above) and the sensitivity control
setting. The instrument provides (through
rear panel connectors)all voltages necessary
for remote control. The programming volt-
ages for Time Base and Function control are
Iow level, -15 volts dc at 5 ma per gate. Con-
trol may also be achieved by using an external
-15 volt dc supply. The position of the deci-
mal point andmeasurements unit maybecor-
rectly illuminated from the remote location,
using +1?0 volts dc from the internal or an
external supply.
Cable Connector: Amphenol 36-pin 57-30360,
2 required.
-f.- relr.z:+--]
1-3

Model 5245L Section fI
Paragraphs 2-1 to 2-10
sEcTtoN il
PRINCIPTES OF OPERATION
2.I. INTRODUCTION.
2-2. This section describes horv the Model 5245L
operates. Basic circuitsused in the counter are des-
cribed first (Paragraphs %3 through 2 -24). Operation
of decimal counters and decade dividers is thoroughly
discussed in Paragraphs 2-25 through 2-35. A dis-
cussionof basic counter functions isgiven next(Para-
graphs 2-36 through 2-43). Pulse timing circuits and
overall operation of the entire counter are discussed
in Paragraphs 2-44 through 2-50. At the end of the
section each assembly is described in order of its
assembly designation (A ) (Paragraphs 2-51 through
2-L22. ) -
2-3. THE DIODE.
2-4. GENERAL. Semiconductor diodes are used in
signal-handling circuits and in pover supply rectifier
and regulator circuits.
2-5. THE "OR" GATE. TVo or more diodes are
sometimes used as an OR gate. The OR gate is a
multiple-input circuit which requires only one input
to produce an output. Figure 2-1A shorvs some OR
gate configurations.
2-6. THE "AI.ID" GATE. The AI.ID gate or coincidence
circuit is a multiple-input circuit which requires the
presence of all input signals to produce an output.
Figure 2-18 shows anANDgate configuration in which
an input signal is passed only when a properly polar-
ized control voltage is applied.
2-7. THE "INHIBII" GATE. The signal normally
passes through an INHIBIT gate; adding a second signal
closes the gate and prevents the signal from going
through. One of the most common forms of the IN-
IIIBIT gate is the series gate shown in Figure z-LC.
If thediode is biased offrthe gate is closed, and pulses
do not reach the decade divider or decimal counterl
when the diode is biased on, the pulses go through the
gate and reach the decade divider or decimal counter.
2-8. LIMITER OR CLIPPER. The limiter or clipper
is a circuit which removes positive or negative peaks
of waveforms. It can be used either as a waveform
shaping circuit or as a protective device to prevent
excessive voltages from reaching a sensitive circuit.
Figure 2-1D shonrs a limiterwhich prevents the nega-
tive peak of a pulse from going more negative than
about -0. 6 volt. Note that for a conducting silicon
diode the cathode voltage is about 0.6 to 0.8 volt more
negative than the anode.
2-9. CLAIVIPER OR DC RESTORER. The clamper or
DC restorer is a circuit which establishes either the
positive ornegative peakof awaveformat a particular
DC reference voltagel in other words, it provides a
definite baseline voltage f or the wavef orm. Figure 2-1E
shols a clamper which provides a baseline of about
+20 volts for a negative pulse.
02349-1
2-10, REGULATOR. A diode regulator uses either
the constant reverse-bias breakdonrn voltage charac-
teristic of a breakdown diodeorthe constant fonpard-
bias voltage drop characteristic of a silicon diode.
Power supply reference voltages are generally pro-
vided by breakdorpn diodes which maintain a constant
voltage when supplied with a reverse-bias voltage
greater than their specified breakdorpn voltage. Regu-
Iated voltages can also be provided by a fonvard-
biased silicon diode which maintains a constant 0.6 to
0.8volt drop. Figure 2-1F shorps connections forboth
types of diodes.
A. "Or" Gate
D- B. "And" Gatg +C. "lnhibit" Gate s_
D. Limiter E. Clampel +2oV
-v (> -0.8v) -v (>-s6v)
REGULATED } REGULATED
ry-s6v
-o.8v
F. Regulator
Figure 2-1. Basic Diode Circuits
2-L

Section fI
Paragraphs 2-11 to 2-18
2-II. THE TRANSISTOR.
2-t2. GENERAL. Transistors are used throughout
the counter in circuit configurations such as the ampli-
fier, the flip-flop or binary, the trigger circuit, and
the one-shot multivibrator, Irl the folqu/ing para-
graphs, basic transistor operation and a few basic
transistor circuits are discussed. These paragraphs
discuss the easily observed changes in currents and
voltages in transistor circuits which help technicians
Iocate circuit faults butdo not attempt todescribe horv
transistors work internally.
2-13. BIASING AI.{D CONDUCTION. VACUUM tUbCS
and transistors are functionally similar. Irr the tube
a small grid-to-cathode voltage controls a larger
plate-to-cathode current flow. In a transistor a small
base-to-emitter current controls a large collector-to-
emitter current. A comparison of basic vacuum tube,
NPN transistor, and PNP transistor operation is
shown in Figure 2-2A; indicated current represents
conventional florv of positive charges external to the
transistor and is not intended to indicate florp of car-
riers inside the transistor structure. Notice that ilre
effect of emitter-base-collector voltages is totally
reversed between NPN and PNp transistorsl circuits
which are arranged for an NpN transistor usually func-
tion normally for a PNP transistor if supply voltages
are reversed.
2-t4. AMPLIFIERS. As witl vacuum tubes, three
basic amplifier types are available (figure-Z-2l) ,
These amplifiers maybe used alone orin combination
to form complex circuits.
2-15. FLIP-FLOP. The flip-flop is a bi-stabte two-
transistor circuit in which one transistor conducts,
holding the other cut off. Each input pulse causes a
reversal of states; that is, the cut off transistor is
turned on and the conducting transistor is cut off. In
the flip-flop shorrn in Figure 2-gA, e1 is initially con-
ducting heavily; its collector voltage is only slightly
negativel a near-zero voltage is supplied to the base
of Q2 (junction of R2?-28 divider). -ine voltage drop
across R24 produces a sufficienily negative voltage
at the emitter of Q2 to hold e2 cut off. With e2 cut
off the R18-R19-R20 divider delivers a negative volt-
age to the base of Q1 to keep it conducting.
2-16. At time t1 the positive input pulsecutsoff el;
the Q1 collector voltage goes negative and drives ez
into conduction (R2?-R2B divider to e2 base); the e2
collector voltage and the Ql base voltage (R1g-R20
divider) then become considerably less negative, per-
mitting Q1 to remain cut off. The R26-R2?-R2B
divider delivers a sufficiently negative voltage to the
base of Q2 to drive it into conduction. In a similar
manner the positive input pulse at time t2 cuts off e2
and starts a sequence of events which 6nds with el
conducting and Q2 cut off. Note that a positive input
pulse has no effect on Ql if it is already cut off. A
negative reset pulse applied to the base of et returns
the flip-flop to its initial condition (e1 conducting, e2
cutoff). The diode CRg removes the negative pulse
from the differentiated square wave input. Wilhout
this diode, the negative pulse would drive el which
is cut off and the stage would switch from one state
2-2
Model 5245L
Figure 2-2. Transistor Operation
to the other but would not divide by two. The AC
coupling through C2 and C3 insures fast switching.
The DC coupling through R1g and R2? insures bi-
stable characteristics.
2-L7. BINARY CIRCUIT. In this manual a flip,flop
which completes its operating cycle and produces an
output pulse after receipt of two similar input pulses
is called a binary circuit, since it is a counting device
in a binary system. The binary circuit is driven from
a single inputwhich is connectedeither through a pair
of resistors or through a pairof gating diodes toeach
transistor base.
2-18. TRIGGER CIRCUIT. The trigger circuit is a
limiter or squaring circuit which produces an output
waveform with very fast rise and fall times. The
02349-1
ooooo-c-36
A. Amplifier Characteristics
SHARACTERISTIC COMMON
BASE COMMON
EMITTER COMMON
COLLECTOR
lnpul lmpedonce
Oulpul lmpedonce
Volloge Goin
Currenl Goin
Power Goin
300-50J)
300Ko-500Ko
500- 1500
<t
20dB-30d8
5000-1500J}
30KO-50KO
300-tooo
25-50
25dB-40d8
20K0-500Ko
500-loooo
<l
2s-50
todB-20d8
(Emitler Follower)
B. Transistor Biasing
TYPE CUTOFF CONDUCTION
NPN
COLLECTOR
,orr.d
\5/
EMITTER
+v
.,df.Ht^,,
comnoNtl\ ,/
CURRENT \-YL
PNP
COLLECTOR
,O"Q
EMITTER
-V
I
,-^6
lggg$'\y'uarr,r
I CURRENT
r/7

A. Flip-Flop
Rr8
-V
R20
fr tz
i.l_r
=*rt
|NPUT 'ci
RESET R23
(TURNS ON OI)
B.Trigger Circuit
G. One-Shot Multivibrator
NOTE:
l= INITIALLY CONDUCTING TRANSISTOR
tNPUr /'
tr tz
{v{"
Model 5245L
Figure 2-3. Basic Transistor Circuits
02349-1
ooooo- c-35
Section II
Paragraphs 2-19 to Z-24
trigger circuit is similar to the flip-flop except that
the RC network in one half is replaced by the input
signal. Capacitor Cl bypasses R3 to couple fast
changes in voltage at the Q1 collector to the base of
Q2. Either Q1 or Q2 can conduct depending on the
voltage at the input. Note that there is a slight dif-
ference in input voltage (called hysteresis) between
switching with a negative-going input (time t1) and
switching with a positive-going input (time t):
2-19. ONE-SHOT MULTIVIBRATOR. The one-shot
multivibrator is a circuit which generates a pulse of
some specified duration following the application of
a suitable triggering pulse. The circuit is similar to
the flip-flop except one DC coupling path has been
removed so the circuit is stable only in the state with
Ql conducting.
2-20. In the typical one-shot multivibrator shown in
Figure 2-3C the following conditions exist during the
initial stable period: the R5-R6 divider delivers a
sufficientlynegative potential tothe base of Q1 to hold
Ql in saturation; the Q1 collector and Q1 emitter are
therefore slightly negative; the R3-R4 divider delivers
the Q2 base an even smaller negative voltage to hold
Q2 cut off.
2-2L. Thepositivetriggering pulse at timetl reduces
conduction of Q1; the resulting negative-going voltage
at the Q1 collector is applied to the Q2 base through
the R3-R4 divider (C2 bypasses R3 to provide coupling
for the rapidly changing voltage at the Q1 collector);
Q2 begins to conduct; the resulting positive-going
change in Q2 collector voltage is coupled through C3
to the Q1 base to further decrease Q1 conduction. The
process is regenerative and quickly results in Q1 being
cut off and Q2 being saturated.
2-22. Capacitor C3 now charges at a rate mainly
determined by the values of R6 and C3 (main charge
path: R1-Q2-C3-R5). When the Q1 base voltage be-
comes sufficiently negative, Q1 begins conduction;
the resulting positive-going Q1 collector voltage is
coupled to the Q2 base; the Q2 collector voltage goes
negative and is coupled through C3 to the Q1 base to
further increase Q1 conduction. The process is re-
generative and ends with the circuit in its original
quiescent state, Ql saturated and Q2 cut off.
2-23. FIELD EFFECT TRANSISTOR (FET). Field
effect transistors have three terminals: source,
drain, and gate which correspond in function to emit-
ter, collector, and base of junction transistors.
Source and drain leads are attached to the same block
(channel) of N or P semiconductor material. A band
of oppositely doped material around the channel (be-
tween the source and drain leads) is connected to the
gate lead.
2-24. In normal FET operation, the gate-source
voltage reverse-biases the PN junction, causing an
electric freld that creates a depletion region in the
source-drain channel. In the depletion region the
number of available current carriers is reduced as
the reverse-biasing voltage increases, making source-
2-3

Section II
Paragraphs 2-25 to 2-28
drain current a function of gate-source voltage. With
the input (gate-source) circuit reverse-biased, the
FET presents a high impedance to its signal sources
(as compared with the low impedance of the forward-
biased junction transistor base-emitter circuit). Be-
cause there is no input current, FETrs have less
noise than junction transistors. Figure 2-4 shows'
the schematic symbol and biasing for N channel and
P channel field effect transistors.
Figure 2-4. Field Effect Transistor Operation
2-25. BASIC OPERATION OF DEGIIIAT
COUNTER OR DECADE DIYIDER
2-26. INTRODUCTION. Operation of the decimal
counter circuit and the decade divider circuit is simi-
Iar. The difference between the two is in function.
Decimal counter circuits divide the input signal by 10
and actuate the digital display tubes, whereas the
decade divider circuits are used to divide the input
2-4
Model 5245L
signal or the output of the internal oscillator into the
frequencies to be counted or frequencies to provide
the various gate times. Throughout the following dis-
cussion, circuits are referred to as "counters"though
the description applies equally to decade dividers.
Paragraphs 2-25 through 2-29 cover general opera-
tion of the counters with emphasis on counting logic;
Paragraphs 2-30 through 2-32 discuss readout cir-
cuits; and Paragraphs 2-73 through 2-86 discuss
specific decimal counter assemblies and the readout
assembly.
2-27.INPUT ANDOUTPUT FROM BINARY. Figures
2'5Aand 2-5B show a flip-flop connected for operation
as a binary circuit (basic flip-flop operation is dis-
cussed in Paragraphs 2-15 and 2-16). Positive input
pulses go to the bases of both transistors and cause
switching by cutting off the conducting transistor.
Negative reset pulses go to the base of onetransistor
and turn it on. Note the letter "A" near one transis-
tor and "4" (read as "A bar" or "not A") near the
other._ The positive-going transition at the collector
of the A transistor (while switching from A conducting
to A conducting) provides the input to the next binary
circuit.
2.28. CIRCUIT ARRANGE MENT AND COUNT
NOTATION. Figure z-SC is a block diagram of a
blnicat four-binary decimal counter. Notice that the
B output i_s applied to the D, D, and C transistors and
that the D output is applied only to the C transistor.
Each input pulse produces a different combination of
conducting and cut-off stages;there are only 10 allow-
able combinations and each combination represents a
decimal digit, Decimal weighting is the decimal value
assigned, arbitrarily, to the output of a pair when the
plain-Ietter transistor is conducting.
a. Decimal Count. Decimal weighting used in the
Model 5245L counter is shorvn in Figure 2-5C,
immediately above each of the four binary stages.
The decimal weight each pair represents is present
only when the plain-letter side (A, Br I, jr _9) is
conducting; when the barred-Ietter side (A, B, D, or
C) is conducting, the decimal weight is zero. The
decimal count can be determined by adding the deci-
mal weighting of the four stages. For example, if the
4, B, D, andC transistors are conductingrwhereA=1,
B = 0r D = 4t C = 2t the output is 1 + 0 + 4 + 2 = 1.
b. Binary-coded Decimals. In binary-coded deci-
mal notation, the output is either 1 (when the plain-
Ietter transistor is conducting) or 0 (when the barred-
Ietter transiqtor is conducting). In binary-coded
decimal notation, the order of the binaries is given
so that binary-coded decimals can be written with the
least significant digit to the right. Thus in the system
used in the Model 5245L, the binary-coded decimal
notation normally is given in the order DCBA. (Coun-
ter binaries are shown intheABDCorderonthe
schematics and in Figure 2-5C to increase clarity in
shoring signal florv.) For the decimal count of 7 used
as anexatopte inParagraph arwith D = 1r C = 1rE = 0,
A = 1, the binary-coded-decimalnumberwould be 1101.
02349-1
ooooo-c-39
A. FET Amplifier Characteristics
CHARACTERISTIC COMMON SOURCE COMMON DRAIN
(Source Follower )
inpul lmpedonce
Outpul lmpedonce
Voltoge Goin
Power Goin
lMo-t5Mo
50KO-TOOKO
r0- 200
60dB- toodB
lMo-l5Mo
lKo-roKo
<l
40dB-80d8
B. FET Biasing
TYPE
N-CHANNEL
DRAIN
GATE
G
o
CONTROL
VOLTAGE
MAXIMUM
CURRENT
FLOW
INCREASING DECREASES
CURRENT
FLOW
CONTROL
VOLTAGE
I
o
CONTROL
VOLTAGE
MAXIMUM
CURRENT
FLOW
INCREASING DECREASES
CURRENT
FLOW
CONTROL
VOLTAGE

Model 5245L
2-29. SEQUENCE. Figure 2-6 shows the counting
sequence for atypical decimal counter. Initially each
binary is in the 'rOt' (reset) state (decimal count = 0,
DCBA = 0000). The following action takes place when
a series of input pulses is applied to the counter.
a. The first pulse switches A to the 'r1't state
(DCBA = 0001 = 0 + 0 + 0 + 1 = 1).
b. The second pulse switches A to the 'r0t' state;
the output from A causes B to switch to the "1" state
(DCBA = 0010 = 0 + 0 +2 + 0 = 2).
c. The third pulse switches A to the "1" state
(ocee = 0011 = 0 + 0 +2 + 1= 3).
d. The fourth pulse switches A to the "0" state; the
output from A switches B to the "0" state; the output
from B switches both D and C to the "1" state; the
resulting signal fromCis apptied toBand D to return
B tothe "1" state and D tothett0" state (DCBA =0110).
Although D is connected to C, no switching occurs at
C as a result of the final switching of D since C has
not fully recovered from its recent switching.
e. The fifth pulse switches A to the rr1'' state
(ocga = 0111 = 0 +2 + 2 + l= b).
f. The sixth pulse switches A to the r'0" state; the
output from A switches B to the "0" state; the output
from B switches D to the "1" state (DCBA = 1100 =
4+2+0+0=6).
g. The seventh pulse switches A to the "1" state
(ocga = 1101 = 4 + 2 + 0+ 1 = ?).
h. The eighth pulse switchesA tothe "0" state; the
output from A switches B to the " 1" state (OCBA =
1110=4+2+2+0=8).
i. The ninth pulse switches A to the r'1't state
(DCBA = 1111 = 4 + 2 +2 + 1 = g).
j. The tenth pulse switches A to the "0" state; the
output from A switches B to the 't0rr state; the output
from B switches D to the 'r0" state; the output from D
switches C to the ,'0,' state (DCBA = 0000). When C
becomes "0", e produces an outputpulsewhich serves
as a carrypulse to afollowingdecimal counter assem-
bly. The counter is now returned to its original count.
2-30. RESETTING TO ZERO. The reset pulse,
(negative) is applied to the base of the "0" state tran-
sistors @, B, D, e) in each binary circuit. If the
''0'r state transistor is conducting, the pulse has no
effect; if the "0" state transistor is not conducting,
the pulse turns it on. Thus the reset pulse ensures
that all f our "0" state transistors are conducting.
Figure 2-? indicates a decimal counter assembly re-
ceiving a reset pulse. The counter is in the decimal
"4" state (OCgA 0110)and the reset pulse returns the
decimal counter assembly to the decimal "0" state
(OCee 0000). Decade dividers can be reset as re-
quired to any desired state, since reset inputs are
available at each transistor. Note the difference be-
tween a regular inputpulse anda reset pulse: a regu-
lar input signal is positive, and causes a conducting
transistor to cut off; a reset pulse is negative, and
causes a cut-off transistor to conduct.
02349-1
Section tr
Paragraphs 2-29 to 2-30
A. BINARY CIRCUIT
A
OUTPUT
O-r ?
3sv-l I
RESET
+
TURNS ON
ol
INPUT + l5V-r
o--J\-
CUTS OFF THE
CONDUCTING
TRANSISTOR
I = CONDUCTING
TRANSISTOR
AFTER RESET
B. EQUIVALENT BLOCK FOR BINARY CIRCUIT
INPUT
-JL
C. COUNTER BLOCK DIAGRAM
/- BCD WEIGHTING FACTOR-r
t242
INPUT
FEEDBACK
Figure 2-5. Basic Four Binary Counter
2-5

Section fI
Figure 2 -6 Model 5245L
02 349 -1
o5212 -C-l
2-6
DECIMAL
COUNT
o
I
2
3
5
6
7
I
9
o
WEIGHTING
A=l I B=2 I D=4
COUNTER STATE
(l coNoucloN )4-LINE CODE
o
o
o
o
tlt
I
o
o
I
I
o
rlt
oto
mlEElm
g]lEElEE
IEE
EE
C=?
EE
EE
EE
EE
E
E
r
E
rI
0
0
o
o
o
I
o
I
o
o
l
EE
]H o
I
I
I
o
I
o
l
o
Figure 2 -6. Counting Sequence of Four Binary Counter

Table 2-1. Four-Line Code Truth Table
Digit 4-Line code, | = ilBgftlT"" Sfftrf
DcBA
0
1
2
3
4
5
6
1
8
I
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
Model 5245L
2-31. Waveforms showing time relationships for the
counter are given in Section VII; remember that a
driven binary switches only when the input wave is
going positive. (Diode clipping removes negative por-
tion of input).
2-32. ELECTRICAL READOUT. A four-line binary-
coded-decimal output is available from each decimal
counter assembly. A voltage representing the state
of each binary is taken from the collector of each of
the plain-Iettered transistors (A, B, C, and D). A
binary "9" is represented by a relativelypositive volt-
age on each line, and a binary "0" is represented by
a relatively negative voltage on each line. Table 2-1
summarizes the ten allowable combinations which
represent the decimal digits "0" through "9". To
protect the binary circuit from being affected by the
load, each output line includes a 100K ohm series-
connected isolation resistor.
Section II
Paragraphs 2-31 to 2-35
(several megohms)when dark and a relativelylow re-
sistance element (less than ?000 ohms) when illumin-
ated. Thus when the three photocell elements which
constitute a circuit path are illuminated, resistance
drops to about 201000 ohms and sufficient current can
florv to light the display digit. Illuminating elements
forthe photocells are neon lamps, one of which is con-
nected in the collector circuit of each of the eight
transistors in the counting circuit; the lamp lights
when the transistor conducts. As explained in Para-
graph 2.-30, a four-binary counting circuit has ten
states, ten combinations of conducting and noneonduct-
ing transistors, each combination corresponding to
one digit. Thus there is a pattern of lighted lamps
for each digit. Assigrring a binary weight of 1 when
the plain-letter lamp (A, B, Cr oJ D) Iighls, and a
weight of 0 when the bar lamp (4, E, e, or D) tigtrts,
the lamp pattern for any digit can be determined from
Table 2-1. Figure ?-9 shows the countingcircuit with
transistors D, C, -B, A conducting. The lamps as-
sociated with these circuits illuminate the photocell
elements in the circuit to the digit 0 display.
2-35. The circuit sequence required to light a lamp
is discussed in the following paragraphs. The sequence
discussed will have more meaning if itis remembered
1) that a much highervoltageisrequiredto fire a neon
Iamp than to maintain illumination in the lamp (for the
lamps used in the Model 5245L, ?0 volts for firing
and 55 volts for maintaining illumination), and 2) that
after application of the firing voltage the lamp cannot
fire immediately because of the time required for
ionization. Arrangement of the binary lamp circuit
used in the Model 5245L is indicated in Figure 2-88.
As will be discussed later, diodes connected between
the lamps make it possible for the circuit to store a
previous count even though the binaries are switching
during the next counting period. In decimal counter
assemblies which do not have this storage feature,
the display changes with each step the binaries take
in setting up the circuit for a given digit. To clarify
certain aspects of the lamp circuit sequence, the lamp
circuit wiII first be discussed as thoughtherewere no
diodes between the two lamps of a binary; this circuit
is shown in Figure 2-8A.
a. Lamp Circuit without Diodes.
(1) As indicated in Figure 2-8A-1, the lamp
associated with the conducting transistor is
2-33. DIGITAL DISPLAY. A display matrix, con-
sisting of eight neon input lamps and 18 photoconductive
elements is used to convert the binary-coded-repre-
sentation to a digital representation. The display
matrix is shown in the Decimal Counter schematics,
Figures 7-9, 7-ll, and ?-14.
2-34. As indicated in the schematic diagrams, Fig-
ures 7-9, ?-Ll, andT-L4, the circuit to each nu-
meral in the display is brought through three series-
connected photocell elements. A characteristic of the
photocell element is that it is a high resistance element
02349- 1
o5212-B-3
COUNT OF 4
RESET TO
ZERO EEET
Figure 2-?. Typical Reset Operation in Four-Binary Decimal Counter Assembly
2-7

A. WITHOUT STORAGE
I. RUNNING STATE WITH
TRANSISTOR A CONDUCT-
tNG, LA!|P A FtRED,
LAMP A EXTINGUISHED.
- t30v
2. LAMP-S CHANGE STATE,
LAMP A FIRED, LAMP A
EXTINGUISHED.
INSUFFICIENT
VOTTAGE TO.
FIRE LAMP A
390K
-48V
a
38V
\
-tov
- rov
B. WITH STORAGE
I. STORAGL
TRANSISTOR A CONDUCTING.
BUT LAMP A CANNOT FIRE:
unue E oru, tRnrusrsron A
NOT CONDUCTING.
2. TRANSFER BEGINS
CONDITIONS DURING
INITIAL PERIOD OF
TRANSFER PULSE
3. TRANSFER COMPLETE
CONDITIONS DURING
FINAL PERIOD OF
TRANSFER PULSE
LAMP A
CANNOT
FIRE
luaup E
REMAINS ON
J
MOMENTARY RISE
IN VOLTAGE WHILE
LAMP A IONIZES
\ _,uu
LAMP A
REMAINS
ON UNTIL
LAMP A
FIRES
,l
LAMP A IS
loNlzlNG 1
-t8v
-8V
NOTE: LAMP VOLTAGES,TYP: FIRES
LAMP AT 7OV AFTER IONIZATION DROP ACROSS
STABILIZES AT APPROXIMATELY 55V.
-t30v
COLLECTOR
CONNECTION
- l30v
a
55.5V 55V
FORWARD
BIASED
(coNDuc-
TION)
- r30v
'2
92V\+
-r30v
*tRnrusrER PULSE -l r+lgv
35MTLLTSECONDSI l_rov
Section II
Figure 2 -8 Model 5245L
02349 -1
05245-B-9
!
2-8
Figure 2 -8. Lamp Control

Model 5245L
lighted, the lamp associated with the noncon-
ducting transistor is dark. Typically, volt-
ages will be as shown. Since the transistor
associated with the dark lamp is not conduct-
ing, no current is flowing in the circuit of the
dark lamp, and voltage across it is established
(a) by the circuit of the conducting lamp and
its transistor, and (b) by the voltage on the
collector of the non-conducting transistor.
This voltage is not high enough to fire the dark
lamp.
(2) When the binary shown in Figure 2-8A changes
state, the voltage on the collector of transistor
A (now conducting) drops to -10 volts, while the
voltage on the collector of nonconducting
transistor A rises to +19 volts. Withtransis-
tor A turned off, current through lamp A de-
creases, and the voltage at the junction of the
two lamps rises. Since Iamp A cannot fire until
ionized, voltage will continue to rise until the
?0-volt firing level is reached; the junction will
reach approximately ?3 volts during the ioni-
zation period. After the dark lamp fires, the
voltage across it stabilizes at about 55 volts,
and since the voltage across the other lamp is
now reduced to 38 volts, the other lamp
extinguishes.
(3) Circuit state after lamp A has fired is shown
in Figure 2-8A-2; it is the mirror image of
that shown in Figure 2-8A-1.
b. Lamp Circuit with Diodes. The steady, or
stora it is indicated in
Figure 2-88-1. The diodes are forward-biased,
eff ectively connecting the lamps in parallel and clamp-
ing them to approximately -1.5 volts. One lamp is
conducting, the other lamp is dark. Since both lamps
are clamped to -1.5 volts, regardless of the state of
the binary, there will never be sufficient voltage across
the dark tight to fire it and it wiII remain dark until
1) the diodes are reverse-biased and 2) there is con-
duction through the transistor in whose collector cir-
cuit the lamp is connected.
(1) When the gate closes at the completion of the
counting period (see Paragraph 2-95) a -29
volt transfer pulse (see Paragraph 2-99) is
applied to the binary diodes, reverse-biasing
them. With the diodes reverse-biased, the
lamps are disconnected from each other, and
the circuit for each lamp is now completed
through its associated transistor.
(2) If the state of the binary is the same as
that at the end of the previous counting period,
the lamps '(see', the voltages required to
maintain them without change. If, however,
the digit is such that the binary state is
changed, the lamps change state. With the
diodes reverse-biased, circuit action is the
same as that described in subparagraph a.
Condition of the circuit during the initiat
period of the transfer pulse when voltage
across the dark lamp is increasing is indi-
cated in Figure 2-BB-2; circuit condition
after the lamp has fired is indicated in Fig-
ure 2-BB-3.
02349- 1
Section II
Paragraphs 2-36 to 2-40
c. Disabling the Storage. Whenthefunctionselector
is set to MANUAL or theSTORAGE switchon the rear
panel is in the off position, the storage feature is
disabled. Circuit action is then described in sub-
paragraph a.
2-36. BAStC COUNTER FUNCTtONS.
2-37, GENERAL.
a. The basic counter circuits are arranged to pro-
vide several functional modes of operation. Each
arrangement includes a main AND gate with 1) a
signal input and 2) a control input, or gating signal.
Following the maingate is a cascaded series of decimal
counters which accumulate and display the total num-
ber of pulses which pass through the main gate. The
various modes of operation are discussed in Para-
graphs 2-36 through 2-41.
b. Circuit sequence in the various modes of opera-
tion is similar: pulses pass through the main gate to
the decimal counters for a predetermined time, are
counted and displayed. The difference between ar-
rangements is in 1) the source of the pulses counted,
and 2) the source of thegatingsignalwhich establishes
the length of time during which the main gate is open
to pass pulses to the decimal counters.
2-38. TOTALIZING. In the totalizing mode (see
Figure 2-9A), the gate flip-flop is controlled by the
FUNCTION switch when it is in the MANUAL START
or MANUAL STOP positions. The decimal counters
count the total number of input pulses applied while
the main gate is held open with the FUNCTION switch
in the MANUAL START position. SwitchingtheFUNC-
TION switch to the MANUAL STOP position closes the
main gate and the number of pulses which came through
the main gate while it was open are displayed.
2-39. FREQUENCY MEASUREMENT. The circuit
arrangement shown in Figure 2-9B permits control of
the main gate by the counter time base. The gate is
opened for a controlled time, therefore the accumu-
Iated count represents the number of input cycles or
pulses during this time. Controlled intervals are
from 10 seconds down to 1 microsecond in decade sub-
multiples, selectable with the front panel TIME BASE
switch. The decimal point is automatically positioned
and the readout is in kilohertz or megahertz with the
units in line with the digital display.
2-40. PERIOD MEASUREMENT. The arangement
shown in Figure 2-9C provides the meansformeas-
uring the period of the input signal. The period of a
signal is the time required for the completion of one
cyclel the counter displays the time in seconds, milli-
seconds or microseconds. The period measurement
is obtained by making the duration of tfie gating signal
equal to the period of the input signal, and counting a
train of pulses supplied bythe counter time base. The
displayed count is the number of time-base pulses
which occur during one period of the input signal. For
multiple period measurements, Figure 2-9D, the
input signal is divided bythe selected decadefactor so
that the gating signal is the selected multiple of one
2-g