Hytera TETRA User manual

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Contents
Revision History .............................................................................................................................................. 1
Copyright Information..................................................................................................................................... 1
Disclaimer......................................................................................................................................................... 1
Introduction...................................................................................................................................................... 2
Product Controls ............................................................................................................................................. 3
Circuit Description........................................................................................................................................... 4
Tuning Description ........................................................................................................................................ 17
Interface Definition........................................................................................................................................ 18
Troubleshooting Flow Chart......................................................................................................................... 23
Disassembly and Assembly ......................................................................................................................... 43
Exploded View ............................................................................................................................................... 48
Parts List 1...................................................................................................................................................... 50
Packing Guide................................................................................................................................................ 52
PCB View........................................................................................................................................................ 53
Schematic Diagram ....................................................................................................................................... 57
Parts List 2...................................................................................................................................................... 76
Specifications .............................................................................................................................................. 100
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1
Revision History
Version Date Description
V00 08-2011 Initial Release
Copyright Information
Hytera is the trademark or registered trademark of Hytera Communications Co., Ltd. (the Company) in
PRC and/or other countries or areas. The Company retains the ownership of its trademarks and product
names. All other trademarks and/or product names that may be used in this manual are properties of
their respective owners.
The product described in this manual may include the Company’s computer programs stored in memory
or other media. Laws in PRC and/or other countries or areas protect the exclusive rights of the Company
with respect to its computer programs. The purchase of this product shall not be deemed to grant, either
directly or by implication, any rights to the purchaser regarding the Company’s computer programs. Any
of the Company’s computer programs may not be copied, modified, distributed, decompiled, or
reverse-engineered in any manner without the prior written consent of the Company.
Disclaimer
The Company endeavors to achieve the accuracy and completeness of this manual, but no warranty of
accuracy or reliability is given. All the specifications and designs are subject to change without notice
due to continuous technology development. No part of this manual may be copied, modified, translated,
or distributed in any manner without the express written permission of us.
If you have any suggestions or would like to learn more details, please visit our website at:
http://www.hytera.com.
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2
Introduction
Intended User
This manual is intended for use by qualified technicians only.
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Product Controls
No. Part Name No. Part Name
○
1SK1 (programmable) ○ 2PTT Key
○
3SK2 (programmable) ○ 4Emergency Key
○
5LED Indicator ○ 6Antenna
○
7Multi-function Control Knob ○ 8Receiver
○
9Display ○
10 Function Keypad
○
11 Speaker ○ 12 Numeric Keypad
○
13 Light Sensor ○ 14 Battery Latch
○
15 Duplex Microphone ○ 16 Simplex Microphone
○
17 Accessory Jack Cover ○ 18 Accessory Jack
○
19 Strap Hole ○ 20 Belt Clip
○
21 Battery ○
22 Charging Piece
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Circuit Description
1. RF Section
The frequency range for PT580 F5 is 806~870MHz (in TMO mode, the frequency range for TX is
806~825MHz, while the frequency range for RX is 851~870MHz; in DMO mode, the frequency range for
both TX and RX is 851~870MHz). The block diagram for the RF section is shown below.
PA Cartesian
Loop ASIC RX FGU POWER_RF
BB TOP
Figure 1 Diagram of RF Section
The RF section consists of PA module, Cartesian Loop ASIC module, RX module, FGU and power
supply module (POWER_RF).
1.1 TX Circuit
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Cartesian IC
DCMEAS
RF_SCLK
RF_DIN
RF_DOUT
TxI+
TxI-
TxQ+
TxQ-
Tx_LO
3V_Tx
RF_SW
7V5
Antenna
PA
3V6_RF
3V_A
Temperature
Sensor
RF_FB
TMP_ALERT
SDA
SCL
RX
PA_BIAS1
PA_BIAS2
3V_TxA
3V_TxD
attenuator
CSN
DOI
DOQ
RF_FB
Figure 2 Diagram of TX Circuit
The TX circuit consists of PA, harmonic filter, pre-amplifier, duplexer, coupler, temperature sensor,
TX/RX switch, antenna and etc. The working principle of the TX circuit is described below:
The TX circuit sends the I/Q signal from the baseband section to the Cartesian IC, which outputs
800MHz TX signal after appropriate processing. The TX signal goes to the filter and then to the PA circuit
for amplification after it is converted by BALUN.
The PA circuit is to amplify the RF signal output by the Cartesian IC to obtain an appropriate power level.
Then the signal passes through the TX/RX switch and is sent out from the antenna.
The feedback channel is to couple the power output by the main PA to the Cartesian IC, to form a
complete Cartesian loop. In this way, the output power can be controlled via the attenuation of the
feedback loop.
The temperature sensor will give protection signal if the PA temperature is too high. In such case, the
output power of the PA will be decreased appropriately to prevent damage to the parts.
The signal output by the main PA passes through the TX/RX switch and then goes to the antenna. The
TX/RX switch controls the TX/RX status according to the control signal output by the baseband.
The interfaces between the TX circuit and the baseband or other circuits are described below.
(1) TMP_ALERT
This is the alarm output interface of the temperature sensor, and is connected with the baseband. It
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6
outputs low level during normal operation, and outputs high level to notify the baseband to reduce the PA
power if the temperature exceeds the preset level.
(2) PA_BIAS1 (same as PA_BIAS2)
This interface is used by the baseband to set the bias status of the PA. In TX status, the level is 2.47V.
(3) RF_SW
This interface is used to transfer the TX/RX switch signal output by the baseband. In the case of high
level, the antenna switch is connected to the output end of the PA, and the RF signal output by the PA is
sent to the antenna via the antenna switch. In the case of low level, the receiver is on, while the
transmitter is off. The antenna switch is connected to the RX interface.
(4) RX
This interface sends the signal to the RX module when the RF_SW switches to the RX end.
(5) RF_FB
This interface feeds the coupled signal back to the Cartesian IC to control the output power.
(6) Tx I+/- and Tx Q+/-
These interfaces are used to transfer the I/Q differential signals from the modulator. The DC level of the
signals is 1.6V, and Vp-p is 1.3 V.
(7) RF_SCLK/RF_DIN/RF_DOUT/CSN
These interfaces are used to transfer the clock signal, data signal and enable signal from the baseband,
and used by the baseband to program the register.
(8) DCMEAS
This interface is used to transfer the signal sent to the baseband for determining whether the DC
calibration is successful.
(9) TX_LO
The signals generated by the TX 1st LO are sent by the VCO to the Cartesian IC, where they are divided
to TX carrier signals. This interface is used to transfer such TX carrier signals.
1.2 RX Circuit
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TR
LNA IF Amplifier
IF BPF
Mixer
Diplexer
ANT
BPF BPF
Buffer
Demodulator
LPF
LPF
Rx_LO1 Rx_LO2
Rx PLL
IQ Processor
ANT Switch
GPS TX
3V_Rx
RX I+
RX I- RX Q+
RX Q-
AGC
RX
Figure 3 Diagram of RX Circuit
The working principle of the RX circuit is described below:
The RX signals pass through the RF switch. First, they are filtered to remove out-of-band signals. Then
they are amplified by the LNA and filtered again. After that, the signals are sent to the mixer for
appropriate processing. The signals output from the mixer are processed by the IF low-noise amplifier
and then by the IF filter to select desired IF signals for demodulation. The obtained I/Q signals are
filtered and finally sent to the baseband for processing.
The interfaces between the RX circuit and the baseband or other circuits are described below.
(1) 3V_RX
This interface is used to transfer the receiver on/off signal from the baseband. If the signal is at high level,
the receiver is on and the RX channel works.
(2) RX
This interface is used to transfer the RX signal output by the antenna switch of the PA.
(3) RX_LO1
This interface is used to transfer the first RX LO signal output by the VCO.
(4) RX_LO2
This interface is used to transfer the second RX LO signal (level: -10dBm) output by the VCO. The signal
enters the IF demodulator, where it is divided and then demodulated together with the first RX IF signal.
(5) AGC
The AGC control voltage from the baseband enters via this interface, to stabilize output of the I/Q
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demodulator. The AGC voltage varies within 0.2V~1.2V. When the AGC control voltage is 0.2V, the gain
gets to its maximum value.
(6) Rx I+/ - and Rx Q+/-
These interface are used to transfer the differential I/Q signals output by the I/Q demodulator.
1.3 FGU
a1
1
a2
2
3a3
4a4
b1
b2
b3
b4
5
6
7
8
Vcc 1
0
GND
0
PLL IC
12MHz _REF
SYN_ON
SYN_CS
SYNTH _LOCK
Loop Filter RxVCO 2
CPout IF
LOOP Filter TXVCO & RXVCO1
CPout RF
5V_SYN
FLout IF
FLout RF
FinIF
FinRF
Figure 4 Diagram of FGU
The working principle of the FGU is described below:
The reference frequency output by the baseband enters the PLL for frequency division. Meanwhile, the
frequency generated by the VCO goes to the divider for frequency division. Then the signals resulted
from both frequency divisions are sent to the phase detector for phase detection. If the signals have
different frequencies or phases, the phase detector will output a signal corresponding to the phase
difference. The signal goes to the low-pass filter to remove high-order harmonics, so as to control the
oscillation frequency of the VCO.
The interfaces between the FGU and the baseband are described below:
(1) FinRF
This interface is used to transfer the feedback signal from the TX/RX VCO to the PLL.
(2) FinIF
This interface is used to transfer the feedback signal from the RX IF VCO to the PLL.
(3) CPout RF
This interface is used to transfer the charging voltage signal from the PLL to the TX/RX VCO.
(4) CPout IF
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This interface is used to transfer the charging voltage signal from the PLL to the RX IF VCO.
(5) FLout IF
This interface is used to transfer the charging voltage lock signal from the PLL to the RX IF VCO.
(6) FLout RF
This interface is used to transfer the charging voltage lock signal from the PLL to the TX/RX VCO.
(7) SYNTH_LOCK
This interface is used to transfer the PLL lock indication signal to the baseband. When this pin outputs
high level signal, it indicates the PLL is locked.
(8) SYN_ON
This interface is used to transfer the PLL enable signal from the baseband. It outputs 3.3V voltage, and
is open in normal status.
(9) 12MHz_REF
This interface is used to transfer the reference frequency for the PLL.
1.4 VCO
VCO VCO
BP filter
BUFFERBUFFER
TRIPLE
5V SYN _ON
TX LO
RX LO
RVO SWITCH
TVO SWITCH
RX LO OUTPUT
TX LO OUTPUT
Figure 5 Diagram of VCO
The working principle of the VCO is described below:
The PLL outputs the control voltage CV. When the RX VCO is locked, it will be output to the receiver via
the BUFFER. When the TX VCO is locked, it will be output to the receiver via the BUFFER, TRIPLE and
filter. The VCO that is powered up will be locked.
The interfaces between the VCO and the baseband or other circuits are described below.
(1) CV: This interface is used by the PLL to output control voltage.
(2) RVO SWITCH: This interface is used to supply power to the RX VCO.
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(3) TVO SWITCH: This interface is used to supply power to the TX VCO.
(4) RX LO OUTPUT: This interface is used by the RX LO to output signal to the RX mixer.
(5) TX LO OUTPUT: This interface is used by the TX LO to output signal to the Cartesian IC.
1.5 Power Supply Module
3V3D 60R 3V3_RF
LDO
Rx_ON
RF LNA
MIXER
IF LNA
Demodulator
3V_RX
80mA
LDO
Tx_ON
Modulator
3V_TX
140mA
LDO Modulator
PLL IC
LT5509
3V_A
9mA
SYN_ON
LDO 3V_B
100uA
SYN_ON
Tx_ON
Rx_VCO_ON
TX_LO_Buffer
TX_Drive
3V_TXDRV
LO1_Drive
RX LO2_VCO
3V_RVCO
V_PA 60R DC/DC LDO
5V_SYN
RX_VCO_ON
Tx_VCO_ON
RX LO1 VCO
5V_RVCO
TX LO VCO
5V_TVCO
Figure 6 Diagram of Power Supply Module
This module is to supply appropriate voltages to the RF circuits. The 3V3D voltage is supplied by the
power management IC of the baseband section, and passes through different LDOs to supply the
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Cartesian IC, TX VCO, RX VCO, pre-amplifier and other RX parts respectively. The V_PA is supplied by
the battery directly. The SYN control signal is open while the portable terminal is operating.
2. Baseband Section
2.1 Power Section
BATTERY
Farad Battery
Z
Z
ON/OFF
V_PA
VBAT
1V8D
1V6D
2V5D
3V_TXCO
3V3D
3.3V_RF
LDO 1V2D
TO RF PART
TO RF PART
PMU
U6001
Figure 7 Diagram of Power Section
The 3V3D, 1V6D, 1V8D and 3V_TXCO are the necessary voltages for the MCU to start up. The MCU
may not start if any of the four voltages becomes invalid.
The 3V3D, 2V5D, 1V2D and 3V_TXCO are the necessary voltages for the FPGA to start up. The FPGA
may not start if any of the four voltages becomes invalid.
No. Network Test Point Reference Voltage during Start-up (V)
(while running Bootloader)
Reference Voltage
after Start-up (V)
1 VBAT L6004_2 3.6～4.2 3.6～4.2
2 3V3D TP6001 3.3 3.15
3 1V8D TP6002 1.8 1.8
4 1V6D TP6003 1.6 1.35
5 2V5D TP6004 2.5 2.5
6 3V_TXCO TP6005 3 3
7 1V2D TP6006 1.2 1.2
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2.2 Control Section
2.2.1 MCU
CAMERA
LCD（WITH
CONTROL
）
GPIO
16 bit EMIFS
16 bit EMIFF
JTAG
32.768KHz and
12 MHz CLOCK
MCU（ARM+DSP）
UART 1
UART 3
UART 2
MCBSP3
MCBSP2
MCBSP1
I2C
MMC/SD CARD
MPUIO
5* 5 KEY
PWL
SPI
8bit
Reserve
5*5
25 KEY
EMLUATOR
CLOCK
CONTROL
LED and GPIO
LCD and KEY
BACKLED CONTROL
LED
128 Mbit SDRAM
16bit
128Mbit FLASH
16bit
16 bit
PIXEL≤160 * 128 ，
COLOR=262K
RF and LCD etc.
RF etc.
CMD1
CMD2
TX/RX
CHANNEL
CODEC
CONTROL
FPGA FLASH.CS and
GPIO
Reserve
Baseband
Processor
PC
Reserve
Reserve
LCD
Figure 8 Diagram of MCU
The dual-core (ARM+DSP) MCU (main frequency speed of 144MHz) accommodates multiple peripheral
interfaces to directly control the LED, LCD, keys and etc. The serial interfaces contain I2C, SPI, MCBSP
and MCSI.
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2.2.2 FPGA
FPGA
MCU
CODER SWITCH
LCD
SIM CARD
SIM _RST
SIM_CLK
SIM_DATA
SIM_SUPPLY
9. 2 16 M _ FPG A
9.216MHz
9.216M_ VCO_ON
/VCO_UP
VCO_DOWN
12MHz BB.
PROCESSOR
/RST_OUT /RST.OUT
RF
MANOUTX
MANOUTY
Acceleration
Sensor
MEMORY
MCBSP2. FSX
CMX_IRQ2
CMX_ BITCLK
SYMCLOCK
SPI
CONTRAL
I/O
CLK
EMIFS
Figure 9 Diagram of FPGA
The FPGA is mainly for channel control, volume control, sequence control, clock management, IO
expansion control, encryption algorithm and etc.
2.2.3 Memory
The MCU provides two types of external memory interfaces: external memory interface slow (EMIFS)
and external memory interface fast (EMIFF).
MCU U2001
EMIFF EMIFS
SDRAM.A[0:12] FLASH.A[24:1]
SDRAM.D[0:15] FLASH.A[15:0]
SDRAM.BA0
SDRAM.BA1
SDRAM.CAS# FLASH.CS3#
SDRAM.RAS# RST_OUT#
SDRAM.CKE#
SDRAM.CLK#
SDRAM.CS#
SDRAM.WE#
SDRAM.DQML
SDRAM.DQMU
A[0:12]
D[0:15]
BA0
BA1
CAS#
RAS#
CKE
CLK
CS#
WE#
LDQM
ULQM
FLASH U2003
A[23:0]
DQ[15:0]
OE#
WE#
Cef#
RESET#
WP#/ACC
RY/Byf#
FLASH.WP#
FLASH.RDY
FLASH.OE#
FLASH.WE#
SDRAM U2004
Figure 10 Diagram of Memory
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The MCU is connected with a 128Mbits NOR FLASH (for program or data storage) and a 128Mbits
SDRAM (for temporary data storage).
2.2.4 CLOCK
The 32K clock, also called real-time clock (RTC), is used for system starting, timing, sleeping and etc.
The generation of the 9.216MHz clock is controlled by the FPGA. This clock is provided to the baseband
processor.
FPGA
R
9.216_VCO_ON
/VCO_UP
VCO_ DOWN
MCLK
DA +3V_TCXO
12MHz_REF
PLLOSCINIF
RF
12MHz
AFC
Synthesizer
12MHz_CLK
CPU
OSC1_IN
OSC1.IN
1V6D
32.768K
12MHz_CLK
9.216M_FPGA
SIM
SIM_CLK
Cartesian
Loop IC
SCLK
BITCLK
SPI.SCK
MCBSP1_ CLKX
MCBSP2_ CLKX
MCBSP3_ CLKX
9.216M_CLK
CLK32_KIN
CLK
32K_
SYMCLOCK
CMX_ SCLK
SPI.SCK
SCK
CLK
RF
Baseband
Processor
IO_L02P_1/A14
R
Figure 11 Diagram of CLOCK
2.2.5 Reset signal
NOR Flash
PMU /RESET
/RST-OUT
LCD
CODEC
MCU
RESET-CODEC
/RST-OUT
Figure 12 Diagram of Reset Signal
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2.2.6 UART
The MCU has 3 UART interfaces: UART1, UART2 and UART 3. The communication rate can be up to
1.5Mbps. The UART connection is shown in Figure 13. The UART2 interface is connected to the
accessory jack for upgrading and programming, while the UART1 and UART3 interfaces are reserved.
UART_RXD
UART_TXD
UART_RTS
UART_CTS
U2501
PC
Reserve
U2001
UART3.RX
UART3.TX
UART2.RX
UART2.TX
UART1.RX
UART1.TX
MCU
UART3.CTS
UART3.RTS
RXA
TXA
J2502
TXA
RXA J2501
Reserve
Figure 13 Diagram of UART Connection
2.2.7 I2C
The MCU provides one I2C interface for the MCU to control the PMU and RTC.
I2C.SCL
SCL
SDA PMU
SDA
SCL RTC
SDA
SCL
Reserve
U2001
I2C.SDA
MCU
Figure 14 Diagram of I2C Connection
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2.3 Audio Section
MCBSP 1
MCBSP 3
MCBSP 2
FSB3
FSB1
FSB2
RF
CLOCK
IRQ
RESET
IRQ
RESET
CLOCK
MIC1
MIC2
AUD
EAR PA
CODEC
MCU
DSP
I/Q
FPGA
b
Baseband
Processor
Figure 15 Diagram of Audio Processing Circuit
2.3.1 Audio input
The audio signal from the MIC goes to the baseband processor for amplification, A/D conversion,
encoding and filtering. After such processing, the PCM code is generated, and is then sent to the MCU
for voice encoding and channel encoding by the DSP. After that, it is converted to I/Q signal by the
baseband processor via π/4 DQPSK modulation, filtering and D/A conversion. Finally, the I/Q signal is
sent via the antenna after modulation, amplification and filtering.
2.3.2 Audio output
The RF signal passes through the antenna, LNA, mixer, filter, IF amplifier and demodulator. After
demodulation, the I/Q signal is sent to the baseband processor for A/D conversion and filtering, and then
enters the MCU via the serial port. After π/4 DQPSK demodulation, channel decoding, voice decoding
by the MCU, the signal is converted to audio signal by the baseband processor via filtering and D/A
conversion. Then the audio signal goes to the audio amplifier. After amplification, the audio can drive the
speaker (the audio can be heard from an earpiece if the analog switch is connected with the accessory
jack). The signal from the receiver (duplex) is output by the baseband processor directly (not passing
through the audio amplifier).
2.3.3 Audio Amplifier Output
Main parameters are listed in the table below:
Rated Power (Po)1W RL = 4
Ω
Maximum Power (Pmax)1.5W RL = 4
Ω
Note: The terminal adopts the class D amplifiers.
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17
Tuning Description
For details about tuning, please refer to the help file for appropriate tuner software supplied by us.
The test standard for current is described in the table below:
No. Test Item Test Value Test Condition
1 Power-off current Test value≤2mA
2 Mean stand-by current in TMO
(screen off)
140mA≤test value≤170mA
3
Mean stand-by current in DMO
(screen off)
210mA≤test value≤250mA
300mA≤test value≤650mA (the
antenna is connected.)
4
Mean TX current in DMO
(screen off) 300mA≤test value≤650mA (the
50Ωload is connected.)
Test v a lue≤1900mA (the antenna
is connected.)
5
Max. TX current in DMO
(screen off) Tes t v a lue≤1800mA (the 50Ω
load is connected.)
300mA≤test value≤650mA (the
antenna is connected.)
6
Mean TX current in TMO
(screen off) 300mA≤test value≤650mA (the
50Ωload is connected.)
Test v a lue≤1900mA (the antenna
is connected.)
7
Max. TX current in TMO
(screen off) Tes t v a lue≤1800mA (the 50Ω
load is connected.)
The voltage is 3.7V. Test
instrument and software:
Agilent power supply, GPIB
card, computer and current
test software.
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18
Interface Definition
The interfaces on the main board contain those for data, keyboard, side key, LED, receiver, MIC,
speaker motor, encoder switch and etc.
J7001: 70-Pin Interface
Pin No. Name Function Valid Level
69, 70 GND Power supply: ground (analog) L
4
5
UP_MIC+
UP_MIC-
Upper MIC interface -
6
7
LOW-MIC-
LOW-MIC+
Lower MIC interface -
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
LCD data cable -
34, 35 3V3D Power supply: 3.3V H
9
11
USB-D+
USB-D-
Reserved -
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