Ibm 360 User manual

Systems Reference Library

IBM

System/360

Model

30

Operating Guide

File

Number

8360-01

Form

A24-3373-2

This

reference

publication

describes

operator

procedures

for

the

IBM 2030

Processing

Unit

and

the

IBM 1052

Printer

Keyboard

(attached

to

the

IBM

8ystem/360

Model

30).

For

additional

information

for

operation

of

the

various

input/output

devices,

refer

to

the

publications

listed

in

the

IBM

8ystem/360

Bibliography,

Form

A22-6822.

Third

Edition

This

is a

reprint

of

A24-3373-1

incorporating

changes

released

in

the

following

Technical

Newsletter.

Form

Number

Pages

Affected

~

N24-0390

20

December

28,

1966

Significant

changes

or

additions

to

the

specifications

contained

in

this

publication

will

be

reported

in

subsequent

revisions

or

Technical

Newsletters

Copies

of

this

and

other

IBM

publications

can

be

obtained

through

IBM

Branch

Offices.

This

manual

has

been

prepared

by

the

IBM

Systems

Development

Division,

Product

Publications,

Dept.

171,

P. O. Box

6,

Endicott,

New

York

13760

Address

comments

regarding

this

publication

to

this

address.

@)

International

Business

Machines

Corporation

1965

ii

CONTENTS

IBM

SYSTEM/360

MODEL

30

OPERATING

GUIDE

..........................

5

IBM

2030

System

Control

Panel

. . . . . . . . .

..

6

Operator's

Control

Panel

(OC

P).

. . . . .

..

6

Console

Controls.

. . . . . . . . . . . . . . .

..

9

Operation

Controls

. . . . . . . . . . . . . . . .

10

Push

Buttons

.....................

12

Displays

........................

14

Use

Meters

.....................

18

SYSTEM

OPERATIONS

.................

19

System

Power-On

and

Power-Off

.......

19

Program

Load

Routine

. . . . . . . . . . . . . .

19

Dis

play

Information

From

Storage

. . . . . .

20

Store

Information

into

Storage

. . . . . . . . .

20

Single-Instruction

Processing

.........

24

Single-Cycle,

Display,

and

Store

Operations.

. . . . . . . . . . . . . . . . . . . .

24

Processing

a

Program

Section.

. . . . . .

25

Starting

at

a

Specific

Instruction

(Set

IC)

Procedure

..................

25

Manual

Intervention

. . . . . . . . . . . . . . .

27

Microprogram

Test

Routines

.............

27

Basic

Test

......................

27

Display

Read/Write

Storage

...........

27

Alter

Read/Write

Storage

. . . . . . . . . . . .

28

Alter

a

Block

of

Read/Write

Storage

.....

28

IBM 1052

PRINTER-KEYBOARD

..........

29

IBM 1050

OPERATIONS

....

37

EXTENDED

BINARY

-CODED-DECIMAL

INTERCHANGE

CODE

(EBCDIC)

.........

41

GLOSSARY

OF

TERMS

.................

44

INDEX

............................

46

iii

Figure

1.

IBM

System/360

Model

30

with

IBM

1052

Printer

Keyboard

4

IBM

SYSTEM/360

MODEL

30

OPERATING

GUIDE

The

IBM

System/360

Model

30

(Figure

1)

is

a

solid-

state,

high-speed

data

processi~g

system

that

is

compatible

with

the

other

models

of

System/360

as

described

in

IBM

System/360,

Principles

of

Opera-

tion,

Form

A22-6821.

--The

operator

controls

needed

for

normal

program

processing

(turning

power

on

and

off

and

loading

and

starting

a

program)

are

contained

on

the

2030

system

control

panel

(console).

The

IBM 1052

Printer-Key-

board

can

be

added

to

the

system

so

that

communica-

tion

between

the

operator

and

the

system

can

be

documented.

5

IBM

2030

SYSTEM

CONTROL

PANEL

The

IBM

2030

Central

Processing

Unit

is

provided

with

a

number

of

indicators

and

manual

controls

that

permit

operation

of

the

system

in

any

of

several

modes,

and

observation

of

the

results

of

any

opera-

tion.

These

indicators

and

controls

are

assembled

on

a

panel

(Figure

2)

that

serves

as

both

an

operator's

system

control

console

and

an

IBM

Customer

Engi-

neer's

panel.

The

lower

right-hand

portion

of

the

console

is

designated

as

the

Operator's

Control

Panel

(OC

P).

This

section

contains

four

push

but-

tons,

three

16-position

rotary

switches,

and

six

indicators.

Except

for

the

nomenclature

printed

on

the

panel,

the

OCP

is

identical

on

all

CPU's

(Central

Processing

Units)

in

System/360.

The

OCP

contains

all

controls

and

indicators

necessary

for

normal

problem-program

processing.

OPERATOR'S

CONTROL

PANEL

(OCP)

This

section

of

the

2030

console

(lower

right

corner)

has

the

following

controls

and

indicators:

Power-On

Key

The

power-on

sequence

for

the

CPU

and

all

on-line

I/O

units

starts

when

this

key

is

pressed.

A

system

reset

function

occurs.

All

data-flow

registers

(but

not

the

general-[Xlrpose

or

floating-point

registers)

are

reset.

as

are

any

priorities

that

happen

to

turn

on.

The

CPU

clock

is

reset

to

prevent

access

to

storage

so

that

information

in

storage

is

not

dis-

turbed.

Hence,

system

power

can

be

turned

off

and

restored

without

destroying

information

in

main

storage.

The

I/O

units

are

sequenced

ON

one

by

one.

If

power

cannot

be

brought

up

for

a

unit,

further

power-on

sequencing

is

interrupted

(console

Power

On

light

remains

off)

until

corrective

action

is

taken

for

that

unit.

All

on-line

I/O

units

are

also

reset.

The

po\ver-on

sequence

bypasses

off-line

6

I/O

devices.

The

time

required

for

a

power-on

sequence

depends

on

the

number

of

on-line

I/O

units.

Note:

The

follo\\ing

procedure

must

be

used

when

applying

or

removing

electrical

power

to

input/

output

devices:

1.

Press

the

2030

Stop

key

and

wait

for

the

l\lanual

light

to

come

on.

2.

Set

the

Rate

switch

to

the

Single-Cycle

position.

3.

Press

the

2030

Start

key.

4.

Turn

power

on

or

off

on

the

I/o

unit.

5.

Set

the

Rate

switch

to

the

Process

position.

6.

Press

the

console

Start

key

to

resume

opera-

tion.

This

procedure

ensures

that

the

system

is

in

a

cycle

in

which

read/write

storage

is

not

being

accessed.

Thus,

any

electrical

surge

on

the

chan-

nel

that

might

have

been

caused

by

applying

or

removing

power

to

the

unit

does

not

affect

the

contents

of

storage.

If

power

is

removed

from

the

last

I/O

unit

(because

maintenance

is

required)

on

a

channel.

the

line

terminators

must

be

relocated

in

order

to

continue

CPU

operations.

The

last

I/O

unit

on

any

channel

must

be

on

as

long

as

the

system

is

on.

Power-Off

Key

This

key

removes

power

to

the

CPU

and

all

on-line

I/O

units.

The

contents

of

main

storage

are

not

altered

during

the

power-off

operation.

except

that

if

a

storage-read

cycle

has

been

taken

(the Allo\\,-

\!.,Trite

indicator

is

on),

a

manual-\\Tite

cycle

is

forced

to

ensure

that

the

contents

of

the

location

just

read

are

not

lost.

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B

I/O

interruption

conditions

are

reset

when

the

Power-Off

Key

is

operated.

Therefore,

any

pending

I/O

interruptions

are

lost

during

a

power-off

opera-

tion.

The

Power-Off

key

takes

precedence

over

the

Power-On

key.

The

recommended

power-off

procedure

is:

1.

Press

the

console

Stop

key

and

wait

for

the

Manual

light

to

come

on.

(The

Stop

keys

on

the

attached

I/O

units

do

not

cause

the

system

to

enter

the

manual

state.

)

2.

Press

the

Power-Off

key.

Emergency

Pull

Switch

The

Emergency

Pull

Switch

removes

all

primary

electrical

power

(including

power

to

all

on-line

I/O

units)

with

no

regard

to

sequencing.

The

contents

of

storage

may

be

altered

if

this

switch

is

operated.

As

the

name

implies,

the

Emergency

Pull

Switch

should

be

used

only

if

necessary.

This

switch

must

be

manually

reset

by

the

Customer

Engineer.

The

system

is

protected

by

thermal

overload

switches.

If

the

temperature

of

the

operating

environment

is

too

high,

these

switches

drop

system

power.

Contact

the

Customer

Engineer

whenever

system

power

cannot

be

maintained.

System

(SYS)

Indicator

This

indicator

is

normally

on

whenever

either

of

the

use

meters

is

running.

(See

the

Use

Meters

section.

)

Manual

(MAN)

Indicator

This

light

indicates

that

the

CPU

clock

is

stopped

and

that

no

channel

operation

is

in

progress

(as

long

as

the

System

light

is

off).

Several

of

the

manual

console

controls

are

effective

only

when

this

lamp

is

on.

\Vait

Indicator

When

this

light

is

on,

the

CPU

clock

is

running

but

no

instruction

processing

occurs.

If

an

interruption

occurs,

processing

is

initiated

as

required

by

the

program.

8

Test

Indicator

The

Test

light

is

on

whenever

the

Address

Compare,

Check

Control,

ROS

Control,

or

Rate

switch

is

not

set

to

Process

(normal

processing

position).

Load

Indicator

This

indicator

turns

on

when

the

Load

key

is

pressed

and

released.

It

remains

on

until

the

load

micro-

program

is

successfully

completed

(the

initial-load

PSW

is

set

into

circuitry).

See

the

Load

Key

section.

Load

Key

This

key

is

used

to

initialize

the

system.

The

f01-

10\ving

functions

occur:

1.

An

automatic

System

Reset

is

performed.

2.

The

CPU

clock

is

started.

3.

The

basic

test

microprogram

is

performed.

This

test

is

looped

128

times.

4.

The

clear

UCW

microprogram

is

run

to

reset

all

the

flag

bytes

in

the

UCW

area

of

auxiliary

storage.

5.

The

load

microprogram

is

begun.

This

routine

analyzes

switches

G,

H,

and

J

to

determine

the

address

of

the

program-loading

I/O

device

(load-unit

address).

\Vhen

this

routine

is

com-

pleted,

the

Initial

Program

Load

(IPL)

PSW

has

been

successfully

set

up,

and

the

Load

light

is

turned

off.

Note

that

the

system

mask

is

reset

when

the

load

key

is

pressed.

The

system

mask

in

the

IPL

PSW

is

then

effective

as

soon

as

the

IPL

PSW

is

set

up.

Interrupt

Key

When

this

key

is

pressed,

the

interruption

code

of

the

external

old

PSW

is

altered

to

indicate

that

an

external

interruption

is

pending.

The

system

recog-

nizes

this

interruption

only

if

programmed

to

do

so.

Switches

F,

G, H,

and

J

These

rotary

switches

are

normally

used

by

the

operator

for

the

following

operations:

1.

Manual

alteration

of

an

instruction

address

or

a ROS

address

(F,

G,

H,

and

J).

2.

Manual

entry

of

the

load-unit

address

(G,

H,

and

J).

3.

Manual

entry

of a

byte

of

information

into

main

storage

or

into

a

data-flow

register

(H

and

J).

~

The

functions

of

these

four

switches

are

described

in

detail

in

other

sections

of

this

manual.

Switch

F

is

also

used

for

1400

compatibility

opera-

tions

(see

IBM

System/360

Model

1400

Compatibility

Feature,

Form

A24-3255).

Switches

F

and

G

have

particular

significance

for

1620

compatibility

opera-

tions

(see

IBM

System/360

Model

30,

1620

Compati-

bility

Feature,

Form

A24-3365).

CONSOLE CONTROLS

The

manual

controls

on

the

2030

console

permit

the

operator

to

initiate

system

operation

in

any

of

seyeral

modes,

and

to

perform

display

and

store

operations.

Note:

Storage

Protection

is

not

effective

during

main-storage

alteration

or

display

operations

initiated

from

the

console.

Care

must

be

exercised

to

ensure

that

useful

data

is

not

unintentionally

altered.

Data

and

Address

Entry

Swit

ches

Eight

rotary

switches

are

provided

for

manually

entering

data

or

addresses

into

the

system.

Each

of

these

sixteen-position

switches

provides

one

hexadecimal

digit

(four

bits

plus

parity).

Switches

A,

B,

C,

and

D

are

used

to

enter

an

address

for

manual

operations

involving

main

or

auxiliary

stor-

age,

or

to

set

up

a

compare

address.

These

four

switches

are

connected

to

the

main-storage

address

register

and

to

the

compare

(match)

circuits.

Switches

F,

G, H,

and

J

are

used

to

set

up

an

instruction

address,

a ROS

address,

a

load-unit

address,

or

enter

manual

data

into

the

system.

These

four

switches

are

connected

to

the

data-flow

system

through

the

A-

and

B-registers.

These

switches

are

normally

used

as

follows:

Switch

A,B,C,D

F,G,H,J

G,H,J

H,J

Function

A

stop

or

restart

address

to

be

matched

against

the

contents

of

the

Main

Storage

Data

Register

(MSDR)

or

the

ROS

address

regis-

ter

(WX),

A

main-storage

address

for

manual

store

or

display

operations.

An

instruction-Start

address

or

a

ROS-Start

address

for

a

manual

operation.

The

load-unit

address

(I/O

device

and

channel

address

from

which

the

program

is

to

be

loaded),

A

data

byte

to

be

loaded

into

main

or

auxiliary

storage,

or

into

a

data-flow

register.

The

specific

functions

provided

by

these

eight

switches

are

detailed

in

various

sections

of

this

publication.

Switches

F

and

G

also

have

functions

unique

to

the

1400

and

1620

compatibility

features.

Display-Storage

Selection

Dial

This

control

can

be

used

to

display

information

from

(or

store

into

certain)

system

registers

that

do

not

have

full-time

indicators

on

the

console.

In

addition,

proviSion

is

made

to

display

from

or

store

into

any

main-storage

or

auxiliary-storage

location.

The

dual-concentric

rotary

switch

labeled

E

is

used

to

access

the

registers

and

system

control

points

shown

on

the

dial

(Figure

3).

Use

of

the

Storage-Display

Selector

switch

is

described

in

the

Display

and

Store

Operations

section.

~s

MS

\ I

~

0 "'TI

-i

v"

~

0

~

/I

5

')

Figure

3.

Display-Storage

Selection

Switch

9

OPERATION

CONTROLS

Four

rotary

control

switches

are

provided

to

allow

any

of

several

modes

of

system

operation.

Althougb

these

controls

are

normally

used

only

by

the

IBM

Customer

Engineer,

certain

of

their

functions

are

useful

to

the

programmer

and

operator.

The

Test

light

is

on

if

these

four

switches

are

not

all

set

to

the

Process

position.

Rate

Switch

The

three

modes

of

operation

provided

by

this

control

are:

Instruction

Step

(INSN

STE

P)

Position

When

the

Rate

switch

is

in

this

position,

one

com-

plete

instruction

(including

all

pending

unmasked

interruptions)

is

executed

each

time

the

Start

key

is

pressed.

After

the

instruction

has

been

executed,

the

A-

and

B-registers

contain

the

address

of

the

The

stop

that

then

occurs

is

identical

to

the

stop

that

occurs

when

the

Stop

key

is

pressed.

If

an

input/output

instruction

is

executed,

the

I/O

instruction

and

all

associated

chaining

is

com-

pleted

before

the

final

stop

occurs.

If

the

start

key

is

pressed

again

during

the

chaining

operation,

the

is

processed.

Process

Position

This

position

of

the

Rate

switch

is

used

for

normal

program

processing.

Single-Cycle

Position

When

the

Rate

switch

is

in

this

position,

the

system

advances

only

one

ROS

cycle

each

time

the

Start

key

is

pressed.

Data

overruns

may

occur

if

this

mode

is

used

for

input/output

operations.

Check

Control

Switch

The

setting

of

this

switch

determines

the

system

reaction

when

an

error

is

detected

in

the

CPU

or

I/O

channels.

Several

courses

of

action

are

allowed

as

follows:

10

Diagnostic

Position

In

this

mode,

system

control

in

case

of

an

error

is

under

control

of a

special

microprogram.

Disable

Position

When

the

system

is

operated

in

this

mode,

parity

errors

are

logged

(in

associated

check

circuitry),

but

otherwise

the

failure

is

ignored.

Note,

however,

that

certain

system

errors

cannot

be

ignored;

that

is,

automatic

correction

of

read-only

storage

addressing

is

not

provided;

and

the

wrong

word

will

be

accessed.

Results

obtained

while

processing

a

problem

program

in

this

mode

may

be

wrong.

Process

Position

This

position

of

the

Check

Control

switch

is

used

for

problem-program

processing.

When a

parity

check

occurs,

the

malfunction

trap

microprogram

is

automatically

initiated.

This

routine

stores

the

contents

of

the

machine

check

register

and

the

pro-

gram

status

word

in

fixed

main-storage

locations

and

originates

a

machine

check

interruption

(refer

to

the

IBM

System/360

Principles

of

Operation,

Form

A22-6821).

Stop

Position

Detection

of

a

parity

error

in

this

mode

causes

an

unconditional

CPU

clock

stop,

regardless

of

machine-

check

masks.

I/O

data

overruns

may

occur

if

the

system

is

operated

in

this

mode.

Restart

Position

When

an

error

occurs

in

this

mode,

the

resultant

system

response

is

dependent

upon

the

setting

of

the

Address

Compare

switch

as

follows:

1.

With

the

Address

Compare

switch

set

to

SAR

Restart,

a

System

Reset

is

initiated,

the

basic

micro-diagnostic

and

clear-UCW

routines

are

executed,

the

instruction

counter

is

set

to

the

address

specified

by

switches

F,

G,

H,

and

J,

and

an

instruction

cycle

is

started.

2.

With

the

Address

Compare

switch

set

to

ROAR

Restart

or

ROAR

Restart

Storage

Bypass

position,

the

circuitry

registers

(not

general-purpose,

floating-point,

or

UCWs)

are

reset,

the

ROS

address

register

is

set

as

specified

by

switches

F,

G, H,

and

J,

and

the

resulting

microprogram

is

initiated

(with

or

without

affecting

main

storage,

depending

on

the

setting

of

the

Address

Compare

sWitch).

3.

\Vith

the

Address

Compare switch

set

to

ROAR

Restart

Without

Reset,

operation

is

identical

to

that

of ROAR

Restart

except

that

no

reset

is

initiated.

4.

With

the

Address

Compare

switch

set

to

any

other

position,

the

address

specified

by

switches

F,

G,

H,

and

J

is

placed

in

the

instruction

counter

and

an

I-cycle

is

started.

Address

Compare

Switch

This

switch

determines

whether

the

CPU

match

circuit

is

connected

to

the

Read-Only

Storage

Address

Register

(ROAR)

or

to

the

Main-Storage

Address

Register

(SAR) ,

and

the

system!

s

reaction

when

an

address

match

occurs.

\Vhen

the

switch

is

in

any

position

that

contains

the

term

ROAR,

the

read-only

storage

address

register

is

compared

to

switches

A,

B,

C,

and

D;

other

positions

apply

to

the

main-storage

address

register.

The

switch

positions

and

the

associated

system

responses

are

as

follows:

Process

Position

This

position

is

used

for

normal

problem-program

processing.

ROAR SYNC

Position

This

position

provides

a

sync

pulse

(for

Field

Engineering

purposes)

when

the

address

specified

by

switches

A,

B,

C,

and

D

matches

the

contents

of

the

read-only

storage

address

register

(WX

register)

.

ROAR

Stop

Position

With

this

setting,

system

operation

proceeds

until

the

contents

of

the

ROAR

match

the

address

speci-

fied

by

switches

A,

B,

C,

and

D.

When

this

match

occurs,

the

CPU

clock

is

turned

off

(at

the

end

of

the

ROS

cycle

in

progress)

and

the

system

stops.

Early

ROAR

Stop

Position

With

this

setting,

processing

proceeds

until

the

contents

of

the

ROAR

match

the

address

specified

by

switches

A,

B, C,

and

D.

When

the

match

occurs,

the

CPU

clock

is

turned

off

(at

the

end

of

the

current

ROS

cycle)

and

the

system

stops.

The

ROAR

indi-

cators

display

the

address

of

the

ROS

word

just

prior

to

the

ROS

word-address

set

in

switches

A,

B,

C,

and

D.

The

ROS

word

djsplayed,

however,

is

the

one

at

the

address

specified

in

switches

A,

B, C,

and

D.

ROAR

Restart

ROAR

Restart

Without

Reset,

and

ROAR

Restart

Storage

Bypass

Positions

These

three

settings

are

similar

in

that

the

occurrence

of

a

match

between

a ROAR

address

and

switches

A,

B,

C,

and

D

causes

the

ROAR

to

be

reset

to

the

value

specified

by

switches

F,

G, H,

and

J.

In

no

case

are

the

general-purpose

or

floating-point

registers,

or

the

UCW

flag

bytes

reset.

For

ROAR

Restart,

CPU

registers

are

reset

before

the

ROAR

is

reset.

For

ROAR

Restart

Storage

Bypass,

the

function

is

identical

except

that

main

storage

is

not

permitted

to

operate;

hence,

normal

problem-program

proc-

essing

cannot

be

done

in

this

mode.

In

the

ROAR

Restart

without

Reset

position,

the

function

is

the

same

as

with

ROAR

Restart

except

that

no

reset

is

performed.

SAR

Restart

Position

When a

match

occurs

in

this

mode,

a

fixed

address

is

forced

into

the

ROAR.

The

basic

micro-diagnostic

and

clear-UCW

routines

are

performed,

the

address

specified

by

switches

F,

G, H,

and

J

is

loaded

into

the

instruction

counter,

and

an

instruction

cycle

is

started.

SAR

Stop

Position

When a

match

between

the

SAR

and

switches

A,

B,

C,

and

D

occurs

in

this

mode,

the

CPU

clock

is

stopped

at

the

end

of

the

write

cycle

in

which

the

match

occurs.

SAR

Delayed

Stop

Position

In

this

mode,

a

match

between

the

SAR

and

switches

A,

B, C,

and

D

causes

the

CPU

clock

to

stop

at

the

11

conclusion

of

execution

of

the

instruction

in

which

a

match

occurs.

All

pending

interruptions

are

taken

before

the

clock

stops.

ROS

Control

Switch

This

switch

is

primarily

for

Field

Engineering

use.

ROS

Scan

Position

This

mode

is

used

when

certain

diagnostic

tests

(scan

ROS

or

read/write

storage)

are

run.

Inhibit

CF

Stop

Position

In

this

mode,

processing

occurs

in

the

normal

fashion

except

that

microprogram

stops

(determined

by

the

CF

field)

are

ignored.

Process

Position

This

position

is

used

for

normal

program

processing.

PUSH BUTTONS

Several

push

button

switches

are

provided

to

allow

the

operator

to

perform

manual

operations

or

to

initiate

system

functions.

The

title

given

to

each

button

describes

the

resulting

function

when

the

switch

is

operated.

Power-On

Key,

Power-Off

Key,

and

Emergency

Pull

Switch

These

controls

are

discussed

in

the

Operator's

Control

Panel

section.

System

Reset

Key

Pressing

this

key

resets

the

CPU

clock,

all

regis-

ters

(except

the

general-purpose

and

floating-point

registers

in

local

storage),

the

controls

in

the

CPU,

and

all

I/o

units

(including

all

sense

and

status

for

the

I/O

units).

In

addition,

when

the

Start

key

is

pressed

after

operation

of

the

System

Reset

key,

the

Basic

Test

and

UCW

Reset

microprograms

are

initiated.

(The

Basic

Test

routine

is

looped

128

times,

so

disregard

the

various

error

indicators

during

this

time.)

See

the

ROAR

Reset

Key

section.

Also,

when

the

System

Reset

key

is

operated,

the

current

system

mask

is

reset.

However,

upon

12

restart,

the

same

current

system

mask

controls

the

system

if

that

mask

in

local

storage

has

not

been

altered

before

restart

(see

Current

Program

Status

Word

Selection

section).

ROAR

Reset

Key

This

key

is

used

to

manually

alter

the

ROAR

address

(WX

registers)

from

the

contents

of

switches

F,

G,

H,

and

J.

The

ROAR

Reset

key

is

active

only

when

the

CPU

clock

is

stopped;

its

function

is

initiated

when

the

Start

key

is

pressed.

If

the

ROAR

Reset

key

is

pressed

after

a

System

Reset

function

but

before

the

Start

Key

is

pressed,

the

Basic

Test

and

Clear

UCW

microprograms

are

not

initiated,

that

is,

the

UCW

flag

bytes

in

the

MPX

storages

are

not

reset

to

zeros.

Start

Key

If

the

Start

key

is

pressed

after

a

normal

stop

(for

example,

after

the

Stop

key

is

pressed),

instruction

processing

continues

as

if

no

stop

had

occurred.

Machine

status

is

unaffected.

If

the

Start

key

is

pressed

after

a

Start

Reset

function,

the

Basic

Test

routine

is

performed,

and

the

Clear

UCW

routine

resets

all

UC\V

flag

bytes

to

zeros.

If

the

Start

key

is

operated

again,

the

PSW

located

at

address

0000

is

loaded

into

circuitry,

and

processing

starts.

(See

Start

Reset

Key

and

ROAR

Reset

Key

sections.

)

Set

IC

Key

This

key

is

used

to

manually

alter

the

Instruction

Counter

(IC)

address

from

the

contents

of

switches

F,

G,

H,

and

J,

and

is

active

only

when

the

CPU

clock

is

stopped

(Manual

light

is

on).

When

the

Set

IC

key

is

pressed,

the

altered

instruction

address

is

displayed

in

the

B-

and

A-registers,

and

the

system

stops.

Any

outstanding

channel

share

cycles

are

completed

before

this

microprogram

stop

0

ccurs.

Processing

begins

at

the

new

instruction

address

when

the

Start

key

is

pressed.

If

the

Set

IC

key

is

pressed

after

a

System

Reset

function,

the

instruction

counter

is

set

to

the

address

entered

from

switches

F,

G,

H,

and

J.

Check

Reset

Key

This

key

resets

all

machine-check

logic

circuits.

The

Check

Reset

key

may

be

used

at

any

time

(C

PU

clock

running

or

stopped).

Stop

Key

When

this

key

is

pressed,

the

system

enters

the

stopped

state

when:

1.

The

instruction

being

processed

has

been

com-

pleted,

2.

All

pending

interruptions

have

been

serviced,

and

3.

Any

I/O

operation

in

progress

has

been

finished.

If

data

or

command

chaining

is

involved,

it

is

completed

before

the

CPU

clock

is

stopped.

The

System

light

stays

on

as

long

as

any

I/O

unit

(except

the

1050)

is

engaged

in

an

I/O

operation;

that

is

until

device-end

is

accepted

for

the

last

command

in

a

chain

for

that

I/O

device).

Note

that

the

machine

environment

is

not

de-

stroyed

and

the

program

that

was

in

progress

can

be

restarted

(by

operation

of

the

Start

key).

The

address

of

the

is

displayed

in

the

B-

and

A-registers.

When

the

system

is

in

the

stopped

state,

the

multiplexor

channel

is

allowed

to

accept

share-

request

traps

(microprogram

branches),

and

the

selector

channel

is

allowed

to

accept

data

cycles.

This

provision

permits

input-terminal

and

multi-

system

operations

even

though

the

2030

program

in

progress

has

been

manually

interrupted.

Even

though

these

operations

are

in

progress,

data

can

be

stored

or

displayed.

At

the

instant

a

cycle

is

being

used

for

a

channel

operation,

the

manual

store

and

display

circuits

are

inactive.

However,

if

the

Store

or

Dis

play

key

is

held

operated,

the

data

is

stored

or

displayed.

If

the

store

key

is

operated

only

during

a

channel-operation

cycle,

the

data

to

be

manually

stored

is

not

stored.

It

is

advisable,

therefore,

to

display

any

location

(in

which

data

is

manually

stored)

so

that

storing

can

be

verified.

Interval

Timer

Switch

(INT

TMR)

When

the

Interval

Timer

feature

is

installed

and

this

switch

is

on,

the

interval

timer

is

allowed

to

generate

program

interruptions.

If

the

switch

is

off,

the

interval

timer

is

ignored

and

the

main-

storage

timer

locations

are

not

changed.

Store

Key

This

key

causes

the

hexadecimal

byte

specified

by

switches

Hand

J

to

be

entered

into

the

area

selected

by

the

Display

Storage

Selection

dial

(switch

E).

If a

register

is

selected

by

switch

E,

the

data

byte

is

entered

into

that

register

and

displayed

in

both

the

B-

and

A-registers.

Information

cannot

be

stored

in

all

the

registers

selectable

by

switch

E.

See

the

Store

and

Display

Section.

When

main

storage

(MS)

or

auxiliary

storage

(AS)

is

selected

by

switch

E,

switches

A,

B,

C,

and

D

specify

the

address

into

which

the

data

byte

is

stored.

The

data

byte

(from

switches

Hand

J)

is

displayed

in

both

the

B-

and

A-registers.

The

CPU

clock

must

be

stopped

for

the

store

operation.

If

main

or

auxiliary

storage

is

being

accessed,

the

Allow

Write

light

must

be

off.

Lamp

Test

Key

Pressing

this

key

causes

all

indicator

lights

on

the

2030

console

to

turn

on.

This

test

does

not

affect

system

operation

and

can

be

performed

during

program

execution

if

desired.

(The

console

lamps

will

be

slightly

dimmer

than

during

normal

operation.

)

Display

Key

The

function

of

this

key

is

similar

to

that

of

the

Store

key,

except

that

the

accessed

location.

is

not

altered.

The

Display

key

is

provided

so

that

regis-

ters

that

do

not

have

their

own

console

indicators

can

be

displayed.

Main-storage

(MS)

and

auxiliary-storage

(AS)

locations

are

displayed

by

setting

switch

E

to

the

storage

area

deSired,

and

switches

A,

B,

C,

and

D

to

the

address

of

the

location

to

be

displayed.

The

Main

Storage

Data

Register

(MSDR)

is

used

to

display

the

contents

of

the

accessed

storage

location.

If

the

original

value

in

the

MSDR

will

be

needed

when

the

program

is

restarted,

record

this

value

so

the

MSDR

can

be

restored

after

the

display

operation.

If

the

ROS

control,

Rate,

Address

Compare,

and

Check

Control

switches

are

all

set

to

Process,

and

the

system

is

allowed

to

come

to

a

normal

stop

(Stop

key

was

pressed

and

the

manual

light

is

on),

the

contents

of

the

M

SDR

need

not

be

restored

before

the

Start

key

is

pressed

to

resume

program

operation.

13

READ

ONLY STORAGE

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1P I 0 1 2 3 I 0 1 2 3 I A 0 1 2 3 I 0 1 I 0 1 2 I 0 1 IA

pi

o 1 2 3 I

I

CR

I

CD

I I

CF

I

CG

I

CV

I

CC

I CS I

I P I 0 1 2 3 I I 0 1 2 I 0 1 I 0 1 I 0 1 2 I A o 1 2 3 I

C

UNT

REGISTER

4

1 2

2 4

5 2 1 I P I 8

6 7 P 0 4

1 2

2 1

3 8

4 4

5 2

6 1

7

CHANNEL

NUMBER

ONE

I I DATA

REGISTER

I

'I

I

~

I 8 4 2

~

I 8 4 2 1 I

0 1 2 4 5 6 7

flAGS

I TAGS

CD

CC

SLI

SKIP

PCI

I OP ADR STAT

IN IN IN

set ADR

CMND

OUT OUT OUT

Figure

4.

Console

Display

Indicators

(Part

1

of

2)

A

register

selected

by

switch

E

is

displayed

in

the

A-register.

When

either

the

I-

or

J

register

(see

Figure

8)

is

selected,

both

the

I-

and

J-registers

are

displayed

in

the

Main

Storage

Address

Register

(MSAR).

This

is

also

true

for

the

U-

and

V-registers

(see

Figure

8).

(The

selected

register

is

also

dis-

played

in

the

A-register.

)

The

CPU

clock

must

be

stopped

and

the

Allow

Write

indicator

must

be off

for

any

dis

play

operations

involving

storage,

or

for

displays

of

the

IJ

or

UV

registers.

Note,

however,

that

the

contents

of

the

I-,

J-,

U-,

or

V-registers

can

be

displayed

in

the

A-register

if

the

Allow

Write

indicator

is

on.

DISPLAYS

Several

indicators

are

provided

to

display

control

information,

data

bytes,

and

system

status.

Each

indicator

shows

the

binary

condition

of

a

latch

or

signal

line.

When

a

latch

is

set,

or

a

signal

is

on,

its

associated

lamp

is

lighted.

In

cases

where

the

position

of a

bit

in

a

field

is

important,

the

numerals

0,

1,

2;

3,

etc,

are

lighted;

but

where

bits

are

grouped

to

form

a

numeric

digit,

the

binary

bit

values

are

lighted

(8,4,2,1).

The

P

lamps

associated

with

many

of

the

console

displays

represent

the

parity

bit

for

the

information.

14

KEY

I

COMMAND

I I

~

I 8 4 2 1

I!

4 2 iI I

0 1 2 3 5 6

I CHECKS

SfRV

I

IL

PROG

PROT

CHNL

CHNl

INT

IN

DATA

CTRL

FACE

SERV

SUP

OUT OUT

In

addition

to

the

control

information

provided

by

the

read-only

storage

display,

the

2030

console

displays

the

contents

of

certain

data

registers,

the

read/write

storage

address

register,

a

number

of

CPU

status

conditions,

the

multiplexor

channel

tags,

and

several

check

conditions.

Although

only

some

of

the

registers

are

displayed,

provision

is

made

to

display

the

contents

of

all

CPU

registers

as

described

in

the

Display,

and

Store

section

of

this

publication.

CPU

Status

Indicators

The

CPU

status

indicators

(Figure

4,

Part

2

of

2)

signal

the

actual

operating

status

of

the

CPU

at

any

time.

These

indicators

and

their

corresponding

meanings

are:

EX.

This

lampturns

on

at

the

end

of

each

instruction

execution

(that

is,

whenever

the

micro-

instruction

branch-on-interrupt

occurs).

In

the

micro-

instruction

word

immediately

following

the

interrupt

word,

the

EX

latch

is

reset.

Note

that

if

the

system

is

programmed

to

stop

at

the

end

of

instruction

exe-

cution

(for

example,

if

the

stop

button

has

been

pressed),

the

EX

lamp

remains

on.

It

turns

off

when

the

CPU

clock

is

restarted.

CHANNEL

NUMBER

TWO

I

DATA

REGISTER

I

KEY

I COMMAND I

I P I 8 4 2 1 , 8 4 2

~

I P I 8 4 2 1 I 8 4 2 1 I

P 0 1 2 3 4 5 6 P 0 1 2 3 4 5 6 7

flAGS

I TAGS I CHECKS

CD CC

Sli

SKIP PCI I

OP

ADR

STAT

SERV

I IL PROG PROT

CHNL CHNL

INT

IN IN

DATA

CTRL FACE

SEL

ADR

CMND

SERV

SUP

OUT OUT

OUT

I

MPX

CHANNEl

IBM 360 User manual

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