Icom IC-R7000 User manual
c
FOREWORD
The most sophisticated,
continuous
coverage receiver on the market today, the
IC-R7000 is the result
of
both advanced ICOM engineering and state-of-the-art
computer
interface technology from ICOM such as the new Cl·V System: a
feature
that
allows
for
easy and convenient computer control
of
your IC-R7000.
Equipped
with
99 internal memories
that
are completely owner-programmable,
the IC·R7000 is unmatched in scanning and coverage versatility
within
the
25
to
1300MHz range and may even cover frequencies up
to
2000MHz. Low band,
aircraft, marine, business, FM, amateur radio, emergency services, government,
and television
bands·
all are conveniently available and immediately accessible
with the IC-R7000.
ASSISTANCE
Five separate versions
of
the IC·R7000 have been designed
for
use in the U.S.A.,
Europe, France, Australia, and Germany. This service manual covers every
version. When using the manual each model can
be
referred to by the follow-
ing assigned version numbers:
#02
U.S.A. version
#03
Europe version
#04
France version
#05
Australia version
#06
Germany version
If
you require assistance
or
information regarding the operation and capabilities
of
the IC-R7000, please
contact
your nearest authorized ICOM Dealer or ICOM
Service Center.
TABLE OF CONTENTS
SECTION 1
SPECIFICATIONS.......................................................
1
-1
SECTION 2 OUTSIDE AND INSIDE VIEWS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 1
~
4
2 - 1 FRONT PANEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 1
2-2
REAR PANEL
...........................................................
2-2
2 - 3 INSIDE VIEW (PLL UNIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 2
2 · 4 INSIDE VIEW (MAIN
UNIT)................................................
2 - 3
2 - 5 INSIDE TOP VIEW (RF AND IF UNITS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 3
2 · 6 INSIDE BOTTOM VIEW (POWER SUPPLY AND DC-DC CONVERTER
UNITS)......
2 - 4
2 · 7 INSIDE BOTTOM VIEW (LOGIC UNIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 4
SECTION 3 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 1
SECTION 4 CIRCUIT DESCRIPTION
.............................................
4 - 1
~
10
4 · 1 RECEIVER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 1 - 6
4 · 2 POWER SUPPLY CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 6
4 · 3 PLL CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 7 - 8
4-
4 LOGIC
CIRCUITS....................................................
4 - 8 - 10
4 - 5 DISPLAY
CIRCUITS..................................................
4 - 10
4 - 6 KEYBOARD
CIRCUITS...............................................
4 -
10
SECTION 5 MECHANICAL PARTS AND
DISASSEMBLY...........................
5 -
1~5
5-1
FRAME DISASSEMBLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 1
5 - 2 FRONT PANEL
DISASSEMBLY............................................
5 - 2
5 · 3 REAR PANEL
DISASSEMBLY.............................................
5 - 3
5 · 4 TOP SIDE CONNECTOR
CONNECTIONS...
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 4
5 · 5 BOTTOM SIDE CONNECTOR CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 5
SECTION 6 MAINTENANCE AND ADJUSTMENT
.................................
6 -
1~11
6-1
PREPARATION BEFORE
SERVICING...................................
6 - 1
6 - 2 PLL
ADJUSTMENT..................................................
6 - 2 - 3
6 · 3 LOCAL OSCILLATOR
ADJUSTMENT...................................
6 - 4 - 5
6 · 4 RECEIVER
ADJUSTMENT.............................................
6 - 6 -
11
SECTION 7 BOARD LAYOUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 1
~
19
7 · 1 INTERCONNECTION
................................................
.
7 - 2 FRONT UNITS
.....................................................
.
7 · 3 MAIN UNIT
........................................................
.
7-1
7-2-3
7-4-5
7 · 4 IF
UNIT..
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 6 - 7
7 - 5
RF
UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 8 - 9
7 · 6 LOGIC UNIT
........................................................
7 - 10 -
11
7 · 7 PLL UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 -
12
-
13
7-8
DISPLAYUNIT
......................................................
7-14-15
7 - 9
REG
AND DL-REG
UNITS.............................................
7 -
16
-
17
7 ·
10
DC-DC,
EF
AND KEYBOARD UNITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 -
18
-
19
SECTION 8 PARTS LIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 1
~
31
SECTION 9 VOLTAGE
DIAGRAMS...............................................
9-1~4
9 - 1 IC-R7000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 1 - 2
9 - 2 TV-R7000 (OPTION) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 3
9 - 3
RC-12
(OPTION).........................................................
9 - 4
SECTION 10 SCHEMATIC DIAGRAM
.............................................
SEPARATE
SECTION 1 SPECIFICATIONS
• Receive frequency range
• Receive modes
• Sensitivity
• Squelch
sensitivity
• Selectivity
• Spurious and image response
rejection
• Frequency
stability
• Receive system
• Intermediate frequencies
• Frequency
control
• Number
of
memory channels
• Supply voltage
• Current drain
•Antenna
impedance
• Audio
output
• Audio
output
impedance
• Usable temperature
• Dimensions
•Weight
VERSION FREQUENCY COVERAGE (MHz)
#02,
#03
25-
999.999
*1025-1999.999
#04,
#05
**25-
999.999
*1025-1999.999
#06
28.0-29.7,
144,0-146.0
430.0-440.0
*
Specifications
guaranteed from
1240-1300MHz.
**Excluding
87.5-108MHz.
A3E (AM),
F3E
(FM), J3E (SSB)
25-999.999MHz
FM
: Less than
-113dBm
for 12dB SINAD
FM
(wide) : Less than
-107dBm
for
12dB
SINAD
AM : Less than
-107dBm
for 10dB S/N
SSB : Less than
-117.5dBm
for
10dB S/N
1240-1300MHz
FM
: Less than
-113dBm
for
12dB
SINAD
FM
(Threshold)
FM
(Tight)
SSB (Threshold)
FM,AM
FM (wide) : Less than
-101
dBm
for
12dB
SINAD
AM : Less than
-101
dBm
for
10dB
S/N
SSB : Less than
-117.5dBm
for
10dB
S/N
Less than
-101
dBm for noise squelch
More than
-17dBm
for
meter squelch at
S9+60dB
More than
-97.5dBm
for meter squelch
±7.5kHz
minimum
at
-6dB
FM (narrow), AM (narrow)
FM (wide)
±3.0kHz
minimum
at
-6dB
±75kHz
minimum at
-6dB
±1.4kHz
minimum
at
-6dB
SSB
More than 60dB
25-999.999MHz
±5ppm
at
o·c-+50°C
1240-1300MHz
±10ppm
at
o·c-+50°C
25-999.999MHz
FM, AM, SSB Triple-conversion superheterodyne
FM (wide) Double-conversion superheterodyne
1240-1300MHz
FM, AM, SSB Quadruple-conversion superheterodyne
FM
(wide) Triple-conversion superheterodyne
25-512MHz
1st
778.?MHz
2nd
10.?MHz
3rd 455kHz excluding
FM
(wide) mode
512-999.999MHz:
1st
266.?MHz
2nd 10.?MHz
3rd 455kHz excluding
FM
(wide) mode
CPU
based 100
Hz
step
digital
PLL synthesizer
99 channels
117V (#02), 230V
(#03,
#04,
#05), 220V
(#06)
AC
(50/60Hz)
Receiving 1.7A at maximum audio
output
Squelched 1.4A
500
More than 2.5W at 10%
distortion
with
an
80
load
4-80
-10·c-+60°c
286(303)mm(W) x 110(127)mm(H) x 276(319)mm(D)
Bracketed values include projections.
Approximately 8.0kg (excluding options)
All stated
specifications
are approximate and subject
to
change
without
notice or obligation.
1
-1
Downloaded by
Amateur Radio Directory
1 SECTION 2 OUTSIDE
AND
INSIDE VIEWS
I
2·1
FRONT PANEL
MODE
INDICATOR------.
1GHz INDICATOR
(1
GHz]
SIG
METER--------------
SCAN-DELAY
CONTROL---
[SCAN-DELA
Y]
METER SWITCH [METER]
SIGNAL INDICATOR [SIG
PROGRAMMED
SCAN-----'
INDICATOR [PRO]
SCAN-SPEED CONTROL SCAN INDICATOR
[SCAN]------'
[SCAN-SPEED]
VOICE SCAN
CONTROL
SWITCH [VSC]
PHONES
JACK---~
[PHONES]
RECORDING JACK [REC]
r---SCAN
START/STOP-------,
1
~PRIO
rmPROG n SEL-M MODE MEMORY
l~~Ll!!s~~
I
Eal] Eal]
Eal] Eal]
Eal]
AF GAIN CONTROL [AF
GAIN]-----'
SQUELCH CONTROL
[SQUELCH]-------'
MEMORY CHANNEL SCAN
START/STOP----~
SWITCH [MEMORY]
SELECTED MODE MEMORY SCAN START/STOP
SWITCH [MODE]
SELECTED MEMORY SCAN START/STOP
SWITCH [SEL-M]
PROGRAMMED SCAN START/STOP
SWITCH [PROG]
PRIORITY SCAN START/STOP
SWITCH [PRIO]
PRIORITY SCAN SET SWITCH
[PRIO-SET]
PROGRAMMED SCAN SET SWITCH
[PROG-SET]
SELECTED MEMORY SET/RESET SWITCH
[SEL-M-SET/RESET]
DIMMER SWITCH
[DIMMER]
NOISE BLANKER
SWITCH [NB]
ATTENTUATOR--+ll!;~ll
SWITCH [ATT]
REMOTE SWITCH
[REMOTE]
-----FREQUENCY
INDICATOR
----AUTO
INDICATOR [AUTO]
MEMORY CHANNEL
INDICATOR
[M
ch]
'-----SELECTED
MEMORY
INDICATOR
[.]
'-------HI-LO
INDICATOR [HI] [LO]
REMOTE CONTROL SENSOR AND
LED INDICATOR
c)
I]
TUNING STEP SELECTOR
CONTROL [TS]
MEMORY CHANNEL-WRITE
SWITCH
[MEMORY CH-WRITE]
'----CLEAR
SWITCH [CLEAR]
'----MEMORY
CHANNEL SELECTOR
CONTROL [MEMORY CH]
1GHz BAND SWITCH
[1GHz)
l~~---SPEECH
SWITCH
[SPEECH]
DIAL LOCK SWITCH
[LOCK]
SELECTED MEMORY CLEAR
SWITCH-----'
[SEL-M-CL] TUNING CONTROL
AUTO-WRITE MEMORY SCAN START/STOP SWITCH
[AUTO-M]
2-1
2·2
REAR
PANEL
~--------ANTENNA
CONNECTOR
[AN_T]
~-----USB/LSB
SELECTOR SWITCH
,:;:r=======================F=====i'==9===i~
I
.-.
[USB/LSB]
USB LSB
lllrti~-tt---EXTERNAL
SPEAKER JACK
[EXT SP]
lll<el:IJ!t--ft----RECORDER-REMOTE
JACK
[RECORDER-REMOTE]
ll\li~-tt----REMOTE
JACK [REMOTE]
,..,__....n.,,,..,,.!1-tt-FM
(1)-FM
(2)
SELECTOR SWITCH
[FM
(1),
FM
(2)]
'---+-+---10.7MHz
IF OUTPUT
JACK
[10.7MHz IF OUTPUT]
~;;;;;;;;;;;;;;;;;;~~~;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;j;=;;;;;;;;;;;;;;;;;;;;;;;;;;;~=f:::r"";;;;;;;;;l::~~--GROUNDTERMINAL[GND]
'-----------SPARE
JACK [SPARE]
'----------RECORDER-SPEECH
SWITCH
[RECORDER-SPEECH]
'------------------AC
POWER SOCKET
2·3 INSIDE VIEW
(PLL UNIT)
1/10, 1
/11
Pre-scaler (M54466L
IC4)--------------.
Programmable Divider (M54929P
IC3)-----------.
1/10 Divider (HD10551
IC7)--------------.
Voltage Regulator (NJM78M05A
IC2)--------.
Voltage RegulatoqµA78M08
IC1)-------~
Multiplier
Circuit
for
2nd LO
Output---~
PLL Reference OSC Crystal (5.12MHz
X2)-----'
--j---DOUBLER
UNIT
---D/A
Converter Crystal
(12MHz
X1)
'------------Mixer
Circuit
,__
____
__..
____________
Multiplier
Circuits
2-2
2·4 INSIDE VIEW
(MAIN
UNln
Converter for
1240-1300MHz
--------.
AF Amp
(µPC1241
H
IC8)--------------'
2·5 INSIDE TOP VIEW
(RF AND IF UNITS)
BPF and
RF
Amp
Circuits------------,
20dB Attenuator
Circuit---------,
RF
UNIT--------+---
IF
UNIT---------+-----1
.-----------FM
Center Meter and
VSC
Control
Circuits
2-3
.----------------VSC
Amp (NJM4558D IC1)
r-------
Signal Center Frequency Detector Circuit
'--------Relay
for
Recording Remote Function
'-----------voltage
Regulator (NJM7809A IC6)
'--------------Noise
Squelch Control
Circuit
.-------------------LO
TRAP UNIT
.----------1st
LO
AMP AND MIXER UNIT
f------,f------1
st IF Amp Circuit
----'-----512-1000MHz
IF Filter
---+------25-512MHz
IF Filter
---+---2nd
LO AMP AND MIXER UNIT
---+-----10.7MHz
Crystal
Filter
----'-----Noise
Blanker Circuit
----'-----
455kHz
3rd
IF
Filter
---~3rd
LO Amp and Mixer Circuits
_ __..___,_JB (AM Filter Selector Connector)
NARROW 6kHz
WIDE 15kHz
JBR
NARROW
§WIDE
2-6
INSIDE BOTTOM VIEW
(POWER SUPPLY AND DC-DC CONVERTER UNITS)
..
REG
UNIT
(#02,
#03,
#04,
#05)-+---
DL-REG UNIT
(#06)
2-7
INSIDE BOTTOM VIEW
(LOGIC
UNln
J7 (Connector for
Optionall---'-----
IC-EX310)
1/0
Expander--------+----
(µPD82C43C IC9, IC10)
2-4
iiiiiii~~----DC
Line Fuse (2A)
=------:
AC
Power Voltage Selector
Connector
(#02,
#03,
#04,
#05)
J4 J3 J4 J3
~~
~~
117V AC 234V AC
(#03,
(#02)
#04,
#05)
---+
1 Connector
for
Optional IC-EX310
-----"f-------DC-DC
UNIT
;----+---Space
for
Optional IC-EX310
VOICE SYNTHESIZER UNIT
'-----~---J14
(Connector
for
Optional
RC-12)
'-----;-----
J3 (Connector
for
Optional
RC-12)
~--+---
J17 Cl-V Baud Rate,
Address Selector Switch
SECTION 3
BLOCK
DIAGRAM
RF
UNIT
ATT
(-20dB)
I
/ CONV
I
....__
_
___..........,
T
L-------------------
osc
TRIPLER BUFFER
X1
r::::::J
DOUBLER
Q1
2SC2367
X3
TRIPLER
Q16
2SC2026
ATTSW
(FRONT)
3SK121
1SV50E x 4
55.555MHz
;:+;
MAIN UNIT 3SK121
152208x 5
PLL UNIT
IC4
M54466
1110
IC7
HD10551
c:J
X1
12.00MHz-;;:::;.
IC1, 2
BPF CTRL
NJM4558Dx2
IC3
LO
TRAP
I--~------_,
CTRL
NJM4558D
409.6MHz
343.2MHz
445.6MHz
RF
AMP
2SC3355
LO
TRAP
VCO SWITCH
Q8,
Q14
2SA1015x2
2SA1015
x3
UNLOCK
MUTE
X2
LOSW
Q20-Q22
2SC3355
1st
MIXER
IC6 BUFFER
DM88X 2SC3355 Fl1
1st
LO
(266.
7
MHz:
x2
768MHz
(778.70-
1290.6999MHz)
FROM
LOGIC
BUFFER
LO
AMP
c
[
X2
51.2MHz
Downloaded by
Amateur Radio Directory
(266.7MHz)
LO
AMP
p
:3355
AGC 2SC945
VSC AMP
NJM4558D
vsc
TO LOGIC MATRIX
IF UNIT
NJM4558D
AMP LPF
IC1/2
X110.7MHz
a
IC2TA7303P
FM
DETECTORi.......-:w
LIMITER
D28
018
1K60 2SC2458
SOL
CTRL
1------'
02,
3,
4,
6
2SC2785
2SA1348x2
2SC3399
SOL
SW
01
2SK30
NJM4558D
_
___,....___
SCAN
CTRL
010, 011
2SC2785
2SA1048
MAIN UNIT
IC7
TO LOGIC
MATRIX
LOGIC UNIT
CPU
HD63A01V1D26P
J
:+,...,..,../;......,.,......,....,.,......,.,1::
:.,_.......,+.-,.,....,.,,......,.,...........,.,..i-;+,.,-,..,.........,..........,,w..,.....,..,.........,....~,..,.........,..........,
........
~
........
.......1
P40
I
osc
024
..@C383
,.........___
........
__...,____.....'--___,
'::21
110
EXPANDER
c:::J IC9, IC10
;:t;.
µPD82C43C x 2
X2
51.2MHz
···························
~:
"
,•
"
·:
INPUT
MATRIX
(FRONT UNIT)
MAIN DIAL
3-1
"""'"""'......,,."""':.:u;"""",;oi
P47
IC2
µPD4069UBC
02,03
2SC2458x2
IC4
µPD4081BC
IC5
µPD4011BC
A4
A5
cs
WR
IR01
SECTION 4 CIRCUIT DESCRIPTION
4-1
RECEIVER CIRCUITS
4·1-1
CONVERTER CIRCUIT (MAIN UNIT)
Input signals from the ANTENNA CONNECTOR are
switched by
RF
relays RL3 and RL4 on the MAIN UNIT
either
to
through
or
to
the converter
circuit
according
to
receive frequency.
When the receive frequency is 1025-1999.9999MHz,
receive signals are applied
to
the converter
circuit
for
heterodyning. This
circuit
converts
1025-
1999.9999MHz receive signals
to
25-999.9999MHz.
A HPF
consisting
of
L9
and
CB7-CB9
attenuates
strong interfering signals in the 200MHz band.
When the receive frequency is higher than 1025MHz,
signals from the ANTENNA CONNECTOR are applied
to
the HPF UNIT. This
unit
consists
of
a HPF and
an
RF
amplifier. The HPF
consists
of
a
strip
line,
c1-
C6,
CB
and
C10-C16.
The HPF attenuates signals
with
frequencies below 1200MHz and prevents
LO
signals
(1
GHz) from leaking through the ANTENNA
CONNECTOR. 01 is an
RF
amplifier
and has a gain
of
approximately
10dB
at 1200MHz.
X1
and
014
oscillate
a frequency
of
55.555MHz.
Output from
014
is
multiplied
by three at
L3-L5,
C31,
C44 and C46 to form a frequency
of
166.66MHz. The
166.66MHz frequency
is
amplified
by 015.
Output
from
015
is
multiplied
by three
at
016
to
form a
frequency
of
500MHz, and then the 500MHz signal
(OdBm) is applied
to
the MAIN DOUBLER UNIT.
In
the MAIN DOUBLER UNIT,
output
from
016
on the
MAIN UNIT is
multiplied
by
two
at 01
to
form a LO
signal (1000MHz, 10dBm)
tor
the double balanced
mixer IC9.
4·1·2 20dB ATTENUATOR CIRCUIT (RF UNIT)
Receive signals from the MAIN UNIT are applied
to
a
BPF
consisting
of
a
strip
line,
L3
and
C1
~cs.
This
circuit
attenuates signals
that
exit
the passband
of
the BPF.
IC5
switches
receive signals through
or
to
the
attenuator.
The
attenuator
consisting
of
R2~RB
provides attenua-
tion
of
approximately 20dB.
4·1·3
RF
AMPLIFIER CIRCUIT (RF UNIT)
Receive signals are
switched
by diodes
D5,
D11,
D12,
D1B,
D19
and
D25
to
each
RF
amplifier. With fre·
quencies higher than 512 MHz,
RF
relays
RL
1 and
RL2 are used
for
the switching.
Receive signals
of
25-999.9999
or
1025-1999.9999
MHz are quadrisected as indicated in Table
1,
and
then each signal is applied
to
the
RF
amplifiers.
Each tuned
amplifier
has approximately
10dB
gain.
Table 1 shows the relation among receive frequencies
(FRx)
and
RF
amplifiers.
RECEIVE FREQUENCY
RF
AMPLIFIER
FRx[MHz]
25-
B9.9999
BPF1
(01)
1025-10B9.9999
90-
249.9999 BPF2 (02)
1090-1249.9999
250-
519.9999 BPF3 (03)
1250-1519.9999
512~
999.9999 BPF4 (04)
1512-1999.9999
Table 1
(a) BPF1
Receive
signals
via
D5
are fed
to
parallel resonance
circuit
D6,
L
11
and C15
to
attenuate interference
signals which frequencies are
half
of
receive fre-
quencies.
Receive signals via
D6,
L11
and C15 are then applied
to
the
RF
amplifier. The input tuning
circuit
of
the
RF
amplifier
is composed
of
varicaps
D7,
DB
and
L
12-L
14.
The
output
tuning
circuit
is composed
of
varicaps
D9,
D10
and
L16-L1B.
These
circuits
are tuned by the
tuning
voltage from
IC1(A).
In
addition,
D50
prevents varicaps from being
charged over
their
maximum rated voltage.
(b) BPF2
Receive signals via
D12
are fed
to
a parallel resonance
circuit
consisting
of
D13,
L22
and
C25.
The
circuit
attenuates the interference signals which frequen·
cies are half
of
receive frequencies.
A series-paralled resonance
circuit
is composed
of
varicap
D14,
L70 and
C61.
The
circuit
attenuates
strong signals
of
FM and TV broadcasts in a fre-
quency range
of
B0-110
MHz.
The input tuning
circuit
of
the
RF
amplifier
is com-
posed
of
04,
varicap
D15,
L23~L25
and C119. The
output
tuning
circuit
is
composed
of
D17,
L27-
L29
and C120.
These
tuning
circuits
are tuned by the tuning voltage
from IC1(B). In addition,
D51
protects
varicap from
being negatively charged.
4-1
(c) BPF3
Receive signals via 019 are fed
to
a HPF consisting
of
L32,
L69,
C34, C35,
C51
and C133. The cut-off
frequency
of
the HPF is
240
MHz.
The receive signals are then input
to
the
RF
amplifier.
The input tuning
circuit
of
the
RF
amplifier
(Q3)
is
composed
of
021, 022, L33 and
L34.
The
output
tuning
circuit
is composed
of
023, 024, L36 and
L37.
These
circuits
are tuned by the tuning voltage from
IC2(A).
(d)
BPF4
Receive signals via RL1 are fed
to
the parallel
resonance
circuit
consisting
of
varicap 026,
L39
and
C45.
The
circuits
attenuate interference signals
to
half
of
the receive frequency.
Input and
output
tuning
circuits
of
the
RF
amplifer
are composed
of
a strip line and varicaps
027-030.
By utilizing the strip line, stable operations are main-
tained at high frequencies.
These
circuits
are tuned by the tuning voltage from
IC2(B).
4-1-4
RF
AMPLIFIER (RF UNIT)
Signals from BPF are then applied
to
wide frequency
band amplifier
Q7
with
a gain
of
approximately 10dB.
4·1·5
LO
TRAP (TUNED NOTCH) CIRCUIT (RF UNIT)
The
LO
trap
circuit
consisting
of
a strip line and
031-034
prevents the
1st
LO
signal leakage
to
the
ANTENNA CONNECTOR.
The notch frequency is controlled by a control voltage
from IC3(B), matching the
1st
LO
frequency.
A LPF consisting
of
a strip line and
C78, C82,
C89
and C137 attenuates higher harmonics
of
the
1st
LO
signal.
4·1·6 1sr
LO
AND 1sr MIXER CIRCUITS (RF UNIT)
A BPF consisting
of
a strip line, L78, C134, C59,
C77
and
C53-C55
attenuates unnecessary signals from
the PLL UNIT.
Table 2 shows the relation among receive frequencies
(FRX)
and
1st
LO
frequencies
(F1s1Lo).
RECEIVE FREQUENCY
1st
LO
FREQUENCY
FRX
[MHz] F1stLo[MHz]
25-
89.9999
803.
7-
868.6999
1025-1089.9999
90-
249.9999 868.7-1028.6999'
1090-1249.9999
250-
519.9999 1028.7-1290.6999
1250-1519.9999
512-
999.9999 778.7-1266.6999
1512-1999.9999
Table 2
4-2
Q5 and
Q6
amplify
the
1st
LO
signal from the PLL
UNIT
to
approximately 10dBm. The
output
of
Q6
is
applied
to
IC6.
A DBM (double-balanced mixer) IC6 converts receive
signals
to
1st
IF (778.7MHz or 266.7MHz) signals.
4·1·7 1sr IF CIRCUIT (RF UNIT)
(a)
1st
IF
AMPLIFIER
1st
IF signals from IC6 are amplified
at
QB
and they
are applied
to
Fl1
or
Fl2.
Table 3 shows the relation among receive frequencies
(FRx)
and
1st
IF frequencies
(F1st1F)·
RECEIVE FREQUENCY
1st
IF
FRX
[MHz]
F1s11F[MHz]
25-
89.9999 778.7 (Fl1)
1025-1089.9999
90-
249.9999 778.7 (Fl1)
1090-1249.9999
250-
519.9999 778.7 (Fl1)
1250-1519.9999
512-
999.9999 266.7 (Fl2)
1512-1999.9999
Table 3
(b)
Fl1
CIRCUIT
The
F11
circuit
is a BPF
with
a center frequency
of
the passband at 778.7MHz and a pass-bandwidth
of
5MHz. The image interference signal (757.3MHz)
is attenuated by a notch
filter
consisting
of
L51,
and
C79.
(c) Fl2 CIRCUIT
The
F12
circuit
is a BPF
with
a center frequency
of
the passband at 266.7MHz and a pass-bandwidth
of
5MHz. The image interference signal (245.3MHz)
is attenuated by a notch
filter
consisting
of
L67, L68,
and
C88.
Series resonance
circuits
consisting
of
L73,
C86,
L74,
and
C90
sufficiently
attenuate
off·
band signals.
1st
IF signals from the
Fl1
or
Fl2
circuits
pass through
a LPF consisting
of
a strip line and
C139-C141.
1st
IF signals are then fed
to
IC7.
4·1·8
2No
MIXER CIRCUIT (RF UNIT)
The 2nd
LO
signal (256MHz
or
768MHz) from the PLL
UNIT is fed
to
a LPF consisting
of
a strip line, C104,
C105, and C146. The 2nd
LO
signal is amplified by
Q16 and Q17
to
approximately 10dBm, and is then fed
to a
3dB
attenuater
(ATT)
consisting
of
R116-R118.
Table 4 shows the relation among receive frequencies
(FRx)
and 2nd
LO
frequencies
(F2nd
Lo).
RECEIVE FREQUENCY 2nd
LO
FREQUENCY
FRx
[MHz]
F2nd
LO
[MHz]
25-
89.9999 768
1025-1089.9999
90-
249.9999
768
1090-1249.9999
250-
519.9999 768
1250-1519.9999
512-
999.9999 256
1512-1999.9999
Table 4
A double-balanced
mixer
IC7 converts
1st
IF signals
to
2nd IF (10.7MHz) signals.
A LPF
consisting
of
C142-C144
attenuates higher
harmonics
of
2nd LO signal from IC7.
Q18
amplifies
2nd IF signals from IC7, and the
output
of
Q18 is fed
to
the IF UNIT.
A part
of
2nd IF signals from IC7 is buffer-amplified
at Q19, then is applied
to
a LPF
consisting
of
L60
and
C114-C116.
These signals are then fed
to
the
[10.7MHz IF OUTPUT] JACK.
4·1·9 TUNED CONTROL CIRCUIT (RF
UN!n
This
circuit
converts the
lock
voltage from the PLL
UNIT
to
tuned voltages
for
the LO trap (tuned notch)
circuit
and
BPF1-BPF4.
Fig. 1 shows the relation among receive frequencies,
the control voltage, the tuned voltage for BPFs and
the tuned voltage
for
the LO trap circuit.
I I j I
~~
::
y:
'.VJ:V1
1
V'
~-
I I I
..Jo
I
CL
> I I
0 I I
0 250 512 762 1000
frequency [MHz]
frequency [MHz]
frequency [MHz]
Fig.1
IC3(A) DC-amplifies the
CV
from the PLL UNIT, and
IC3(A) supplies IC1(A), IC1(B), IC2(A), and IC2(B)
with
control voltage.
IC1(A) supplies
E!PF1
with
a tuned voltage. The gain
and
offset
voltage
of
IC1(A) are
controlled
by
R68
and
R66,
respectively.
IC1(B) supplies BPF2
with
a tuned voltage. 053 and
R157
adjust
the gain
of
IC1(B)
to
fit
the
characteristics
of
BPF2.
IC2(A) supplies BPF3
with
a tuned voltage.
IC2(B) supplies BPF4
with
a tuned voltage. The gain
and
offset
voltage
of
IC2(B) are
switched
by
Q9
and
Q10,
respectively,
to
convert the variations
of
two
PLL
lock
voltages
to
a
continuous
tuned voltage.
IC3(B) supplies a tuned voltage
with
the
LO
trap
(tuned notch) circuit. The
offset
voltages
of
IC3(B)
are switched by
Q11
to
convert the variations
of
two
PLL
lock
voltages
to
a
continuous
tuned voltage.
4·1·10 POWER SOURCE SWITCHING CIRCUIT
(RF
UNln
IC5
switches
the power source
of
each
RF
amplifier
and attenuators by
signals
from the LOGIC UNIT.
Q21
and 052 are voltage converters and regulators
of
the power source for IC5.
An
inverter
circuit
consisting
of
Q12
and
R106
reverses
ATT signals from the LOGIC UNIT
to
make THROUGH
signal.
Q14
and
Q15
are power source
switches
for
RF
relays
RL1
and
RL2.
Q14 and
Q15
turn
ON
via BPF4
signals.
BPF4 signals control IC4, and IC4
outputs
positive
voltage
to
pin 7 (when the receive frequency is
25-511.9999
or
1025-151.9999MHz)
or
pin 1 (when
the receive frequency is
512-999.9999
or
1512-
1999.9999MHz).
4·1·11
AGC BUFFER CIRCUIT (RF
UNln
An
AGC voltage
buffer
Q20 converts AGC voltage
variation
(4-0V)
to
the voltage variation
that
is
required
for
Q1-Q4.
4-1-12
FM (wide) CIRCUIT (IF
UNln
In
FM
(wide) mode, 2nd IF
signals
(10.7MHz) from the
RF
UNIT are impedance-converted at
L1,
and fed
to
Fl1. 2nd IF signals from
Fl1
are
amplified
at
Q2
and
IC1. The gain
of
Q2
and
IC1
is approximately 40dB.
2nd IF signals are then applied
to
IC2, and are
limiter
amplified and then detected
to
obtain
AF signals.
AF signals from IC2 are applied
to
buffer
amplifier
Q4.
This
circuit
switches
AF signals and matches
the level
of
AF signals
with
other
modes.
4-3
4·1-13
AGC
CIRCUIT
FOR
FM
(wide) MODE (IF UNIT)
IC2
(pin
3)
generates a voltage corresponding to the
signal strength
of
IF signals.
030
is a buffer for
DC
voltage. When IF signals are strong,
030
turns
026
ON
to cut
off
the
AGC
voltage.
When IF signals become stronger the
AGC
maintains
the voltage
of
IC2
(pin
3)
at a constant value.
2nd
IF
(FROM Fl1)
Q1
2nd IF
>---'lfV\r-(TO
MAIN
UNIT)
--------+----------AGC
?!:
~4
~
3
0
> 2
M"
.!::
1
a
N
2
> 4
~3
c:
-~
2
()
1
(!)
c(
Fig. 2
Signal
strength
Signal
strength
Fig. 3
4·1-14
2No
IF CIRCUIT
FOR
FM
(narrow),
SSB
AND
AM MODES (IF UNIT)
In
FM
(narrow) mode,
SSB
mode, or
AM
mode, 2nd IF
signals
(10.7
MHz)
are applied to Fl3. Fl3 sufficently
attenuates unrequired signals. The 2nd IF signals
are then amplified at 05. The gain from
L4
to
L5
is
approximately 28dB.
4·1-15
NOISE BLANKER CIRCUIT (IF UNIT)
Part
of
the receive signals from
05
is amplified by
IC4
and detected by
D32
and
D33.
AGC
detector
09
controlsthe gain
of
IC4
via
DC
amplifier029. The time
constant
of
the noise blanker circuit is determined by
R156,
R157
and
C65.
010
turns
ON
or
OFF according
to
the detected pulses. While pulse-type noise is
received,
010
turns 011 ON. The noise blanker
switch consisting
of
D7
and
D9
is reverse-biased,
and the 2nd IF signals are
cut
OFF.
4-4
4·1-16
3Ro
MIXER AND
3Ro
LO
CIRCUIT (IF UNIT)
2nd IF signals from the noise blanker switch are
applied to double-balanced mixer
IC3.
IC3
converts
2nd IF signals (10.7MHz) to 3rd IF (455kHz) signals
utilizing 3rd
LO
signals
(10.245
MHz)
which are
oscillated by
X2
and 012.
Output signals from
IC3
is impedance-converted by
L
13
and
C25,
and is fed to the 3rd IF circuit.
4·1-17
3Ro
IF CIRCUIT (IF UNIT)
3rd IF (455kHz) signals from the noise blanker switch
are then applied to filters corresponding to each
mode.
Fl4 (pass-bandwidth 15kHz) is a
filter
for
FM
(narrow)
and
AM
modes. Fl5 (pass-bandwidth 6kHz) is a
filter for
AM
mode. Fl6 is a
filter
for
SSB
mode. (pass-
bandwidth 2.8kHz.) Cermaic filters are used for
all
of
these.
In
AM
mode, Fl4 and Fl5 can be selected by
JS
on
the IF UNIT.
06
and
07
amplify 3rd IF signals.
R165
is a ther-
mistor for temperature compensation.
4-1-18
BFO
(BEAT
FREQUENCY
OSCILLATOR)
CIRCUIT
AND
SSB
DETECTOR
CIRCUIT (IF UNIT)
A
BFO
(Beat Frequency Oscillator) consists
of
021
and
022
and supplies
to
the
SSB
detectorcircuit a beat
frequency signal.
In
LSB mode, 031 is turned
ON
by the LSB mode
(LSB)
signal from the
EF
UNIT, and the capacitance
of
C133
and
C134
is added
to
L15,
C130,
and
C119
to
shift
the oscillation frequency 3kHz up.
Output signal from the 3rd IF circuit and a beat
frequency signal from the BFO circuit are applied
to the SSB detector circuit consisting
of
D37-
D40.
This circuit detects
SSB
signals.
AF amplifier
024
switches AF signals from the
SSB
detector circuit and 024 matches the level
of
AF
signals with other modes.
4·1·19
FM
(narrow)
DETECTOR
CIRCUIT (IF UNIT)
In
FM
(narrow) mode, 3rd IF signals from
07
are
applied to 019, and then are limiter-amplified by IC5 to
remove
AM
components in 3rd IF signals. Ceramic
discriminator
X3
is used
for
FM
detection to obtain
AF signals.
013
and
023
form a deemphasis circuit and a HPF to
attenuate low frequency (below
200
Hz)
components
in AF signals.
4·1·20
AM
DETECTOR
CIRCUIT (IF UNIT)
In
AM
mode, 3rd IF signals from
019
are detected at
D30.
AF signals from
D30
are amplified by 020.
4·1·21
AGC CIRCUIT FOR FM (narrow), SSB AND
AM MODES (IF UNIT)
In
FM
(narrow) mode, SSB mode and AM mode, a part
of
3rd IF signals from
019
are applied
to
AGC
detector
circuit
D28
to rectify 3rd IF signals. The
DC
voltage
from
D28
is DC-amplified at 018.
In
AM
mode and SSB mode,
016
turns
017
ON
and C89
is applied
to
C91,
resulting in a longer
time
constant
than in FM (narrow) mode. The rise (attack)
time
constant
for
AGC
is
determined by
C89,
C91
and
R114,
and the fall (delay)
time
constant
is determined
by
R113.
The AGC voltage (when the IC-R7000 receives no
signal)
is
offset
by approximately 4V by
R117
and
R116.
018
supplies IF,
RF
and MAIN UNITS
with
the AGC
signal.
4·1·22 5kHz NOTCH CIRCUIT (IF UNIT)
AF signals in each mode are fed
to
a 5kHz notch
filter
consisting
of
IC6(A), R167-R172, and
C135-
C140. This
circuit
attenuates the
5kHz
AF signal
generated by leakage
of
the PLL reference frequency.
In
this
circuit, the
0-factor
can be adjusted by
R171.
IC6
(A)
sends the AF
signals
to
the MAIN UNIT.
o---------
to
:s!.
Qj
-20
>
~
"S
-40
.e
:l
0
u.
-60
<(
I
~
1 5
10
Fig. 4
Audio
frequency
[kHz]
4·1·23 POWER SUPPLY CIRCUIT (IF UNIT)
014
and
015
switch
9V
in
FM
(wide) mode and other
modes. In FM (wide) mode,
015
is
switched
ON,
while
014
is switched
ON
in
other
modes.
Mode signals from the LOGIC UNIT
switch
the AF
amplifier
of
each mode and IF
filters
by the diode
matrix composed
of
D22-D26,
029,
D45
and
D46.
4·1·24 NOISE SQUELCH CIRCUIT
(IF UNIT)
Noise squelch operates in FM (narrow) mode and AM
mode.
A part
of
AF signals from X3 is fed
to
active
filter
IC6(B). The noise
components
of
AF signals pass
through the active filter, and are double voltage
rectified by
D35
and
D36.
The voltage from 035 and
036 is then charged
to
C30.
The voltage
of
C30 is
fed to the squelch
circuit
in the MAIN UNIT as squelch
voltage (SQLV).
(MAIN UNIT)
Noise voltage from the IF UNIT is DC-amplified at
IC7(A). The
output
of
IC7(A) passes through a voltage
limiter
circuit
consisting
of
D28,
D29
and
R116,
and
then enters comparator IC7(B). The reference voltage
of
IC7(B) is varied by the [SQUELCH] CONTROL, and
controls
the squelch threshold level.
4·1·25 METER SQUELCH CIRCUIT (MAIN UNIT)
AGC signal from the IF UNIT
is
applied
to
IC4(A),
and is inversion-amplified. Reference voltage
of
the
meter squelch is varied by the [SQUELCH] CONTROL,
and is applied
to
IC4(B) via
Q9
and
D19.
The meter squelch
is
switched
ON
and OFF depend-
ing on the
output
of
the above comparator.
Fig. 5
4·1·26 CENTER DETECTOR CIRCUIT
FM(wide)
DET
R16
R17
9V
2nd
IF IC2
>------_____,,,VV--.--'W'v---.----M._
(IF UNIT)
9V
'"
"'
a:
N
"'
a:
Fig. 6
-7V
CENT
Output voltage
of
the FM (wide) and
FM
(narrow)
detector
circuits
differ
from each other in the center
frequency
of
IF signals. Therefore, in FM (narrow)
mode the
offset
voltage is applied
to
the
output
of
the
detector
circuit
by
R92-R94,
and
is
adjusted
at
R92
to
the same
output
voltage
of
FM (wide) mode.
Q3
and
Q8
are
DC
voltage buffers.
(MAIN UNIT)
CENT signal is applied
to
a
window
comparator
consisting
of
IC5(A) and IC5(B). The
offset
voltage
is adjusted at
R66
to
make the
window
comparator
output
OV
when the IC-R7000 receives the center fre-
quency
of
the signal. IC5(A) and IC5(B)
output
the
STOP signal
to
the LOGIC UNIT.
4-5
4·1·27 SQUELCH SWITCH CIRCUIT (MAIN UNIT)
The base
of
Q2
receives output voltage from
IC7(B)
via 027 when the noise squelch is activated,
or
output voltage from IC4(B) via 020 when the meter
squelch
is
activated.
Q2
switches
03.
Q6 turns
Q1
(the squelch switch)
ON
and OFF, and
Q1
switches AF
signals. The collector voltage
of
03
is applied
to
the base
of
Q4.
The, and the output
of
Q4
lights up
the
"SIG"
INDICATOR on the FREQUENCY DISPLAY.
4·1·28 VSC (Voice
Scanning
Control)
CIRCUIT
(MAIN UNIT)
This circuit sends the
VSC
signal
to
the LOGIC UNIT
when the IC·R7000 receives signals with AF signal
components.
Output from
Q1
is
fed
to
IC1{A).
An active low-pass
filter consisting
of
IC1(A),
R7-R12,
and
C6-C10
blocks signals higher than 1kHz to prevent
circuit
malfunctions. Output from
IC1(A)
is amplified by
IC1
(B).
02
detects AF signal components in the
output
of
IC1(B), and then the detected voltage
is
charged at
C15.
The voltage
of
C15
is
applied
to
comparator IC2(A). IC2(A) outputs
"HIGH"
output
to pin 7 only when receiving signals with AF signal
components.
Q5
and
Q7
control relay
RL
1 for the [RECORDER-
REMOTE] JACK.
RL
1 turns
ON
when the squelch
opens.
VSC
operation is given priority even when the
squelch opens. When the
VSC
function is activated,
the MO signal form the LOGIC UNIT is applied to 07,
and
RL
1 turns OFF.
4·1·29 SCANNING CONTROL CIRCUIT (MAIN UNIT)
Output from the center detector circuit and the
MUTE
signal from the LOGIC UNIT is applied to the base
of
Q10.
010
turns OFF only when the CENT signal and
MUTE
signal
is
"LOW"
(the squelch opens when the
receiver
is
tuned
to
the center
frequen~y).
When
Q10
turns OFF, a STOP signal
is
sent
to
the LOGIC UNIT
via
R72
and
Q11,
and scanning stops.
Q11
switches the STOP signal OFF when the
[SQUELCH] CONTROL
is
turned fully counterclock-
wise.
4·1·30 METER CIRCUIT (MAIN UNIT)
(a) S·METER CIRCUIT
In
FM
(wide} mode, the METER receives $-meter
(SM)
signals via
D16
when receiving a strong signal,
or
SM
signals from IC4(A) via 015 when receiving a weak
signal.
In
FM
(narrow), SSB
or
AM
modes, the METER receives
SM
signals via
D18.
4-6
(b) CENTER METER CIRCUIT
CENT signal from the IF UNIT is inversion-amplified
at
IC2(B).
Output voltage from
IC2(B)
is applied
to
the
METER
as a center meter
(CM)
signal.
In
SSB
mode,
Q17
turns the center
(CENT)
signal
from
IC5
and the center meter
(CM)
signal from
IC2(B)
OFF.
4·1·31 AUDIO FREQUENCY (AF) AMPLIFIER CIRCUIT
(MAIN UNIT)
Output from
Q1
is
applied
to
IC3(B) (pin
1).
The
[AF GAIN] CONTROL controls the voltage
of
IC3(B)
(pin
13)
to
vary the AF gain.
Output from
IC3(B)
is
amplified up
to
a sufficent AF
level by IC8
to
drive the speaker
SP1.
Output from
Q1
is also applied
to
buffer amplifier
IC3(A).
Output from
IC3(A)
is fed to the [RECORDER·
REMOTE] JACK.
Q18
amplifies SPK signals from the optional IC-EX310
VOICE SYNTHESIZER UNIT, and signals from
Q18
are applied
to
IC3(B).
4·2 POWER SUPPLY CIRCUITS
4·2·1 REG CIRCUIT (REG UNIT)
The
AC
power source from the AC
POWER
SOCKET
is fed to
T1.
Voltage from
T1
is
rectified by 01, next
it
is then fed
to
the stabilization circuit consising
of
Q1, Q2,
and
Q3,
and then
it
is supplied
to
other circuits.
4·2·2 DC·DC CONVERTER CIRCUIT
(DC·DC UNIT)
This circuit converts 13.8V
DC
from the
REG
UNIT
to
-7V,
-12V
and
+24V
DC
voltage. This
circuit
consists
of
a oscillation circuit, a voltage step up/
down transformer, and three regulator circuits.
(MAIN UNIT)
RL2
is a power ON/OFF switch operated by the
optional
RC-12
WIRELESS REMOTE CONTROLLER.
The power control
(POC)
signal from the
RC-12
switches
Q13
and
013
switches
RL
12.
IC6
is
a voltage regulator
that
supplies a stabilized
9V
to
the MAIN UNIT, IF UNIT and
RF
UNIT.
4.3 PLL CIRCUIT (PLL UNIT)
This
circuit
generates the
1st
LO
signals
(778.70-
DATA
(FROM LOGIC
UNIT)
,----------,
I DIVIDER Fret PHASE I
I
I
I
I
1/1024 (5kHz) DETECTOR
PROGRAM·
MABLE
DIVIDE
1/N
LOOP
FILTER
06,
013,
019
I
'---HI
CONTROL
I COUNTER
-~.,-1
COUNTER
1/10,1/11
~:__
_________
_J
X2
J_
X5
025
(51.2MHz)
c::::i
___
...
T
J_
c::::J
Tx1
X3
010
X4
016
XS
025
12MHz
band
(153.6
MHz)
(204.8
MHz)
(256
MHz)
X3
015
X2
012
X2
018
X3
027
1290.699MHz)
for
the
1st
mixer, and 2nd
LO
signals
(256
or
768
MHz)
for
the 2nd mixer.
vco 1
01,
02
vco 2
03,
04
IC8
(307.2MHz)
(409.6MHz)
(768MHz)
(256
MHz)
Fvco
X2
D1,
D2
Fvco
Fe
F1stLo
Fig. 7
4·3·1
REFERENCE OSCILLATOR CIRCUIT
This
circuit
consists
of
crystal
X1
and 024.
The
output
(51.2MHz)
of
Q24 is used
to
make
for
the reference frequency
of
the PLL (Fret), the
LO
frequency in the PLL loop (Fa), and 2nd
LO
signal
(F2nd
LO).
In addition, the
output
of
Q24 is divided
into
1/10
at IC?, and then fed
to
IC3.
4·3·2
2No
LO
CIRCUIT
(a)
256MHz 2nd
LO
SIGNAL CIRCUIT
The signal from
Q24
is multiplied by five at 025,
and passes through
L41-L43,
Q26,
and 029.
Q29
outputs
a 2nd
LO
signal (F2ndL0=256MHz, OdBm).
(b) 768MHz 2nd
LO
SIGNAL CIRCUIT
The signal from Q26 is multiplied by three at 027,
and
028
outputs
the another 2nd
LO
signal
(F2nd
Lo
=768MHz, OdBm).
The band signal
(BS)
switches the above
two
kinds
of
2nd
LO
signals according
to
the receive frequency.
Q20 and
Q21
turns
OFF according
to
the MUTE signal
when in an unlocked condition or by the BLK signal
when in blank memory channel.
4.3.3 PLL LOOP SYSTEM
This
circuit
generates the
1st
LO
signal
for
the
RF
UNIT.
(a)
VCO
CIRCUIT
The
VCO
circuit
consists
of
the >..-resonator
circuit
with
a micro-strip line. This allows for a variable
range
of
389.35-645.35MHz by
two
VCOs.
IC3 controls
oscillation
frequencies
of
this
circuit.
The
VCO
selector
(VS)
signal switches VCOs accord-
ing
to
receive frequencies.
4-7
(b)
PLL LOOP CIRCUIT
The
VCO
output
is amplified by IC10 and passes
through a LPF,
02
and is multiplied by
two
at a
doubler
circuit
consisting
of
01,
02
and
L5.
It is
fed
to
the BPF, and then is applied
to
the MAIN UNIT
as a
1st
LO
signal.
A part
of
the
VCO
output
signals (Fvco) is amplified
by IC5, and is mixed with the
LO
signal in the PLL
loop (Fa) from the
VCO
UNIT
at
IC6 for heterodyning.
The relation
of
Fb, Fvco and Fa is as
follows:
Fb=Fvco-Fa
(See Fig.
7)
The signal from IC6 (Fb) passes through
L9,
L10,
and
01,
and
it
is fed
to
IC4. The
limiter
05
and
06
prevents excessive signal input.
(c)
LO
CIRCUIT IN PLL LOOP
When
FRx
is between
25
and 249.9999MHz or
512
and 761.9999MHz:
The
output
of
X2
(51.2MHz) is multiplied by three at
010. The signal from
010
passes through
L18~L20,
and -011, and then
it
is multiplied by
two
at
012
to
obtain Fe (307.2MHz). The
output
of
012
passes
through
L23
and
L25
and then is fed
to
mixer IC8.
When
FRx
is between 250 and 511.9999MHz
or
762
and 999.9999MHz:
The
output
of
X2
(51.2MHz) is multiplied by four at
016. The signal from
016
passes through
L31~L33,
and
017
and then is
multiplied
by two at
018
to
obtain Fe (409.6MHz). The
output
of
018
passes
through
L36
and
L38
and then is fed
to
mixer IC8.
X1
oscillates 12MHz band signals, and the
DA
signal
from the LOGIC UNIT controls
oscillation
frequencies
of
X1.
Signals from
X1
are multiplied by three
at
015
to
obtain Fd.
Fd varies between
36
and 36.00495MHz in 50Hz
steps.
In
addition, Fd
shifts
±0.75kHz
depending
on the [USB/LSB] SELECTOR SWITCH. The
output
of
the
1st
LO
signal
(F1s1Lo)
is obtained by double
multiplication, so F1
stLO
shifts
±1.5kHz.
Fd and Fe are mixed
at
IC8
to
obtain Fa (the
LO
frequency in the PLL loop). The relation
of
Fa, Fe
and Fd is as
follows:
Fa=Fc+Fd
(See Fig.
7)
4-4
LOGIC CIRCUIT (LOGIC UNIT)
4·4·1
CPU
IC?
(a
high-speed 8-bit COMS
CPU)
controls data such
as mode, receive band, VCOs and expanded
output
ports IC9 and IC10.
The CPU's port addressing is shown in Fig.
9.
4-8
GND
CRYSTAL
CRYSTAL
WR
NC
RXD (Cl-V)
TXD (Cl-V)
SS1
A5
A4
cs
PROG
RES
CTL
CPU PIN
CONNECTION
Fig. 8
4·4·2 MATRIX ALLOCATION
DBO
DB1
DATA
DB2 BUS
DB3
DB4
DB5
DB6
DB?
Y1/A9
Y2/A8
Y3/A7
Y4/A6
Y5/A3
Y6/A2
A1
AO
5V
The matrix allocation is shown in Fig.
10.
Y1
Y2 Y3
KEYBOARD
[TS]
Y4 Y5 Y6
Cl-V
ADDRESS
Cl-V
TRANSCEIVE
~--!+--..>..j~-+-...>....~-+---"--~++---"--t---t-->-~-+-.>.~DB5
Cl-V
[VSC] BAUD RATE
(MAIN
UNIT]
Fig. 9
Downloaded by
Amateur Radio Directory
(a)
Y1--+
D80-D83
(KEYBOARD,
MEMORY-CH
ENTER)
Following is a matrix
for
the KEYBOARD, MEMORY-
CH
ENTER and the optional
RC-12
WIRELESS
REMOTE CONTROLLER.
~
DBO
DB1
DB2 DB3 HEX
y CODE
1 H L L L 1
2 L H L L 2
3 H H L L 3
4 L L H L 4
5 H L H L 5
6 L H H L 6
7 H H H L 7
8 L L L H 8
9 H L L H 9
0 L H L H A
*1
MEMORYCH
ENTER
H H L H B
• L L H H c
ENT H L H H D
*2
CE
L H H H E
*1:
Used in [MEMORY CH] CONTROL.
*2:
Used in the optional
RC-12
WIRELESS REMOTE
CONTROLLER.
Table 5
(b) Y1--+ D84 (DIAL UP/DOWN)
When a TUNING CONTROL
clock
signal is input, the
following results
will
occur.
Y1--+
084
RESULT
H The receive frequency inceases.
L The receive frequency decreases.
Table 6
(c)
Y1
--+
D85-
7 [TS]
This matrix sets frequency steps.
~
DB5 DB6 DB7
T
0.1
kHz L L L
1kHz
H L L
5kHz L H L
10kHz H H L
12.5kHz L L H
25kHz H L H
Table 7
(d) Y3--+
DB0-1
(FREQUENCY UP/DOWN)
This matrix increments receive frequencies
for
the
optional
RC-12
WIRELESS REMOTE CONTROLLER.
(e) Y3--+ DB2 (SQUELCH STOP)
This matrix stops the scan when the squelch opens.
(f)
Y4--+
D86-7
[SCAN·DELAY]
This matrix sets the scan delay time.
~
DB6 DB7
G
OFF H L
5
(seconds)
L H
15
(seconds)
H H
oo (infinity) L L
Table 8
(g)
Y6
--+
DB0-4
(Cl·V ADDRESS)
This matrix sets the address
for
the *Cl-V. The
desired address for IC-R7000 may
be
1
to
31
and
consists
of
5 bits.
*Cl-V: ICOM Communication lnterface-V.
(h)
Y6
--+
DB5
(Cl·V TRANSCEIVE)
This matrix sets the transceive operation
for
the Cl-V.
(i)
Y6--+
DB6-7
(Cl·V BAUD RATE)
This matrix sets the baud rate.
~
DB6
T
76800 L
9600 H
1200 L
300 H
Table 9
LOGIC
UNIT J17
DB7
L
L
H
H
DB7•D181'4111
DB6
•D171'411!
DB5
•D161'4111
DB4
,D151'411!
DB3
,D141'4111
DB2
•
D13
1'4111
DB1
•
D121'4111
~
BAUD
(1200BAUD)
PS
0 0
~
TRANSCEIVE (ON)
P7
0 0
rBJ
P6
0 0
0 0
DBO
1 D
11
1'4111
0 0
Fig.10
4.4.3
CPU
RESET
CIRCUIT
ADDRESS
(08)
The
CPU
reset
circuit
detects
the power supply voltage
to
reset the
CPU.
13.BV
IC7
Fig.
11
4-9
4.4.4 RECORDING SPEECH CIRCUIT (LOGIC UNIT)
When the STOP signal from the MAIN UNIT is applied
to
IC3(A), the
output
of
IC3(A) becomes
"LOW"
for
approximately 1sec. from the rise
of
the STOP signal.
When the [RECORDER-SPEECH] SWITCH
is
ON,
after
1sec. from the rise
of
the STOP signal (if the
VSC
signal
is
"HIGH"),
05
and
04
are
switched
on, and
the SPKS signal
is
output.
5V
D7
EQ4C
C13
STOP~------+----.----~
>'--H---.--.....---spKs
~
N
a:
Fig.12
5V
l!RECORDER-SPEECHJ
OFF
: o<J
I
I
I
L
___
_
I
DB~
[VSC)
OFF
4.4.5 SCAN SPEED CONTROL CIRCUIT (LOGIC UNIT)
This
circuit
accelerates the speed
of
the MEMORY
CHANNEL SCAN, SELECTED MODE SCAN and
SELECTED MEMORY SCAN.
By the PRIO signal, the
output
of
IC16 remains
"HIGH"
even while receiving the another frequency.
When 021 is switched
ON
by a PRIO
or
a
PRO
signal,
C7
is
input in parallel
with
CS,
and the
clock
fre-
quency will decrease.
5V
LOGIC
UNIT!
[SCAN-SPEED)
064
Fig.13
4·4·6
81
-84, BH, BS AND
VS
SIGNALS
co:
ct::
isw2
UNIT
,....
~-----------
ii:
The LOGIC UNIT supplies
following
signals
with
the
PLL UNIT and
RF
UNIT.
RECEIVE
FREQUENCY
SIGNALS
FRX
[MHz]
B1
B2 B3 B4
BH
BS
vs
25-
89.9999 H L L
1025-1089.9999 L H
90-
249.9999 L H L L L
1090-1249.999~
- -
250-
511.9999 L L H H L
1250-1511.9999
512-
761.9999 L L L L H
1512-1761.9999 H -H -
762-
999.9999 L L L H L
1762-1999.9999
B1-B4,
BH: BPF signals
BS: Band signal
VS: VCO selector signlal
Table 10
4-10
4·5 DISPLAY CIRCUIT (DISPLAY
UNln
This
circuit
is
consists
of
a fluorescent display tube
DS1,
display tube drivers IC1, IC2 and a DC-DC con-
verter circuit.
4·5·1
FREQUENCY DISPLAY CIRCUIT
IC1
drives the
display
of
frequencies while IC2 drives
the display
of
memory channels.
Signals from the LOGIC UNIT and the MAIN UNIT
control
IC1
and IC2.
4·5·2 MODE DISPLAY CIRCUIT
IC2 allocates
T3-T7
for five types
of
data, and IC2
send the segment
data
"1"
to
R19.
EXAMPLE:
The AND
circuit
of
"Q
" and
"T7''
is configured
with
R18
and
R19.
05
and
010
are switched
ON
by the
timing
of
"T7"
only
when
"Q"
is at
"HIGH",
and
then the letter
"SCAN"
lights
up.
5V
T7
R19
Fig. 14
4.5.3 PRIORITY DETECTOR CIRCUIT
Both the segment
"c"
and
"d"
are turned OFF
simultaneously
only
when
DS1
displays the letter
"P".
In
this
case, IC2
switches
014
OFF and IC2
sends the
T1
signal
to
the LOGIC UNIT as a PRIO
signal. a
I g
1·
ef
d
v,
' \
Fig.15
R41
016
T1
014 IC2
c
PRIO c d
Fig. 16
4·6 KEYBOARD CIRCUIT (KEYBOARD UNIT)
This
circuit
consists
of
the keyboard
circuit
and the
remote control circuit.
The signals from photo-diode
D28
are
amplified
by
IC1
and
01.
01
outputs
the remote (REM) signal
to
the LOGIC UNIT.
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