Icom IC-2SET User manual

o
ICOM
SERVICE
MANUAL
144MHz FM TRANSCEIVER
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INTRODUCTfON
This service manual describes the latest service information for the
IC-2SAT/SET 144 MHz FM TRANSCEIVER at the time of going to press.
5versions of the IC‘2SAT/SET have been designed. This service manual
covers each version.
VERSION NUMBER VERSION MODEL
if 02 Europe IC-2SET
if04 Italy
#05 U.S.A,
#07 Ausiralia IC-2SAT
#09 Asia
To upgrade quality, any electric or mechanical pari and internal circuits are
subject to change without notice or obligation
DANGER
NEVER connect the transceiver to an AC outlet or to aDC power supply that
uses more than 16 V. This will ruin the transceiver.
DO NOT expose the transceiver to rain, snow or any liquids,
DO NOT reverse the polarities of the power supply when connecting the
transceiver.
DO NOT apply an RF signal of more than 20 dBm (100 mW) to the antenna
connector. This could damage the transceiver's front end,
ORDERING PARTS
Be sure to include the following four points when ordering replacement parts;
1.10-digit order numbers
2. Component part number and name
3. Equipment model name and unit name
4. Quantity required
<SAMPLE ORDER
>
1150000730 1C SCI 096 1C-3SAT MAIN UNIT 5pieces
8810005720 Screw PH BO W2 x20 2K IC-2SAT Rear panel 10 pieces
Addresses are provided on the inside back cover for your convenience.
REPAIR NOTE
1. Make sure aproblem is internal before disassembling the transceiver.
2. DO NOT open the transceiver until the transceiver is disconnected from a
power source.
3. DO NOT force any of the variable components. Turn them slowly and
smoothly.
4. DO NOT short any circuits or electronic parts, An Insulated tuning tool
MUST be used for all adjustments,
5. DO NOT keep power OIM for along time when the transceiver is defective.
6. DO NOT transmit power inlo asignal generator or asweep generator.
7. ALWAYS connect a30 dB"“40 dB attenuator between the transceiver and
adeviation meter or spectrum analyzer when using such test equipment.
8. READ the instructions of test equipment thoroughly before connecting
equipment to the transceiver.

TABLE OF CONTENTS
SECTION 1SPECIFICATIONS 1—1
SECTION 2INSIDE VIEWS 2—1
SECTION 3BLOCK DIAGRAM 3—1
SECTION 4CIRCUIT DESCRIPTION 4—1~6
4
-1RECEIVER CIRCUITS 4—1
4-2 TRANSMITTER CIRCUITS 4—2
4-3 PLL CIRCUITS 4—3
4-4POWER SUPPLY CIRCUITS 4—4
4-5OTHER CIRCUITS 4—4
4-6CPU PORT ALLOCATIONS (LOGIC UNIT) 4—5
SECTION 5MECHANICAL PARTS AND DISASSEMBLY 5—1~2
5-1FRONT PARTS 5—1
5-2CHASSIS PARTS 5—2
SECTION 6ADJUSTMENT PROCEDURES 6—1~5
6-1PREPARATION BEFORE SERVICING 6—1
6-2 PLL ADJUSTMENT 6—2
6-3 RECEIVER ADJUSTMENT 6—3
6-
4TRANSMITTER ADJUSTMENT 6—4
SECTION 7BOARD LAYOUTS 7-1-10
7-1LOGIC (LGC) UNIT 7—1
7-
2MAIN (MIN) UNIT 7—4
7-3 MBD AND AF UNITS 7—6
7-4 10 AND MIC UNITS 7—7
7-5 DET AND REG UNITS 7—8
7-6 RF AND APC UNITS 7—9
7-7 PLL AND PRT UNITS 7—10
SECTION 8PARTS LIST 8-1-7
SECTION 9OPTIONAL UNITS 9-1-3
9-1UT-50 TONE SQUELCH UNIT 9—1
9-2 UT-51 TONE ENCODER UNIT 9—2
9-3 UT-49 DTMF DECODER UNIT 9—3
SECTION 10 VOLTAGE DIAGRAM 10 —1

SECTION 1SPECIFICATIONS
GENERAL
•Frequency coverage
•Mode
•Selectable tuning step
•Memory channels
•Antenna impedance
•Power supply requirement
•Current drain (at 13.8 VDC)
•Usable temperature range
•Frequency stability
•Dimensions
•Weight
TRANSMITTER
•Output power (at 13.8 VDC)
•Modulation system
•Max. frequency deviation
•Spurious emissions
•Microphone impedance
RECEIVER
•Receive system
•Intermediate frequencies
•Sensitivity
•Selectivity
•Spurious rejection ratio
•Audio output power
•Audio output impedance
MODEL VERSION FREQUENCY
COVERAGE
IC-2SAT U.S.A.
140.00~150.00 MHz*
Asia
IC-2SET Italy
IC-2SAT Australia 144.00~148.00 MHz
IC-2SET Europe 144.00—146.00 MHz
‘Specifications apply to only 144.00~148.00 MHz.
F3 (FM)
5, 10, 12.5, 15, 20, 25 and 50 kHz
48 plus acall channel
50 0
6~16 VDC negative ground or battery packs BP-81 ~BP-85 or battery case BP-90
Receive 16mA (power saved)
250 mA (max. audio output)
Transmit 650 mA (LOW 1)
1500 mA (HIGH)
-10 “C~-F60 °C(-f 14 °F~-F140 T)
±15 ppm (-10 “C-+60 °C)(-M4 T-+140 ”F)
49 (W) X102.5 (H) X35 (D) mm
1.9 (W)x4.0 (H)x 1.4 (D) in
(Projections not included)
280 g(9.9 oz)
High 5.0 W
Low 3.5/1 .5/0.5 W(selectable)
Variable reactance frequency modulation
±5 kHz
Less than -60 dB
2kO
Double-conversion superheterodyne
1st 30.875 MHz
2nd 455 kHz
0.18 pV for 12 dB SINAD
More than 15kHz/-6dB
Less than 30kHz/-60dB
More than 60 dB
More than 200 mW at 10 %distortion with an 8Qload
80
All stated specifications are subject to change without notice or obligation.
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1—1

SECTION 2INSIDE VIEWS
MAIN UNIT
RF amplifier circuit (RF UNIT)-
-1st IF filter (Fit :30M16B)
AF amplifier circuit (AF UNIT)
ARC circuit fAPC UN1T)-
2rd LO crystal (X2: CR-214 30.42 MHz)
Demodulator circuit {DET UNIT)
Power module {IC1 :SC1096)=
Microphone amplifier circuit {MIC UNIT)
PLL circuit (PLL UNIT)
Internal NiCd battery^
(BT1: P^03ER/F23G1)
Charging circuit {PRT UNIT)-
LOGIC UNIT
CPU clock
{XI; CSB800J220 798.642 kHz) -CPU (IC1: HD404608A21H)
Microphone (MCI :WM-62A)-
Lifhium backup battery^
(BT1: CL202O-1VC)
Buili4n clock crystal
{X2: DT-26S 32.768 kHz)
CPU resetyCPU power supply circuit
(RES BOARD)
Keyboard (LGC BBOARD)

DET
UNIT
I
main
unit
SECTION 3BLOCK DIAGRAM
3—1
LOGIC
UNIT

SECTION 4CIRCUIT DESCRIPTION
4-1 RECEIVER CIRCUITS
4-1-1 ANTENNA SWITCHING CIRCUIT
(MAIN AND APC UNITS)
Received signals enter the antenna connector and pass
through aiow-pass filter (L2~L4, C21~C25). The signals
are applied to the antenna switching circuit (D7, D9, L5,
L6, and C26~C28) and then to the RF UNIT via the RFIN
signal line. The antenna switching circuit employs a
two-stage A/4-type diode switching system.
The antenna switching circuit functions as alow-pass
filter while in receiving and becomes very high impedance
while in transmitting.
4-1-2 RF CIRCUIT (RF UNIT)
The signals from the antenna switching circuit pass
through abandpass fiiter (LI, D2), and are applied to
the RF amplifier (Q1, Q2).
Amplified signais are reappiied to the other bandpass
filter (L2, L3, D4, D5) to suppress unwanted signals.
The signals are applied to the 1st mixer circuit (MAIN
UNITQ1).
D2, D4 and D5 are varactor diodes that track the band-
pass filters and are controlled by the PLL lock voltage.
These diodes tune the center frequency of the bandpass
filters for wide bandwidth reception and good image
response rejection.
4-1-3 1ST MIXER CIRCUIT (MAIN UNIT)
The signals from the RF circuit are mixed with the 1st LO
signal from the PLL UNIT to produce a30.875 MHz 1st
IF signal.
4-1-4 1ST IF CIRCUIT (MAIN AND DET UNITS)
After passing through the matching circuit (LI), the 1st IF
signal is applied to apair of crystai filters (FI1) to suppress
out-of-band signals. The 1st IF signal enters the DET
UNIT and is amplified at the IF amplifier (Q2) and then
applied to the 2nd mixer circuit.
4-1-5 2ND IF AND DEMODULATOR
CIRCUITS (DET UNIT)
The 1st IF signal from Q2 is appiied to the 2nd mixer
section of IC1, and is mixed with the 2nd LO signal to be
converted to a455 kHz 2nd IF signal.
IC1 contains the 2nd mixer, local oscillator, limiter
ampiifier and quadrature detector circuits. The local
oscillator section and X2 generate 30.42 MHz for the
2nd LO signal.
The 2nd IF signal from the 2nd mixer (101, pin 4) passes
through the ceramic filter, FI1, where unwanted signals
are suppressed. It is then amplified at the limiter amplifier
section (Id, pin 6) and applied to the quadrature detector
section (101, pin 10 and ceramic discriminator XI) to
demodulate the 2nd IF signal into an AF signal.
AF signal output from Id pin 1 1 is applied to the squelch
circuit and de-emphasis circuit (R7, 024, 025). This de-
emphasis circuit is an integrated circuit with frequency
characteristics of -6 dB/octave. The resulting signal is
applied to the AF amp, optional tone squelch and optional
DTMF decoder circuits.
RECEIVER CIRCUIT BLOCK DIAGRAM
4—1

4-1-6 AF AMP CIRCUIT (AF AND VR UNITS)
The AF signal is applied to Q1 and Q2 on the AF UNIT.
Q1 is an active filter that functions as ahigh-pass filter
to suppress tone signals for the tone squelch operation.
Q2 is also an active filter that functions as alow-pass
filter to suppress higher noise signals.
The filtered signal is applied to the [VOL] control (R1)
on the VR UNIT via the AF mute circuit (Q3). When the
squelch is closed, Q3 cuts the AF signal as the AF mute
switch. The AF signal is power-amplified at the AF
power amplifier (ICt) to drive the speaker.
The AF voltage regulator (Q4~Q6) supplies power to
the AF power amplifier. The AFS signal from the MAIN
UNIT controls Q6 and mutes AF output while receiving
no signal or no specified tone/DTMF signal.
4-1-7 SQUELCH CIRCUIT (DET UNIT)
Some of the noise components in the AF signal from IC1
pin 11 are applied to IC1 pin 13 via C11, R8, Cl 3and
C14. The [SQL] control (R2) on the VR UNIT adjusts the
pin 13 input level.
The active filter section in IC1 amplifies noise components
of frequencies of 20 kHz and above, and outputs the
resulting signals from pin 14. Output signals are rec-
tified by D1 and are converted to DC voltage.
The rectified voltage triggers the squelch switch (Q1).
The coliector of Q1 outputs the squelch signal. The
signal is applied to the CPU (IC1, pin 27) on the LOGIC
UNIT through the BUSY signal line. The CPU outputs the
RMUTE and BUSY LED signals.
The RMUTE signal, decoded at the output expander
(IC1) on the 10 UNIT, activates the AF mute circuit (03)
on the AF UNIT to cut the AF signal. The BUSY LED
signal is applied to 01 on the LOGIC UNIT, turning OFF
the receive indicator.
4-2 TRANSMITTER CIRCUITS
4-2-1 MICROPHONE AMPLIFIER (MIC UNIT)
AF signals from the built-in condenser microphone or
from the [MIC] jack are applied to IC1 pin 3, and are
pre-emphasized to -F6 dB/octave through C6 and R4
connected to pin 2. IC1 functions as the microphone
amplifier and the limiter.
The output signals from IC1 pin 1pass through the
splatter filter circuit (IC1 pins 5and 6) where signals
of 3kHz and above are attenuated. IC1 pin 7then
outputs the signals. The signals are applied to the
modulation circuit (PLL UNIT, D2) in the VCO to produce
an FM signal.
The VCO circuit (02, L2, D2) on the PLL UNIT oscillates
the transmit frequency with AF signal modulation.
4-2-2 DRIVE AMPLIFIER (MAIN UNIT)
The VCO output, buffer-amplified at 05 on the PLL
UNIT, is applied to the the transmit/receive switching
circuit (D14) on the MAIN UNIT. The VCO output is then
amplified at the predrive amplifier (07) and the drive
amplifier (06).
The voltage controlled by the APC circuit is applied to the
collector of 06 and 07 to protect the RF power module
from damage by an antenna mismatch.
4-2-3 RF POWER AMPLIFIER (MAIN UNIT)
IC1 is apower module which provides stable 5Woutput
power.
An RF signal from the drive amplifier (06) is applied to
IC1 pin 1. The amplified signal is output from pin 4,
and applied to the antenna connector through the diode
switching and low-pass filter circuits.
TRANSMITTER CIRCUIT BLOCK DIAGRAM
Fig. 2
4—2

4-2-4 APC CIRCUIT (MAIN AND APC UNITS)
The APC circuit protects the power module (IC1) from
amismatched output load and selects HIGH and LOW
output power.
The output power level from the power module (IC1) is
detected at the APC detector (D10~D12). When antenna
impedance is matched at 50 Q, the detected level is
at aminimum. However, when antenna impedance is
mismatched, the detected voltage is higher than when
matched.
When the antenna impedance is mismatched, the base
voltage of Q3b (APC UNIT) Is higher than the other base
voltage of Q3a (reference voltage). Q3b decreases the
collector current of Q1 using Q2. Collector current of
Q1 is used at the drive amplifiers (Q6, Q7) on the MAIN
UNIT. Hence, when the antenna Impedance is mis-
matched, the output power is decreased.
The output power selecting circuit uses the APC circuit.
The PCON voltage from the lO UNIT shifts the reference
voltage, changing the output power to HIGH or LOW
1~3.
4-2-5 ANTENNA SWITCHING CIRCUIT
(MAIN UNIT)
When transmitting, D7 and D9 are turned ON. The RF
output signal is not applied to the receiver circuit, passing
through D9 and C60, the low-pass filter (L2~L4, C21
~C25) and then to the antenna. The low-pass filter
suppresses high harmonic components.
4-3 PLL CIRCUITS
4-3-1 GENERAL (PLL UNIT)
The PLL circuit, using aone chip modulus prescaler (IC1),
directly generates the transmit frequency with the Tx
VCO (Q2) and the 1st LO frequency with the Rx VCO (01).
The modulus prescaler (IC1) sets the dividing ratio based
on serial data from the CPU, and compares the phases
of aVCO signal and the reference oscillator frequency.
It detects the out-of-step phase and outputs it. The
reference frequency is oscillated at XI
.
4-3-2 REFERENCE OSCILLATOR CIRCUIT
(PLL UNIT)
Areference frequency is produced by the local oscillator
section of IC1 and XI. C22 provides frequency control.
4-3-3 LOOP FILTER CIRCUIT (PLL UNIT)
Phase-detected signals from IC1 pin 13 are converted to
DC voltage by alag-lead loop filter (R17, R18, C28, C29).
The frequency at which the VCO oscillates is controlled
by varactor diodes (D1, D2). DC voltage (PLL lock
voltage) is provided through the buffer amplifier (06).
01 0provides Rx bandpass filter tuning.
PLL CIRCUIT
IC1 M54959FP
PLL
OUTPUT
XI Fig. 3
4-3-4 VCO CIRCUIT (PLL UNIT)
IC-2SAT/SET has 2VCO circuits for transmitting and
receiving. IC1 pins 10 and 11 output control signals
for selecting the receive VCO circuit (Q1, LI, D1) or
transmit VCO circuit (02, L2, D2). Varactor diodes (D1,
D2) provide frequency control. The buffer amplifiers
(Q3~Q5) do not affect the PLL output signal from VCO
oscillation. 07 selects the transmit or receive VCO
circuit.
4-3-5 UNLOCK SENSOR CIRCUIT (PLL UNIT)
When the PLL circuit is unlocked, IC1 pin 14 is “HIGH”
and the “HIGH" signal is applied to the CPU pin 7as an
unlock signal.
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3

4-4 POWER SUPPLY CIRCUITS
4-4-1 VOLTAGE LINES
LINE DESCRIPTION
Vcc The internal or attached battery pack voltage
or external DC power passed through the
power switch.
-1-5 Common 5Vconverted from the Vcc line at Q1
and Q2 on the REG UNIT using IC1 as the
reference voltage.
-I-5S 5Vcontrolled by the power saver function.
This voltage is converted from Vcc at 03 and
04 on the REG UNIT using IC2 output as the
reference voltage.
R-I-5S Receive 5Vcontrolled by the power saver
function and SEND signal line. This voltage is
converted from Vcc at 05 and 06 on the REG
UNIT using IC3 output as the reference
voltage.
T-l-5 Transmit 5Vcontrolled by the TMUTE signal
line. This voltage is converted from Vcc at 04
and 05 on the APC UNIT.
AF 7VAF amp power source controlled by the AFS
signal line. R14/R15 provides reference
voltage.
4-4-2 CPU POWER SUPPLY CIRCUIT
(LOGIC UNIT)
When the power switch is turned OFF and the
internal/externai battery pack is discharged, avoltage is
appiied to the CPU (IC1) pin 73 via R29 from the iithium
backup battery (BT1) installed In the transceiver to provide
backup for the memory contents.
When the internai or attached battery pack voltage or
external DC power is applied to the transceiver, BT1 is
charged using the current regulator (C3).
4-4-3 +5S AND R+5S SWITCHING
CIRCUITS (REG UNIT)
The IC-2SAT/SET has apower saver to reduce current
consumption to approx. 1/4.
The PSC (Power Saver Control) signal is applied to IC2.
IC2 controls +5S regulator (G3, C4, D1) to turn CN and
CFF +5S voltage.
PSC and SEND signals are applied to ICS. ICS controls
R-t-5S regulator (05, Q6, D2). R+5S turns OFF during
power saved period or transmitting.
4-4-4 CHARGING CIRCUIT (PRT UNIT)
Voltage from the [DC 13.8V] jack is applied to current
control circuit (01, 02, D5, D6) to charge an internal or
attached battery pack (except the BP-85).
When the external battery pack is attached, the current
from D2 charges the attached battery pack. When the
external battery pack is removed, the current from D2
charges the internal battery pack.
The mechanical switch (MP7) selects the battery packs.
This circuit charges one of the battery packs in approx. 15
hours.
Over voltage protector (D4) decreases the transceiver
circuit damage from over voltage and reverse polarity
connections of the power supply.
4-5 OTHER CIRCUITS
4-
5-1 S/RF INDICATOR CIRCUIT
(DET, MAIN AND LOGIC UNITS)
Aportion of the 2nd IF signal is output from IC1 pin 12
on the DET UNIT via the SD signal line. The signal is
rectified at D1 on the MAIN UNIT to obtain an S-indicator
signal. The S-indicator signal is applied to IC2b pin 5
on the LOGIC UNIT.
IC2b pin 6receives an S-indicator reference signal from
the CPU KEYSO—3 terminals via the D/A converter (R11,
R37~R40). The CPU terminals increase the reference
signal level.
When the D/A converted level becomes greater than the
5-
indicator level, IC2b pin 7becomes “LOW.” The CPU
detects the signal strength level using the KEYS0~3
terminal outputs and indicates the signal strength level
on the function display when receiving the “LOW” signal.
While transmitting, the S/RF indicator indicates the
selected output power.
SINDICATOR CIRCUIT
4-5-2 DISPLAY BACKLIGHT CIRCUIT
(LOGIC UNIT)
When the [LIGHT] switch is pushed, pin 77 of the CPU
outputs “HIGH.” The signal is applied to 01 to light up
the backlight LEDs (DS2, DS3).
4—4

•OUTPUT PORT •OUTPUT EXPANDER (10 UNIT, IC2)
PORT NUMBER PIN
NUMBER DESCRIPTION
DO
[LAMPO]
77 Becomes "HIGH” when the
backlight LEDs light up.
D1
[BUSY LED]
78 Outputs asignai for iighting up in
green the transmit/receive
indicator. This port becomes
“LOW” while receiving.
(squeich opens)
D2
[TONE OUT] 79 Outputs a1750 Hz tone signai.
(IC-2SET oniy)
D3
[TOE]
80 Outputs an enable signal for the
UT-49.
D6-D9
[KEYSO-
KEYS3]
3~6 Outputs astrobe signal for the
keyboard, initial and key matrices
and D/A converter counting signai
alternateiy in an intervai.
ROO
[SOK]
15 Outputs ciock signals for serial
data.
R01
[lO STB]
16 Outputs astrobe signal for serial
data to the expander ICs.
R02
[SDATA]
17 Outputs serial data synchronized
with the SOK signal.
R03
[PLL STB]
18 Outputs astrobe signal for serial
data to the PLL 1C.
•OUTPUT EXPANDER (10 UNIT, IC1)
PORT NUMBER PIN
NUMBER DESCRIPTION
Q2, 03
[BA2, BA3]
5, 6Outputs acontrol signal for the RF
bandpass filter.
05, 06
[POW 1
,
POW2]
13, 14 Outputs acontrol signal for the
output power selecting circuit.
This signal is converted into PCON
voltage (APC reference voltage)
using the D/A converter (R2~R6).
PORT NUMBER PiN
NUMBER DESCRiPTiON
01
[AF ON]
4Outputs an AF mute signal for AF
power amplifier.
02
[MiC MUTE] 5Outputs amicrophone mute
signai. When transmitting atone
signai, the MiC signai iine goes to
ground.
03
[RMUTE]
6Outputs areceive mute signal for
the AF mute circuit. When
emitting abeep tone, this port
outputs the mute signai and the AF
ON port does not output it.
04
[TMUTE]
7Outputs acontrol signal for T+5 V
regulator.
05
[SEND]
14 Outputs transmit/receive switching
signals. This port becomes
“LOW” whiie transmitting.
06
[PSC]
13 This port becomes “HiGH” while
the power saver function is
activated.
07
[CPC]
12 Outputs acontroi signai to cut off
the ioop fiiter whiie the power saver
function is activated.
08
[MODE]
11 Outputs amode signai.

4-5-3 1750 Hz TONE CALL CIRCUITS
(LOGIC UNIT)
Only the IC-2SET is equipped with this function.
When the [PIT] switch is quickly pushed 2times or
when the [PTT] switch is pushed with the [LIGHT] switch,
pin 79 of the CPU (TONE OUT) outputs a1750 Hz tone
signal. R15 adjusts the 1750 Hz tone deviation. The
signal is aiso output to the AF UNIT via R12.
4-5-4 SUBAUDIBLE TONE ENCODER
CIRCUIT
This function can be activated only when an optional
UT-50 TONE SOUELCH UNIT or UT-51 PROGRAMMABLE
TONE ENCODER UNIT is installed.
Atone signal is applied to the splatter filter circuit on
the MIC UNIT via the TONE signal line. RIO on the
UT-50 and R5 on the UT-51 adjust the subaudible tone
deviation.
4-5-5 DTMF ENCODER CIRCUIT
(LOGIC UNIT)
This function can be activated only when the matrix
KEYS1->KEYI1 is OPEN, (an optional UT-49 DTMF
DECODER UNIT is installed.)
Pins 70 and 71 of the CPU (TONEC/TONER) output
aDTMF code signal. R16 adjusts the DTMF code signal
deviation. The signal is also output to the AF UNIT via
R17.
4-5-6 CPU RESET CIRCUIT (LOGIC UNIT)
103 detects -F5 voltage. When the -F5 voltage line
becomes 5V, 103 turns INTO “HIGH” and the CPU (101)
restarts operation.
The CPU is reset when IC1 pin 76 becomes “HIGH.”
The AND gate 10 (104) outputs areset signal when
both input terminals are “HIGH.” One terminal is
“HIGH” when the [MONIj switch is pushed and the
other (INTO line) is “HIGH” when the power is turned ON.
RESET CIRCUIT
+5
4-5-7 TRANSMIT/RECEIVE INDICATOR
CIRCUIT (LOGIC UNIT)
The transmit/receive indicator (DS4) uses a2-input LED
and lights up in red or green.
The indicator lights up in red as the transmit indicator
while transmitting using the T-F5 voltage.
The indicator lights up in green as the busy indicator
while the squelch opens using CPU pin 78 output via
the inverter (02).
4-5-8 CLOCK OSCILLATOR CIRCUIT
(LOGIC UNIT)
IC1 oscillates the 798.642 kHz CPU system clock signal
using XI. 101 oscillates the 32.768 kHz clock signal for
the built-in clock using X2.
4-6 CPU PORT ALLOCATIONS
(LOGIC UNIT)
•INPUT PORT
PORT NUMBER PIN
NUMBER DESCRIPTION
D4
[PTT]
1Inputs asignal on the PTT line.
This port becomes “LOW” when
the PTT switch is pushed.
D5
[SIN]
2Inputs S-meter-compared signal
from IC2b to indicate the CPU
counting ievel to the S-indicator in
the function display.
DIO
[UL]
7Detects aPLL unlock signal.
When the signal is “HIGH," the PLL
is uniocked.
D12, D13
[DIAL
UP/DN]
9, 10 input port for the up/down signai of
the tuning controi.
R10-R13
[KEYIO-
KEYI3]
19—22 These are input ports for the initiai
and key matrices.
R20-R23
[KEYRO-
KEYR3]
23-26 These are input ports for the
keyboard and DTMF code from the
UT-49.
R30
[BUSY]
27 Detects asqueich signai. The
signai is “HiGH” when the squeich
opens.
R31
[OPT]
28 Input port for an optional unit.
This port becomes “HIGH” when
the tone squelch opens. (UT-50)
This port becomes “LOW” when
the UT-51 is installed.
R32
[INTO]
29 Detects asignal for the standby
mode of the CPU. The CPU enters
the standby mode when the port
becomes “LOW.”
R33
[INTI]
30 The CPU decodes received DTMF
code when this port becomes
“LOW.”
4—5
Fig. 5

5-1 FRONT PARTS
ORDER
NO. DESCRIPTION
8930016400 756 LOGIC Ground spring plate
8810001700 Screw PH BO No. 0-3 M1.4x3
8930015790 PIT Ground spring plate
8930014880 752 P.C. Board holder
2230000770 Switch [F] SW-104 (SKHUPE004B)
2230000770 Switch [PTT] SW-104 (SKHUPE004B)
2260001150 Switch (H/UDTMF]SW-103 (SKHUPC007B)
2260001150 Switch [MONi]SW-103 (SKHUPC007B)
8930014940 752 MIC holder
7700000860 Microphone WM-62A
8010009070 756 Reflector plate
8930015920 LCD contact strip SRCN-756
6910003910 LCD LCD2439 (inci. shield)
8930015960 756 LCD holder
ORDER
1NO. DESCRIPTION
8930016410 756 Speaker ground lag
8810005740 Screw FH BO No. 0 M2x3
8930014810 752 Speaker plate
2510000450 Speaker EAS-3P123D
8810001700 Screw PH BO No. 0-3 M1.4X3
8510006050 Key shield
8010009080 756 Keyboard
8610005970 Knob K138 [H/L/DTMF], [MONI]
8210005090 756 Front panel (A) IC-2SAT
(incl. Front plate and 756 lens)
8210005100 756 Front panel (B) IC-2SET
find. Front plate and 756 lens)
8810000530 Screw PH No. 0M2 X5ZK
Screw abbreviations PH :Pan head
ACCESSORIES
BO :Self-tapping screw ZK: Black
UBEL ORDER
NUMBER NO.
8010008970
El Optional product
8930014960
®8010008620
8810005730
DESCRIPTION
Screw abbreviations BuH ;Button head
BS; Brass ZK: Black

LABEL
NUMBER ORDER NO. DESCRIPTION QTY. LABEL NUMBER ORDER NO. DESCRIPTION QTY.
©8610005790 Knob N147 [TUNING] 1(0) 8510005850 752 PLL case 1
@8610005780 Knob N146 [SQUELCH], [PWR/VOL] 28510005820 751 PLL cover 1
®8830000550 VR nut (E) 38930015940 756 PTT switch rubber 1
8210005070 756 TOP panel 18810000120 Screw PH M2.6X3 1
8930014950 752 TOP seal 18810005860 Screw PH No. 0M2x3 Ni 5
8930014801 752 VR plate-1 1IBI 8930014840 752 Module shield plate 1
2260000890 Rotary switch [TUNING] SRBM1L040A 18510005860 751 MAIN shield plate 1
®7210001440 Variable resistor [PWR/VOL] 8810005700 Screw PH No. 0M2 x4ZK 1
RK097111101NA(10KA) 752 Release button-2 1
®7210001450 Variable resistor [SQUELCH] lEl 8930014820 Release spring (M) 1
RK0971110051A(10KB) @8930015980 Joint plate 1
2260001150 Switch [LIGHT] SW-1 03 (SKHUPC007B) 18930016570 756 BP holder plate 1
6510008620 Antenna connector BNC-RM-F 18930016590 BP rubber 1
EM 8810005720 Screw PH BO M2x20 ZK 23030000270 NiCd battery P-03ER/F23G1 1
EM 8810000100 Screw PH M2 X4ZK 18930014852 752 Battery terminal-2 3
(Q) 8930014911 Light switch-1 rubber 11^9 8930016583 756C terminal-3 1
8810005890 Screw FH M2x4 ZK 21^9; 8930016970 756A Contact 1
8010009064 756 Rear panel-4 a^9 8930016980 756B Contact 1
8510005830 CO-PLL cover 1Optional product BA-11 BOTTOM CAP 1
Screw abbreviations PH: Pan head FH: Flat head BO: Self-tapping screw ZK: Black Ni: Nickel
5—2

6-1 PREPARATION BEFORE SERVICING
REQUIRED TEST EQUIPMENT
EQUIPMENT GRADE AND RANGE EQUIPMENT GRADE AND RANGE
AC power supply Output voltage 13.8 VDC DC voltmeter Input impedance 50 k£2/DC or better
Current capacity 2Aor more AC milli-voltmeter Measuring range 10 mV-10 V
RF power meter
(terminated type)
Measuring range
Frequency range
Impedance
SWR
1~10 W
120-160 MHz
50 Q
Less than 1.2 :1
External speaker impedance 8Q
Audio generator Frequency range
Output ievel
300-3000 Hz
1-500 mV
Frequency counter Frequency range
Frequency accuracy
0.1—160 MHz
±1ppm or better
Attenuator Power attenuation
Capacity
30 or 40 dB
10 Wor more
Sensitivity 100 mV or better Distortion meter Measuring range 0.1-20 %
Oscilloscope Frequency range
Measuring range DC-20 MHz
0.01-10 VFM deviation meter Frequency minimum
Measuring range
160 MHz
0— ±10 kHz
Standard signal
generator (SSG)
Frequency range
Output level
0.1—160 MHz
-127 17 dBm
(0.1 pV-32 mV)

6-2 PLL ADJUSTMENT
ADJUSTMENT ADJUSTMENT CONDITIONS
MEASUREMENT VALUE
ADJUSTMENT
POINT
UNIT LOCATION UNIT ADJUST
LOCK
voltage
1*Displayed frequency: 145.00 MHz
*Simplex
Transmitting
PLL Connect the
oscilloscope to C6.
(L2 side)
1.6 VDC PLL L2
2*Receiving 1.6 VDC L1
3Install the shielding plaie, Readjust L2 and Li when ihe lock voltage is changed.
REFERENCE
FREQUENCY
1Djsplayed frequency: 146.00 MHz
•Connect the RF power meter or a
50 0dunfimy toad.
•TransmiUlng
Top
panel
Loose couple the
frequency counter to
Ihe antenna
connector,
146.0000 MHz PLL C22
PLL UNtT
Lock voltage
adjust ment
PLL UNtT
C22 Reference frequency adjustment
C6 Lock voltage CP
6—2

6-3 RECEIVER ADJUSTMENT
Sensitivity
adjustment —L1
{MAIN UNITl
LOGIC, RF, MAIN AND DET UNITS
MAIN UNIT LOGIC UNIT
R5 S'iTteter adjusimeni
DET UNIT
RF UNIT
Sline Sen&itiviiy CP
(No resist land)
ADJUSTMENT ADJUSTMENT CONDITIONS
SENSITIVITY \
2
*Displayed trequency: 145.00 MHz
-fSQL] control :Max. CCW
•Set the signal generator;
Level :0.32 pV (- 117dBm)
Modulation: ikHz
Deviation :±3.5 kHz
•Receiving
!
S-METER 1•Displayed trequency: 145.00 MHz
•Set the signal generator;
Level :0.32 pV{-117dSm)
Modulation: \kHz
Deviation :±3-5 kHz
•Receiving
MEASUREMENT
UNIT LOCATION
LOGIC Connect the DC
voltmeter lo the land
oT the Sline.
Connect the
pa he I
I
distortion rneter with
an 3Qload to the
[SPJ jack.
Function |S/RF indicator
display
VALUE
Maximum
Minimum
2bars fS2)
ADJUSTMENT
POINT
UNIT ADJUST
MAIN
DET

6-4 TRANSMITTER ADJUSTMENT
ADJUSTMENT ADJUSTMENT CONDITIONS
MEASUREMENT VALUE
ADJUSTMENT
POINT
UNIT LOCATION UNIT ADJUST
OUTPUT
POWER 1•Displayed frequency: 145.00 MHz •Output power :HIGH
•Simplex
•Transmitting
Top
panel
Connect the RF
power meter to the
antenna connector.
5.0 W10 R5
2•Output power :LOW 10.25~1.0 WVerify
1•Output power :LOW 2Approx. 1.5 WVerify
1•Output power :LOW 3Approx. 3.5 WVerify
FREQUENCY
DEVIATION
1•Displayed frequency: 145.00 MHz
•Output power :HIGH
•Apply an AF signal to the [MIC]
jack.
75 mV/1 kHz (except U.S.A.)
170 mV/1 kHz (U.S.A.)
•Set the FM deviation meter.
HPF :50 Hz
LPF :20 kHz
De-emphasis: OFF
Detector :(P-P)/2
•Transmitting
Top
panel
Connect the FM
deviation meter to
the antenna
connector via the
attenuator.
±4.8 kHz MIC R13
DTMF TONE
FREQUENCY
DEVIATION
1•Displayed frequency: 145.00 MHz
•Push and hold the [PTT] switch and
then push the [D] key.
Top
panel
Connect the
deviation meter to
the antenna
connector via the
attenuator.
±3.5 kHz LOGIC R16
TONE CALL
FREQUENCY
DEVIATION
{IC-2SET only)
1•Displayed frequency: 145.00 MHz
•Push and hold the [LIGHT] switch
and then push the [PTT] switch.
Top
panel
Connect the
deviation meter to
the antenna
connector via the
attenuator.
±3.5 kHz LOGIC R15
6—4

40460*
to AND MIC UNITS
R5 Output power adjustment
MIC UNIT
R13 Frequency deviation adjustment
OUNIT
LOGIC UNIT
R16 DTMF tone frequency
deviation adjustment R1S Tone call frequency
deviation adjustment
H.fv
bi, q
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