Icom IC-M604 User manual

S-14306MZ-C1
Aug. 2006
SERVICE
MANUAL
VHF MARINE TRANSCEVER
iC-m604

This service manual describes the latest service information
for the IC-M604 VHF MARINE TRANSCEIVER at the time
of publication.
NEVER connect the transceiver to an AC outlet or to a DC
power supply that uses more than 15.6 V. This will ruin the
transceiver.
DO NOT expose the transceiver to rain, snow or any liquids.
DO NOT reverse the polarities of the power supply when
connecting the transceiver.
DO NOT apply an RF signal of more than 20 dBm (100
mW) to the antenna connector. This could damage the
transceiver’s front end.
To upgrade quality, any electrical or mechanical parts and
internal circuits are subject to change without notice or
obligation.
MODEL VERSION MICROPHONE COLOR
IC-M604 USA HM-126RB BLACK
USA-1 HM-126RG GRAY
Be sure to include the following four points when ordering
replacement parts:
1. 10-digit order numbers
2. Component part number and name
3. Equipment model name and unit name
4. Quantity required
<SAMPLE ORDER>
1110003490 S.IC TA31136FN IC-M604 MAIN UNIT 5 pieces
8820001210 Screw 2438 screw IC-M604 Top cover 10 pieces
Addresses are provided on the inside back cover for your
convenience.
Icom, Icom Inc. and logo are registered trademarks of Icom Incorporated (Japan) in the United States, the United
Kingdom, Germany, France, Spain, Russia and/or other countries.
ORDERING PARTS
1. Make sure a problem is internal before disassembling
the transceiver.
2. DO NOT open the transceiver until the transceiver is
disconnected from its power source.
3. DO NOT force any of the variable components. Turn
them slowly and smoothly.
4. DO NOT short any circuits or electronic parts. An insu-
lated tuning tool MUST be used for all adjustments.
5. DO NOT keep power ON for a long time when the trans-
ceiver is defective.
6. DO NOT transmit power into a signal generator or a
sweep generator.
7. ALWAYS connect a 50 dB to 60 dB attenuator between
the transceiver and a deviation meter or spectrum ana-
lyzer when using such test equipment.
8. READ the instructions of test equipment thoroughly
before connecting equipment to the transceiver.
REPAIR NOTES
INTRODUCTION DANGER

SECTION 1 SPECIFICATIONS
SECTION 2 INSIDE VIEWS
2-1 IC-M604.......................................................................... 2-1
2-2 HM-157(Optionalproduct) ........................................................... 2-2
SECTION 3 DISASSEMBLY INSTRUCTION
SECTION 4 CIRCUIT DESCRIPTION
4-1 RECEIVERCIRCUITS .............................................................. 4-1
4-2 TRANSMITTERCIRCUITS........................................................... 4-3
4-3 PLLCIRCUITS .................................................................... 4-4
4-4 DSCCIRCUITS.................................................................... 4-5
4-5 LOGICCIRCUITS.................................................................. 4-5
4-6 POWERSUPPLYCIRCUITS.......................................................... 4-6
4-7 PORTALLOCATIONS............................................................... 4-6
SECTION 5 ADJUSTMENT PROCEDURES
5-1 PREPARATION .................................................................... 5-1
5-2 PLLADJUSTMENTS................................................................ 5-2
5-3 RECEIVERADJUSTMENTS.......................................................... 5-3
SECTION 6 PARTS LIST
SECTION 7 MECHANICAL PARTS
7-1 IC-M604.......................................................................... 7-1
7-2 HM-126RB/RG..................................................................... 7-3
7-3 HM-157(Optionalproduct) ........................................................... 7-3
SECTION 8 SEMI-CONDUCTOR INFORMATION
SECTION 9 BOARD LAYOUTS
9-1 VRUNIT ......................................................................... 9-1
9-2 SQLUNIT ........................................................................ 9-1
9-3 DIALUNIT........................................................................ 9-1
9-4 CONNECTUNIT................................................................... 9-1
9-5 LOGICUNIT ...................................................................... 9-2
9-6 MAINUNIT ....................................................................... 9-4
9-7 AFUNIT.......................................................................... 9-6
9-8 HM-126RB/RG..................................................................... 9-8
9-9 HM-157(Optionalproduct) ........................................................... 9-8
SECTION 10 BLOCK DIAGRAM
SECTION 11 WIRING DIAGRAM
SECTION 12 VOLTAGE DIAGRAM
12-1 LOGICUNIT ..................................................................... 12-1
12-2 MAINUNIT ...................................................................... 12-2
12-3 AFUNIT......................................................................... 12-4
12-4 HM-126RB/RG.................................................................... 12-5
12-5 HM-157(Optionalproduct) .......................................................... 12-6
TABLE OF CONTENTS

¤GENERAL
• Frequency coverage : 156.025–157.425 MHz (TX)
156.050–163.275 MHz (RX)
• Mode : 16K0G3E (FM) / 16K0G2B (DSC)
• Power supply voltage : 13.8 V DC ±15 % (negative ground)
• Operating temperature range : –20˚C to +60˚C; –4˚F to +140˚F
• Current drain (at 13.8 V DC) : Transmit at 25 W 5.5 A approx.
Receive max. audio 1.5 A approx.
• Antenna impedance : 50 Ω(nominal)
• Dimensions (projections not included) : 220(W)×110(H)×109.4(D) mm; 821⁄32(W) ×411⁄32(H) ×45⁄16(D) in
• Weight : 1400 g; 3.09 lb
¤TRANSMITTER
• Output power (at 13.8 V DC) : High 25 W
Low 1 W
• Modulation : Variable reactance frequency modulation
• Maximum frequency deviation : ±5.0 kHz
• Frequency stability : ±0.3 kHz
• Spurious emissions : Less than –70 dBc
• Adjacent channel power : More than 70 dB
• Residual modulation : More than 40 dB
• Audio harmonic distortion : Less than 10% at 60% deviation
• Audio frequency response : +1 dB to –3 dB of 6 dB/octave from 300 Hz to 3000 Hz
• Microphone impedance : 2 kΩ
¤RECEIVER
• Receive system : Double conversion superheterodyne system
• Intermediate frequencies : 1st 21.7 MHz*1, 30.15 MHz*2
2nd 450 kHz
• Sensitivity : Less than –10 dBµ at 12 dB SINAD (for both regular and CH70)
• Squelch sensitivity : Less than –10 dBµ at threshold
• Adjacent channel selectivity : More than 80 dB
• Spurious response : More than 80 dB
• Intermodulation rejection ratio : More than 80 dB
• Hum and noise : More than 40 dB
• Audio output power (at 13.8 V DC) : 5.0 W typical at 10% distortion with a 4 Ωload
• Audio frequency responce : +1 dB to –3 dB of –6 dB octave from 300 Hz to 3000 Hz
*1Channel 70, *2Normal channels
Specifications are measured in accordance with TIA/EIA 603
All stated specifications are subject to change without notice or obligation.
SECTION 1 SPECIFICATIONS
1 - 1

¤VHF MARINE CHANNEL LIST
1 - 2
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2-1 IC-M604
• MAIN UNIT
* Located under side of the point
RF amplifier
(Q1: 3SK294)
RF amplifier (for CH70)
(Q7: 3SK294)
Antenna switch circuit
1st mixer circuit (for CH70)
D21: HSB88WS
L48, L49: 617DB-1327=P3
TX/RX switch circuit
(D42, D43*: MA77) Power amplifier*
(IC13: RA35H1516M)
TX VCO circuit
Q18: PMBFJ310
D39, D40: 1SV214
2nd mixer (for CH70)
(IC6: TA31136FN)
D/A converter
(IC15: M62363FP-650C)
1st mixer circuit
D11: HSB88WS
L18: 617DB-1919=P3
L19: 617DB-1327=P3
RX VCO circuit
Q12: PMBFJ310
D32, D33: HVC358B
2nd mixer
(IC1: TA31136FNG)
PLL IC
(IC12: µPD3140GS)
Reference oscillator
(X4: CR-827 15.3 MHz)
• LOGIC UNIT
Reset IC
(IC2: S-80942CNMC-G9C)
DIAL UNIT
SQL UNIT
VR UNIT
LOGIC UNIT
EEPROM
(IC4: HN58X24164TI)
CPU
(IC1: HD64F2633FRF28V)
System clock
(X1: CR-691 9.8304 MHz)
Speaker
SECTION 2 INSIDE VIEWS
2 - 1

2-2 HM-157 (Optional product)
• TOP VIEW
LCD
(DS1: A0119)
• BOTTOM VIEW
CPU
(IC1: MPD789405AGK-A30-9EU)
Data buffer circuit
System clock
(X1: CSTCC4.91MG)
8V regulator
(IC6: TA7808F)
Dimmer circuit
Reset IC
(IC7: S-80928CNMC)
MIC amplifier
(IC4: NJM2125F)
5V regulator
(IC5: TA78L05F) Volume IC
(IC3: M62429FP)
AF/MIC switch
(IC9: TC4W53FU)
AF amplifier
(IC2: TA7368F)
2 - 2

J2
J4
J5
J8
J10
J9
K
K
J
H
I
K
AF UNIT
4. Removing the AF UNIT
1 Disconnect 4 connectors from J5, J8, J9 and J10.
2 Disconnect 2 flat cables from J2 and J4
3 Unscrew 2 screws H, and remove 2 clips I, J.
4 Unscrew 3 screws K, and remove the AF UNIT.
1. Opening the transceiver case
1 Unscrew 6 screws A, and remove the front unit.
2 Unscrew 6 screws B, and remove the rear panel.
A
A
A
A
A
B
B
B
B
B
FRONT UNIT
REAR panel
E
J7
J4 J5
J2
J1
J6
J3
C
D
D
D
D
D
D
D
LOGIC UNIT
G
G
F
G G
F
G
F
G
G
J1
J2
Unsolder point
MAIN UNIT
2. Removing the LOGIC UNIT
1 Disconnect connector from J5 and flat cables from J1,
J2 and J6.
2 Unsolder 2 points C.
3 Disconnect microphone connector from J4 and SQL/
DIAL connectors from J7.
4 Unscrew 7 screws D, and remove the LOGIC UNIT.
3. Removing the MAIN UNIT
1 Remove the shield cover E.
2 Disconnect flat cables from J1 and J2.
3 Unsolder 17 points F.
4 Unscrew 7 screws G, and remove the MAIN UNIT.
SECTION 3 DISASSEMBLY AND OPTIONS INSTRUCTIONS
3 - 1

4-1 RECEIVER CIRCUITS
4-1-1 ANTENNA SWITCHING CIRCUIT (MAIN UNIT)
The antenna switching circuit functions as a low-pass filter
while receiving and as resonator circuit while transmitting.
The circuit does not allow transmit signals to enter the
receiver circuits.
Received signals enter the MAIN unit from the antenna con-
nector and pass through the low-pass filter (L1, L2). The
signals are then applied to the RF circuit via the antenna
switching circuit (D1, L3, L4, C7–C9).
4-1-2 RF CIRCUIT (MAIN UNIT)
The RF circuit amplifies signals within the range of frequen-
cy coverage and filters out-of-band signals.
The signals from the antenna switching circuit pass through
the tunable bandpass filter (L11, C23–C25) which the object
signals are led to each RF amplifier of channel 70 circuit (Q7)
or other channels (except channel 70) circuit (Q1).
• CHANNEL 70 CIRCUIT
The amplified signals from the RF amplifier (Q7) are applied
to the 4-stage bandpass filter (L31–L34, C407, C408, C410
–C423) to suppress unwanted signals and improve the
selectivity. The signals are then applied to the 1st mixer cir-
cuit for channel 70.
• OTHER CHANNELS CIRCUIT
The amplified signals from the RF amplifier (Q1) are applied
to the 4-stage bandpass filter (L12–L15, C33, C34, C36–
C48) to suppress unwanted signals and improve the selec-
tivity. The signals are then applied to the 1st mixer circuit for
other channels.
IF
amp.
For other channels
to the 2nd mixer circuit
(IC1, pin 16) BPF
RF
amp.
IF
amp.
RF
amp.
BPF LPF
ANT
ANT
sw.
BPF
1st LO signal
1st LO signal
to the 2nd mixer circuit
(IC6, pin 16)
For channel 70 only
• 1ST MIXER AND 1ST IF CIRCUITS
SECTION 4 CIRCUIT DESCRIPTION
4-1-3 1ST MIXER AND 1ST IF CIRCUITS
(MAIN UNIT)
The 1st mixer circuit converts the received signal into a
fixed frequency of the 1st IF signal with a 1st LO (VCO out-
put) frequency. By changing the 1st LO frequency, only the
desired frequency will pass through a pair of crystal filters at
the next stage of the mixer.
• CHANNEL 70 CIRCUIT
The signals from the RF circuit are mixed with the 1st LO
signals at the 1st mixer circuit (D21, L48, L49) to produce a
21.7 MHz 1st IF signal.
The 1st IF signal is amplified at the 1st IF amplifiers (Q8,
Q9), and then passes through the pair of crystal bandpass
filters (FI4, FI5) to suppress out-of-band signals. The filtered
signal is then amplified at the 2nd IF amplifier (Q10), and is
then applied to the 2nd mixer circuit (IC6).
• OTHER CHANNELS CIRCUIT
The signals from the RF circuit are mixed with the 1st LO
signals at the 1st mixer circuit (D11, L18, L19) to produce a
30.15 MHz 1st IF signal.
The 1st IF signal is amplified at the 1st IF amplifiers (Q3,
Q4), and then passes through the crystal bandpass filter
(FI1) to suppress out-of-band signals. The filtered signal
is then amplified at the 2nd IF amplifier (Q2), and is then
applied to the 2nd mixer circuit (IC1).
4 - 1

4-1-4 2ND IF AND DEMODULATOR CIRCUITS
(MAIN UNIT)
The 2nd mixer circuit converts the 1st IF signal into a 2nd IF
signal. A double superheterodyne system (which converts
receive signals twice) improves the image rejection ratio
and obtains stable receiver gain.
The FM IF IC (IC6 for channel 70, IC1 for other channels)
contains the 2nd local oscillator, 2nd mixer, limiter amplifier,
quadrature detector, and noise detector circuits, etc.
• CHANNEL 70 CIRCUIT
The 1st IF signal from the 2nd IF amplifier (Q10) is applied
to the 2nd mixer section of FM IF IC (IC6, pin 16), and is
mixed with a 21.25 MHz 2nd LO signal, which is generated
at the 2nd oscillator section in IC6 and X3, to produce a 450
kHz 2nd IF signal.
The 2nd IF signal from IC6 (pin 3) is passed through the
ceramic filter (FI6), which unwanted signals are suppressed,
and is then applied to the 2nd IF (limiter) amplifier in IC6 (pin
5). The signal is applied to the FM detector section in IC6
for demodulating into AF signals.
“DEC2” signal
AF signal “DET”
IC5a,
IC5b
IC11
1
910
5
FI6
Limiter
amp.
FM
detector
2nd
mixer
11
X2
8V
3
16 1st IF (21.7 MHz) from Q10
X3
21.25 MHz
2nd IF filter
450 kHz
IC6 TA31136FNG
2
6
IC3c,
IC3d
IC9
DSC
decoder
• 2ND IF AND DEMODULATOR CIRCUITS
(For CHANNEL 70 ONLY)
2nd
Mixer
16
Limiter
amp.
2nd IF filter
450 kHz
PLL IC
IC12
X4
15.3 MHz
X1
(30.6 MHz)
Q16
RSSI
IC1 TA31136FNG
14 1st IF (30.15 MHz) from Q2
"NOISE" signal to the SQL amplifier (IC2, pin 1)
11109
17
IC11
IC3a
IC3b
"DEC1" signal
"WXDEC" signal
87 5 3
AF signal "DET"
8V
D/A convertor IC
(IC15, pin 23)
2
17 16
Active
filter
FI3
Noise
detector
FM
detector
2
DSC
decoder
• 2ND IF AND DEMODULATOR CIRCUITS
(For OTHER CHANNELS)
The FM detector circuit employs a quadrature detection
method (linear phase detection), which uses a ceramic dis-
criminator (X2) for phase delay to obtain a non-adjusting
circuit. The detected signal from IC6 (pin 9) is applied to the
AF circuit.
• OTHER CHANNELS CIRCUIT
The 1st IF signal from the 2nd IF amplifier (Q2) is applied
to the 2nd mixer section of FM IF IC (IC1, pin 16), and is
mixed with a 30.6 MHz 2nd LO signal, which is generated
at the PLL circuit using the reference frequency (15.3 MHz),
to produce a 450 kHz 2nd IF signal.
The 2nd IF signal from IC1 (pin 3) is passed through the
ceramic filter (FI3), which unwanted signals are suppressed,
and is then applied to the 2nd IF (limiter) amplifier in IC1 (pin
5). The signal is applied to the FM detector section in IC1
for demodulating into AF signals.
The FM detector circuit employs a quadrature detection
method (linear phase detection), which uses a ceramic dis-
criminator (X1) for phase delay to obtain a non-adjusting
circuit. The detected signal from IC1 (pin 9) is applied to the
AF circuit.
4 - 2

4-1-5 AF AMPLIFIER CIRCUIT (AF UNIT)
The AF amplifier circuit amplifies the demodulated signals
to drive a speaker. The AF circuit includes an AF mute cir-
cuit for the squelch.
AF signals from the FM IF ICs (channel 70; IC6, pin 9, other
channels IC1, pin 9) are passed through the analog switch
(IC7, pins 10, 11) via the “DET” signal, and are applied to
the de-emphasis circuit (R31, C41). The de-emphasis circuit
is an integrated circuit with frequency characteristic of –6
dB/octave.
The signals pass through the bandpass filter (Q11, Q12),
and are then applied to the AF mute swtich (Q13). The sig-
nals passed through the [VOLUME] control (VR unit; R1),
and are then applied to the AF power amplifier (IC3, pin
1) to obtain 5 W AF audio output power. The amplified AF
signals drive the internal speaker as “SP+” signal directly or
external speaker as “AF” signal via the RL2.
4-1-6 SQUELCH CIRCUIT
(MAIN AND LOGIC UNITS)
A squelch circuit cuts out AF signals when no RF signals
are received. By detecting noise components in the AF sig-
nals, the squelch circuit switches the AF mute switch.
A portion of the AF signals from the FM IF IC (IC1, pin 9)
is passed through C89, and is applied to the D/A converter
(IC15, pin 24) to control the amplitude. The signal is applied
to the FM IF IC’s active filter section (IC1, pin 8). The active
filter section amplifies and filters noise components. The fil-
tered signals are applied to the noise detector section and
output from pin 14 as the “SQL” signal. The “SQL” signal is
amplified at the DC amplifier (IC2) and applied to the main
CPU (LOGIC unit; IC1, pin 104) as the “SQL” signal. The
main CPU compares “SQL” voltage with “SQLV” voltage from
the SQL board, and outputs the “MICM” and “RMUTE” sig-
nals to toggle the AF mute switches (Q7, Q13).
4-2 TRANSMITTER CIRCUITS
4-2-1 MICROPHONE AMPLIFIER CIRCUIT
(AF UNIT)
The microphone amplifier circuit amplifies audio signals with
+6 dB/octave pre-emphasis from the microphone to a level
needed at the modulation circuit.
• USING HM-126RB/RG
The AF signals from the microphone (ACC unit; HM-126RB/
RG) are amplified at the microphone amplifier (IC6a) via the
analog switch (IC4, pins 11, 10) as “MIC” signal. A capacitor
(C77) and resistor (R73) are connected to the microphone
amplifier to obtain the pre-emphasis characteristics.
• USING HM-162
The AF signals from the microphone (ACC unit; HM-162)
are amplified at the microphone amplifier (IC6a) via the
analog switch (connecting option1 jack: IC16, pins 2, 3, 4;
connecting option2 jack: IC16, pins 4, 9, 10) as “AF/MIC1”
or “AF/MIC2” signals. A capacitor (C77) and resistor (R73)
are connected to the microphone amplifier to obtain the pre-
emphasis characteristics.
The amplified signals are applied to the IDC amplifier (IC8a,
pin 2) via the analog switch (IC7, pins 2, 3, 9), and are then
passed through the splatter filter (IC8b) to suppress unwant-
ed 3 kHz or higher signals. The filtered signals are applied
to the modulation circuit.
4-2-2 MODULATION CIRCUIT (MAIN UNIT)
The modulation circuit modulates the VCO oscillating signal
(RF signal) using the microphone audio signals.
The audio signals from the splatter filter (IC8b) are passed
through the D/A converter IC (IC15, pins11, 12), and are
then applied to the modulation circuit. The applied signals
change the reactance of the varactor diode (D37), and mod-
ulate the oscillated signal at the TX-VCO (Q18).
4-2-3 PRE-DRIVE AND YGR AMPLIFIERS CIRCUIT
(MAIN UNIT)
The drive amplifier circuit amplifies the VCO oscillating sig-
nal to a level needed at the power amplifier.
The output signal from VCO circuit is amplified at the buffer
amplifiers (Q19 and Q27), and is applied to the TX/RX
switch (D43). The transmit signal from the TX/RX switch is
amplified at the pre-drive (Q28) and YGR (Q30) amplifiers
to obtain an approximate 50 mW signal level. The amplified
signal is then applied to the RF power amplifier (IC13).
4-2-4 POWER AMPLIFIER CIRCUIT (MAIN UNIT)
The power amplifier circuit amplifies the driver signal to an
output power level.
IC13 is a power module which has amplification output
capabilities of about 35 W with 50 mW input. The output sig-
nal from IC13 (pin 1) is passed through the antenna switch-
ing circuit (D46) and is then applied to the antenna connec-
tor via the low-pass filter (L1, L2, L89, C361, C364).
4 - 3

4-2-5 APC CIRCUIT (MAIN UNIT)
The APC (Automatic Power Controller) circuit stabilizes the
TX output power.
The RF output signal from the power amplifier (IC13) is
detected at the power detector circuit (D47, D48) and is
applied to APC controller. The applied voltage compares
to “DAPCON” signal from the D/A converter IC (IC15, pin
14), and then outputs the differential bias voltage for power
amplifier (IC13, pin 3). Thus the APC circuit maintains a
constant output power.
4-3 PLL CIRCUITS
4-3-1 GENERAL
The PLL circuit provides stable oscillation of the transmit
frequency and receive 1st LO frequency. The PLL circuit
compares the phase of divided VCO frequency with the ref-
erence frequency. The PLL output frequency is controlled by
the crystal oscillator and divided ratio of the programmable
divider.
IC12 is a dual PLL IC, which controls both TX and RX VCO
circuits, and contains a prescaler, programmable counter,
programmable divider, phase detector, charge pomp and
etc.
The PLL circuit, using a one chip PLL IC (IC12), directly
generates the transmit frequency and receive 1st IF fre-
quency with VCOs. The PLL IC sets the divided ratio based
on serial data from the main CPU, and compares the phas-
es of VCO signals with the reference oscillator frequency.
The PLL IC detects the out-of-step phase and outputs from
pins 8 and 13 for TX and RX, respectively. The reference
frequency (15.3 MHz) is oscillated at the reference oscillator
(X4).
D47 D48
L89
H/L
"TXDET" signal to the CPU
(LOGIC board; IC1, pin 106)
Q33
Pre
drive YGR
Q28 Q30
RF signal
from PLL to antenna
RF detector
circuit
APC control circuit
Power module
IC13
Q32
T8
"TMUTE" signal from the CPU
(LOGIC board; IC1, pin 93)
IC14 "DAPCON" signal from the D/A
convertor (IC15, pin 14)
• APC CIRCUIT
4-3-2 TX AND CHANNEL 70 (RX) LOOPS
The generated signal at the TX-VCO/CHANNEL 70-VCO
(Q18, D37, D39, D40) enters the PLL IC (IC12, pin 2) and
is divided at the programmable divider section and is then
applied to the phase detector section.
The phase detector compares the input signal with a refer-
ence frequency, and then outputs the out-of-phase signal
(pulse-type signal) from pin 8.
The pulse-type signal is converted into DC voltage (lock
voltage) at the loop filter (R217–R219, C247, C249, C278),
and is then applied to the varactor diodes (D39, D40) of the
TX-VCO to stabilize the oscillated frequency.
4-3-3 OTHER CHANNELS (RX) LOOP
The generated signal at the RX-VCO (Q12, D32, D33)
enters the PLL IC (IC2, pin 19) and is divided at the pro-
grammable divider section and is then applied to the phase
detector section.
The phase detector compares the input signal with a refer-
ence frequency, and then outputs the out-of-phase signal
(pulse-type signal) from pin 13.
The pulse-type signal is converted into DC voltage (lock
voltage) at the loop filter (R182, R213, R214, C225, C248),
and is then applied to the varactor diodes (D32, D33) of the
RX-VCO to stabilize the oscillated frequency. The lock volt-
age from the loop filter is amplified at the buffer amplifier
(Q23), and is then applied to the RF circuit.
4 - 4

4-3-4 VCO CIRCUIT (MAIN UNIT)
• TX-VCO/CHANNEL 70-VCO (RX) CIRCUITS
The VCO outputs from TX-VCO/CHANNEL 70-VCO (Q18)
are amplified at the buffer amplifiers (Q19 and Q27), and
are applied to the TX/RX switch circuit (D42, D43). The
receiver LO signal is applied to the 1st mixer circuit for
CHANNEL 70 (D21, L48, L49) passing through a low-pass
filter (L51, L52, C150–C152), and the transmitter signal is
applied to the pre-drive amplifier (Q28). A portion of the
VCO output signal is re-applied to the PLL IC (IC12, pin 2)
via the buffer amplifier (Q15).
• OTHER CHANNELS-VCO (RX) CIRCUITS
The VCO outputs from OTHER CHANNELS-VCO (Q12) are
amplified at the buffer amplifiers (Q13 and Q23). The receiv-
er LO signal is applied to the 1st mixer circuit for OTHER
CHANNELS (D11, L18, L19) passing through a low-pass
filter (L21, L22, C52–C54). A portion of the VCO output sig-
nal is re-applied to the PLL IC (IC12, pin 2 or pin 19) via the
buffer amplifier (Q19).
4-4 DSC CIRCUITS
4-4-1 DSC MODULATION CIRCUIT
(LOGIC, AF AND MAIN UNITS)
The ATIS signal from the CPU (LOGIC unit; IC1, pin 117)
is applied to the buffer amplifier (AF unit; Q18) as “DSC”
signal. The signal passes through the analog switch (AF
unit; IC7, pin 1), and then applied to IDC amplifier (AF unit;
IC8a). Then, the amplified signal is applied to the transmitter
circuit.
Loop
filter
X2
15.3 MHz
Shift register/
data latch
IC12 (PLL IC)
Prescaler
Phase
detector
Programmable
counter
Programmable
divider
3
4
5
2
8
2
PSTB
PCK
PDATA
30.6 MHz signal
to the FM IF IC
(IC1, pin 2)
Q27
Q15
Q19
to transmitter circuit
to 1st mixer circuit
D42
D43
17
Q16
16
Q18, D37, D39, D40
VCO Buffer
Buffer
Buffer
• PLL CIRCUIT
Buff.
amp.
Q18
"DSC" signal from the CPU
(LOGIC board; IC1, pin 117)
IC7
analog
switch
IDC
amp.
IC8a
LPF
IC8b
D/A
convertor
IC15
to VCO circuit
• DSC CIRCUIT
The signalis passed through the splatter filter (AF unit; IC8b)
to suppress unwanted 3 kHz or higher signals. The filtered
signals are then applied to the TX modulation circuit via the
D/A converter IC (MAIN unit; IC15, pins 11, 12) as a DSC
modulation signal “MOD”.
4-5 LOGIC CIRCUITS
4-5-1 LOGIC UNIT
• CPU
IC1 is a 8 bit single chip micro-computer, which contains
LCD driver, serial I/O, timer, A/D converter, programmable
I/O, ROM and RAM.
• SYSTEM CLOCK CIRCUIT
X1 is a crystal oscillator, which oscillates 9.8304 MHz sys-
tem clock for the main CPU (IC1).
• RESET CIRCUIT
IC2 is a reset IC, which outputs a reset signal (“LOW” pulse)
to main CPU (IC1, pin 79) when turning transceiver power
ON.
4 - 5

4-6 POWER SUPPLY CIRCUITS
4-6-1 VOLTAGE LINE (MAIN UNIT)
4-7 PORT ALLOCATIONS
4-7-1 EXPANDER IC (AF unit; IC18)
4-7-2 EXPANDER IC (AF unit; IC17)
LINE
HV
VCC
8V
5V
T8
R8
DESCRIPTION
The 13.8 V from the connected DC power sup-
ply.
Same voltage as the 13.8 V line, and is applied
to the AF power amplifiers (AF unit; IC3, IC10),
LOGIC unit, etc.
Common 8 V converted from the VCC line at
the +8V regulator circuit (AF unit; IC1). The out-
put voltage is applied to the T8 controller (MAIN
unit; Q36, Q36), +5 regulator (AF unit; IC2), R8
regulator (AF unit; Q1, Q2), etc.
Common 5 V converted from the 8V line at the
+5 regulator circuit (AF unit; IC2). The output
voltage is applied to the buffer amplifiers (AF
unit; IC19, Q14), expander ICs (AF unit; IC17,
IC18), etc.
Transmit 8 V controlled by the T8 control circuit
(MAIN unit; Q35, Q36) using the “SEND” signal
from main CPU. The output voltage is applied to
the pre-dirve (MAIN unit; Q28), YGR amplifier
(MAIN unit; Q30), APC controller (MAIN unit;
IC14), etc.
Receive 8 V controlled by the R8 control circuit
(AF unit; Q1, Q2) using the RCV signal from
main CPU. The controlled voltage is applied to
the bandpass filter (AF unit; Q11, Q12), buffer
and IF amplifiers (AF unit; Q2 and Q23), etc.
4
5
6
7
11
12
13
14
MICS2
MICS1
SPS2
SPS1
SP
BPLVL
RCV
HLC
Outputs HM-162/2 control signal.
High : While transmitting via the
HM-162/2.
Outputs HM-162/1 control signal.
High : While transmitting via the
HM-162/1.
Outputs HM-162/2 control signal.
High : While receiving via the
HM-162/2.
Outputs HM-162/1 control signal.
High : While receiving via the
HM-162/1.
Outputs the internal speaker (FRONT
unit; SP1) control signal.
High : The speaker is activating.
Outputs beep audio level control sig-
nal.
Low : Beep audio level is maximum.
Outputs the R8 regulator (AF unit; Q1,
Q2) control signal.
High : While receiving.
Outputs the Hailer speaker TX/RX
select signal.
High : While transmitting via the
Hailer speaker.
Pin Port Description
number name
4
5
6
7
11
12
13
14
STRU
AFSUB
INCMH
INCHM
MIC/DSC
HAILIN
FOGC
HAILOUT
Outputs scrambler unit bypass control
signal.
High : Bypassing the scrambler unit.
Outputs sound signals to the HM-162.
High : Sounding from HM-162.
Outputs voice signals from IC-M602
to HM-162 using intercom function.
High : While receiving.
Outputs voice signals from HM-162 to
IC-M602 using intercom function.
High : While transmitting.
Outputs MIC/DSC modulation circuit
control signal.
High : While the DSC signal is mod-
ulated.
Outputs the microphone select signal.
High : While using the hailer speaker.
Outputs fog horn control signal.
High : Fog horn is ON.
Outputs the microphone select signal.
High : While using the HM-126.
Pin Port Description
number name
4 - 6

4-7-3 CPU (LOGIC BOARD; IC1)
Input port for the low-battery detecting
signal. Low battery indicator appears
when the battery becomes less than
2.58 V
Input port for transmit detecting signal.
Input port for the indide temperature
detecting signal.
Input ports for the dial data signals.
Input port for the HM-136’s PTT but-
ton detecting signal.
Low : While PTT button is pushed.
Input port for the microphone hanger
detecting signal
Low : The microphone on hook.
Outputs ATIS/DSC encode signals.
Outputs the voice scramber unit
(UT-112) control signal.
Outputs a strobe signal to the voice
scrambler unit (UT-112).
Outputs a strobe signal to the PLL IC
(MAIN unit; IC12, pin 3).
Outputs a strobe signal to the D/A
convertor IC (MAIN unit; IC15, pin 6).
I/O port for the communicating singal
from the microphone (HM-162/2) to
the transceiver.
I/O port for the communicating singal
from the transceiver to the micro-
phone (HM-162/2).
LBAT
TXDET
TEMP
DIAL1–
DIAL4
PTT
HANG
DSC
SCON
OPSTB
DASTB
PSTB
DATAH2M
DATAMH2
105
106
107
111–114
115
26
117
120
121
124
125
126
127
40
41
28
34
38
110
58
59
63
64
66
69
70
71
6
92
93
94
96
97
98
103
104
UNLK
EDATA
ECK
DEC3
.
DEC1
BEEP
DATAMC
DATACM
DATAMH1
DATAH1M
DATANM
DATAMN
PDATA
PCK
OPTIN
RMUTE
TMUTE
SEND
H/L
ATT2C
ATT1C
WXDEC
SQL
Input port for PLL unlock signal from
the PLL IC (MAIN unit; IC12, pin 7).
High : While PLL is unlocked.
I/O port for the data signals to the
EEPROM (IC4, pin 5).
Outputs a clock signal to the
EEPROM (IC4, pin 6).
Input port for the decode signal for
channel 70 receiver.
Input port for the ATIS/DSC decode
signals.
Outputs beep audio signals.
I/O port for the cloning data from the
transceiver.
I/O port for the cloning data to the
transceiver.
I/O port for the communicating signal
from the transceiver to the micro-
phone (HM-162/1).
I/O port for the communicating signal
from the microphone (HM-162/1) to
the transceiver.
I/O port for the GGA signals
I/O port for the NMEA data.
Outputs a data signal to the PLL IC
(MAIN unit; IC12, pin 5).
Outputs a clock signal to the PLL IC
(MAIN unit; IC12, pin 4).
Outputs the voice scrambler unit
(UT-112) detecting signal.
Low : While UT-112 is connecting.
Outputs RX muting signal.
High : While RX signal is muting.
Outputs transmit mute signal.
High : While TX muting.
Outputs T8 regulator control signal.
High: While transmitting.
Output port for RF output power (High
or Low) select signal.
Low : While Low power is selected.
Output RX attenuator control signals.
Input port for the weather alert signal.
Input port for the FM IF IC (MAIN unit;
IC1, pin 14)’s noise amplifier detect-
ing signal.
Pin Port Description
number name
Pin Port Description
number name
ATT level
ATT1C
ATT2C
OFF
1
1
ON (1)
1
0
ON (2)
0
1
MAX.
1
1
4 - 7

5-1 PREPARATION
¤ REQUIRED TEST EQUIPMENT
EQUIPMENT
DC power supply
External speaker
Tracking generator
GRADE AND RANGE
Output voltage : 13.8 V DC
Current capacity : 10 A or more
Input impedance : 4 Ω
Capacity : 5 W or more
Frequency range : 100–300 MHz
Output level : 0.1 µV to 32 mV
(–127 dBm to –17 dBm)
EQUIPMENT
Standard signal
generator (SSG)
DC voltmeter
Distortion meter
GRADE AND RANGE
Frequency range : 0.1–300 MHz
Output level : 0.1 µV to 32 mV
(–127 to –17 dBm)
Input impedance : 50 kΩ/V DC or better
Frequency range : 1 kHz ±10 %
Measuring range : 1–100 %
)#-REARPANEL
./4%%84%2.!,30%!+%2*!#+0).#/..%#4)/.
.-%!/54
.-%!/54
.-%!)..-%!).
30
30
0OWERSUPPLY
6!ORMORE
4RACKINGGENERATOR
3TANDARDSIGNALGENERATOR
-(Z
D"MTOD"M
6TOM6
#!54)/.
$/ ./4 TRANSMIT WHILE AN
33' IS CONNECTED TO THE
ANTENNACONNECTOR
TOTHEANTENNA
CONNECTOR
TOEXTERNALSPEAKERJACK
LOAD $ISTORTIONMETER
SECTION 5 ADJUSTMENT PROCEDURES
5 - 1
¤ CONNECTION

• MAIN UNIT TOP VIEW
Lock voltage
adjustment for TX
L73
Lock voltage
check point for RX
CP1 Lock voltage
check point for TX
CP2
Lock voltage
adjustment for RX
L62
5-2 PLL ADJUSTMENTS
LOCK
VOLTAGE
ADJUSTMENT
ADJUSTMENT ADJUSTMENT CONDITION MEASUREMENT VALUE
POINT
UNIT LOCATION UNIT ADJUST
1
2
3
• Operating channel : ch P2
• Receiving
• Operating channel : ch P2
• Output power : Low
• Transmitting
• Operating channel : ch 70
• Receiving
MAIN Connect a digital
multi-meter or oscil-
loscope to check
point CP1.
Connect a digital
multi-meter or oscil-
loscope to check
point CP2.
3.8 V – 4.0 V
3.1 V – 3.3 V
2.4–3.7 V
MAIN L62
L73
Verify
5 - 2

*This output level of a standard signal generator (SSG) is indicated as SSG’s open circuit.
5-3 RECEIVER ADJUSTMENTS
SENSITIVITY
(Except chan-
nel 70)
(Channel 70)
ADJUSTMENT
ADJUSTMENT ADJUSTMENT CONDITION MEASUREMENT VALUE
POINT
UNIT LOCATION UNIT ADJUST
1
2
• Operating channel : ch 16
• Connect a tracking generator’s
output to the antenna connector
and set as:
Level : 7.1 mV*
(–30 dBm)
• Operating channel : ch 70
• Connect an SSG to the antenna
connector and set as:
Frequency : 156.525 MHz
Level : 10 µV*
(–97 dBm)
Modulation : 1 kHz
Deviation : ±3.5 kHz
• Set the internal speaker OFF in
the SET mode, and connect a
distortion meter with a 4 Ωload
to [EXT SP] receptacle.
• Receiving
MAIN
MAIN
Connect a tracking
generator’s input to
the MAIN unit; J3.
Connect a DC volt-
meter to check point
CP3.
Set the flat wave form
as shown below.
Maximum voltage
MAIN
MAIN
L11
L12
L13
L14
L15
L31
L32
L33
L34
-(Z -(Z
3ETTOFLATWAVEFORM
5 - 3

L11
L12
L13
L14
L15
J3
RX sensitivity adjustment
for other channels
RX sensitivity check point
L31
L34
L33
L32 RX sensitivity adjustment
for channel 70
• MAIN UNIT TOP VIEW
• MAIN UNIT TOP VIEW
5 - 4

6 - 1
SECTION 6 PARTS LIST
M.=Mounted side (T: Mounted on the Top side, B: Mounted on the Bottom side)
[FRONT UNIT]
REF ORDER DESCRIPTION M. H/V
NO. NO.
LOCATION
W1 8900015550 CBL OPC-1658
W2 7120000470 JMP ERDS2T0
W3 7120000470 JMP ERDS2T0
S.=Surface mount
[LOGIC UNIT]
REF ORDER DESCRIPTION M. H/V
NO. NO.
LOCATION
R47 7030003360 S.RES ERJ3GEYJ 221 V (220) B 103.8/13
R48 7030003360 S.RES ERJ3GEYJ 221 V (220) B 107.1/49.6
R49 7030003360 S.RES ERJ3GEYJ 221 V (220) B 34.2/22.3
R50 7030003330 S.RES ERJ3GEYJ 121 V (120) B 31/33.5
R51 7030003330 S.RES ERJ3GEYJ 121 V (120) B 63.3/36.6
R52 7030003700 S.RES ERJ3GEYJ 154 V (150 k) B 63.9/38.7
R53 7030003640 S.RES ERJ3GEYJ 473 V (47 k) B 65.2/38.7
R55 7030003560 S.RES ERJ3GEYJ 103 V (10 k) B 35.6/22.3
R56 7030003560 S.RES ERJ3GEYJ 103 V (10 k) B 38.2/22.3
R57 7030003560 S.RES ERJ3GEYJ 103 V (10 k) B 40.8/22.3
R58 7030003560 S.RES ERJ3GEYJ 103 V (10 k) B 43.4/22.3
R62 7030003680 S.RES ERJ3GEYJ 104 V (100 k) B 28.9/44.8
R63 7030003560 S.RES ERJ3GEYJ 103 V (10 k) B 34.9/36.9
R64 7030003440 S.RES ERJ3GEYJ 102 V (1 k) B 25.9/41.8
R65 7030003440 S.RES ERJ3GEYJ 102 V (1 k) B 27.2/41.8
R66 7030003320 S.RES ERJ3GEYJ 101 V (100) B 33.4/35.1
R71 7030003680 S.RES ERJ3GEYJ 104 V (100 k) B 60.7/46.2
R72 7030003860 S.RES ERJ3GE JPW V B 58.6/43.7
R81 7030003640 S.RES ERJ3GEYJ 473 V (47 k) B 81.9/70.6
R82 7030003560 S.RES ERJ3GEYJ 103 V (10 k) B 85.3/70.6
R83 7030003560 S.RES ERJ3GEYJ 103 V (10 k) B 83.2/70.6
C2 4030006900 S.CER C1608 JB 1H 103K-T B 106.1/66.5
C4 4030008890 S.CER C1608 JB 1H 273K-T B 88.3/33.9
C5 4510008560 S.ELE EEE1HAR47SR B 88.1/30.8
C6 4030006900 S.CER C1608 JB 1H 103K-T B 84.3/35
C7 4030011600 S.CER C1608 JB 1E 104K-T B 78/65.3
C8 4030011600 S.CER C1608 JB 1E 104K-T B 74.9/63.7
C9 4510008540 S.ELE EEE1CA100SR B 69.7/66.6
C11 4030011600 S.CER C1608 JB 1E 104K-T B 93.4/54.7
C12 4030011600 S.CER C1608 JB 1E 104K-T B 93.1/47.8
C15 4030006850 S.CER C1608 JB 1H 471K-T B 84/39.1
C17 4030011600 S.CER C1608 JB 1E 104K-T B 82.4/41.9
C18 4030007050 S.CER C1608 CH 1H 220J-T B 77.4/42.7
C19 4030007050 S.CER C1608 CH 1H 220J-T B 80.5/42.7
C20 4030011600 S.CER C1608 JB 1E 104K-T B 74.6/42.7
C21 4030006900 S.CER C1608 JB 1H 103K-T B 71.8/42.7
C25 4030011600 S.CER C1608 JB 1E 104K-T B 110.7/60.9
C26 4510008540 S.ELE EEE1CA100SR B 118.8/65.2
C27 4030011600 S.CER C1608 JB 1E 104K-T B 119/68.3
C34 4030006900 S.CER C1608 JB 1H 103K-T B 62.6/38.7
C35 4030011600 S.CER C1608 JB 1E 104K-T B 66.5/38.7
C37 4030006900 S.CER C1608 JB 1H 103K-T B 49.9/21.6
C38 4030011600 S.CER C1608 JB 1E 104K-T B 47.7/22.3
C39 4030006860 S.CER C1608 JB 1H 102K-T B 44.7/22.3
C40 4030006860 S.CER C1608 JB 1H 102K-T B 42.1/22.3
C41 4030006860 S.CER C1608 JB 1H 102K-T B 39.5/22.3
C42 4030006860 S.CER C1608 JB 1H 102K-T B 36.9/22.3
C44 4030006900 S.CER C1608 JB 1H 103K-T B 58.6/42.4
C46 4030006900 S.CER C1608 JB 1H 103K-T B 29.2/42.8
C47 4030006850 S.CER C1608 JB 1H 471K-T B 23.9/42.8
C48 4030006900 S.CER C1608 JB 1H 103K-T B 33.4/38.2
C49 4030007090 S.CER C1608 CH 1H 470J-T B 26.6/22.5
C50 4030007090 S.CER C1608 CH 1H 470J-T B 22/22.9
C51 4030007130 S.CER C1608 CH 1H 101J-T B 15.1/45.1
C52 4030007130 S.CER C1608 CH 1H 101J-T B 12.9/64.4
C53 4030006900 S.CER C1608 JB 1H 103K-T B 15.2/24.8
C55 4030011600 S.CER C1608 JB 1E 104K-T B 42.2/61.5
C56 4510008540 S.ELE EEE1CA100SR B 46.4/63.5
C57 4030011600 S.CER C1608 JB 1E 104K-T B 64/68.9
C58 4030006900 S.CER C1608 JB 1H 103K-T B 64/67.6
C59 4030006900 S.CER C1608 JB 1H 103K-T B 49.7/66.9
C60 4030006900 S.CER C1608 JB 1H 103K-T B 64/59.4
C61 4550007370 S.TAN F931V225MBABMA B 46.4/69.3
C62 4550007370 S.TAN F931V225MBABMA B 36/84.6
C63 4550007370 S.TAN F931V225MBABMA B 36/81.3
C64 4550007370 S.TAN F931V225MBABMA B 46.4/72.7
C65 4550007650 S.TAN F931V105MAABMA B 43.3/85.2
C66 4550007650 S.TAN F931V105MAABMA B 43.3/83.1
C67 4550007650 S.TAN F931V105MAABMA B 43.3/81
C68 4550007650 S.TAN F931V105MAABMA B 43.3/78.9
C69 4550007650 S.TAN F931V105MAABMA B 43.3/76.8
C71 4030006860 S.CER C1608 JB 1H 102K-T B 45.4/56.7
C72 4510008540 S.ELE EEE1CA100SR B 41.9/54.1
C73 4030006900 S.CER C1608 JB 1H 103K-T B 48.2/56.7
C74 4510008540 S.ELE EEE1CA100SR B 51.7/54.1
C101 4030006860 S.CER C1608 JB 1H 102K-T B 81/73.6
C103 4030006860 S.CER C1608 JB 1H 102K-T B 82.3/73.6
C104 4030007090 S.CER C1608 CH 1H 470J-T B 82.3/84.3
C105 4030007090 S.CER C1608 CH 1H 470J-T B 83.6/73.6
C106 4030007090 S.CER C1608 CH 1H 470J-T B 83.6/84.3
C107 4030007090 S.CER C1608 CH 1H 470J-T B 84.9/73.6
C108 4030006860 S.CER C1608 JB 1H 102K-T B 86.2/73.6
C109 4030006860 S.CER C1608 JB 1H 102K-T B 85.3/84.3
• IC-M604
[REPLACEMENT UNITS]
ORDER NO. UNIT NAME COLOR
0325770121
0325770122
U M604 #21 FRONT (including LOGIC UNIT)
U M604 #22 FRONT (including LOGIC UNIT)
BLACK
GRAY
[LOGIC UNIT]
REF ORDER DESCRIPTION M. H/V
NO. NO.
LOCATION
IC1 1140013650 S.IC HD64F2633RF28 (FX-2577D) B 80/53
IC2 1110005771 S.IC S-80942CNMC-G9CT2G B 88.3/36.4
IC4 1140008650 S.IC HN58X2464TI B 104.6/61
IC5 1180002380 S.IC S-817B33AMC-CWW-T2G B 41.9/59
IC6 1130013200 S.IC TC74LCXR164245 (E F) B 56.4/65.7
IC8 1180000421 S.IC TA78L05F (TE12) B 46.8/53.3
Q4 1530003960 S.TR KTC2875-B-RTK/P B 99.8/42.1
Q12 1590003670 S.TR KRA304-RTK/P B 98.8/73.8
Q13 1590003670 S.TR KRA304-RTK/P B 96.3/73.8
Q15 1530003900 S.TR KTC4075 BL-RTK/P B 113.9/59
Q16 1530003900 S.TR KTC4075 BL-RTK/P B 113.9/61.6
Q17 1520000840 S.TR KTA1664Y-RTF/P B 118.3/60.2
D1 1790001561 S.DIO 1SS372 (TE85) B 94.2/43.1
D3 1730002360 S.ZEN MA8062-M (TX) B 23.5/41.2
D4 1730002360 S.ZEN MA8062-M (TX) B 29.6/41.2
D5 1730002360 S.ZEN MA8062-M (TX) B 33.5/39.9
D6 1750001320 S.DIO KDS4148U RTK/P B 80.3/33.5
X1 6050011090 S.XTL CR-691 (9.8304 MHz) B 75.3/39.4
R4 7030003560 S.RES ERJ3GEYJ 103 V (10 k) B 104.7/66.5
R5 7030003560 S.RES ERJ3GEYJ 103 V (10 k) B 103.4/66.5
R6 7030003680 S.RES ERJ3GEYJ 104 V (100 k) B 96.2/31.9
R7 7030010610 S.RES ERJ1TYJ 470U (47) B 56/53
R8 7030003570 S.RES ERJ3GEYJ 123 V (12 k) B 86.7/40.1
R9 7030003620 S.RES ERJ3GEYJ 333 V (33 k) B 85.1/37
R10 7030003640 S.RES ERJ3GEYJ 473 V (47 k) B 85.9/35
R12 7030003680 S.RES ERJ3GEYJ 104 V (100 k) B 64/66.2
R13 7030003680 S.RES ERJ3GEYJ 104 V (100 k) B 64/64.9
R14 7030003680 S.RES ERJ3GEYJ 104 V (100 k) B 64/63.6
R15 7030003680 S.RES ERJ3GEYJ 104 V (100 k) B 64/62
R16 7030003680 S.RES ERJ3GEYJ 104 V (100 k) B 64/60.7
R17 7030003680 S.RES ERJ3GEYJ 104 V (100 k) B 102.7/47.6
R18 7030003680 S.RES ERJ3GEYJ 104 V (100 k) B 104.1/48.2
R23 7030003570 S.RES ERJ3GEYJ 123 V (12 k) B 110.2/69.8
R24 7030003450 S.RES ERJ3GEYJ 122 V (1.2 k) B 59.9/53.3
R25 7030003450 S.RES ERJ3GEYJ 122 V (1.2 k) B 88.1/66.6
R27 7030003570 S.RES ERJ3GEYJ 123 V (12 k) B 66.7/63.5
R28 7030003570 S.RES ERJ3GEYJ 123 V (12 k) B 66.7/62.2
R29 7030003570 S.RES ERJ3GEYJ 123 V (12 k) B 66.7/60.9
R31 7030003440 S.RES ERJ3GEYJ 102 V (1 k) B 98.9/48.5
R32 7030003440 S.RES ERJ3GEYJ 102 V (1 k) B 97.6/48.5
R33 7030003580 S.RES ERJ3GEYJ 153 V (15 k) B 99.8/45.7
R34 7030003640 S.RES ERJ3GEYJ 473 V (47 k) B 99.8/44.4
R35 7030003500 S.RES ERJ3GEYJ 332 V (3.3 k) B 84/41.9
R36 7030003680 S.RES ERJ3GEYJ 104 V (100 k) B 100.2/48.5
R37 7030003570 S.RES ERJ3GEYJ 123 V (12 k) B 104.3/73.3
R38 7030003680 S.RES ERJ3GEYJ 104 V (100 k) B 46/58.3
R39 7030003330 S.RES ERJ3GEYJ 121 V (120) B 93.6/88.2
R40 7030003330 S.RES ERJ3GEYJ 121 V (120) B 57.7/88.2
R41 7030003630 S.RES ERJ3GEYJ 393 V (39 k) B 110.7/58.3
R42 7030003640 S.RES ERJ3GEYJ 473 V (47 k) B 110.7/59.6
R43 7030003440 S.RES ERJ3GEYJ 102 V (1 k) B 110.7/62.2
R44 7030003560 S.RES ERJ3GEYJ 103 V (10 k) B 114.3/63.5
R45 7030003500 S.RES ERJ3GEYJ 332 V (3.3 k) B 110.7/63.5
R46 7030003360 S.RES ERJ3GEYJ 221 V (220) B 128/51.9