Infineon Technologies XC161 User manual

User’s Manual, V2.2, Jan. 2004
Microcontrollers
Never stop thinking.
XC161
Volume 2 (of 2): Peripheral Units
16-Bit Single-Chip Microcontroller
with C166SV2 Core

Edition 2004-01
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
©Infineon Technologies AG 2004.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.

User’s Manual, V2.2, Jan. 2004
Microcontrollers
Never stop thinking.
XC161
Volume 2 (of 2): Peripheral Units
16-Bit Single-Chip Microcontroller
with C166SV2 Core

Template: mc_tmplt_a5.fm / 3 / 2003-09-01
Controller Area Network (CAN): License of Robert Bosch GmbH
XC161 Volume 2 (of 2): Peripheral Units
Revision History: V2.2, 2004-01
Previous Version: V2.2, 2003-09 (Pre-release)
V2.1, 2003-06
V2.0, 2003-03
V1.1, 2002-02 (Draft Manual)
V1.0, 2001-04 (Draft Manual)
Page Subjects (major changes since version V2.1)1)
1) In order to create the current version V2.2 of this manual, the layout of several graphics and text structures
has been adapted to company documentation rules. The contents have not been changed otherwise, except
for the Pre-release note on page 1-2 or obvious typographical errors.
14-1ff Timer block description introduced
14-7 Phrasing improved
14-26 Figure corrected
14-27 Prescaler table reworked
14-29 Timer register description added
14-35 Phrasing improved
14-50 Prescaler table reworked
14-53 Timer register description added
17-1ff Register names adapted
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
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XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Table of Contents Page
User’s Manual I-1 V2.2, 2004-01
This User’s Manual consists of two Volumes, “System Units” and “Peripheral Units”. For
your convenience this table of contents (and also the keyword index) lists both volumes,
so can immediately find the reference to the desired section in the corresponding
document ([1] or [2]).
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 [1]
1.1 Members of the 16-bit Microcontroller Family . . . . . . . . . . . . . . . . . . . 1-3 [1]
1.2 Summary of Basic Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 [1]
1.3 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 [1]
1.4 Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 [1]
2 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 [1]
2.1 Basic CPU Concepts and Optimizations . . . . . . . . . . . . . . . . . . . . . . . 2-2 [1]
2.1.1 High Instruction Bandwidth/Fast Execution . . . . . . . . . . . . . . . . . . . 2-4 [1]
2.1.2 Powerful Execution Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 [1]
2.1.3 High Performance Branch-, Call-, and Loop-Processing . . . . . . . . . 2-6 [1]
2.1.4 Consistent and Optimized Instruction Formats . . . . . . . . . . . . . . . . 2-7 [1]
2.1.5 Programmable Multiple Priority Interrupt System . . . . . . . . . . . . . . 2-8 [1]
2.1.6 Interfaces to System Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 [1]
2.2 On-Chip System Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 [1]
2.3 On-Chip Peripheral Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 [1]
2.4 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 [1]
2.5 Power Management Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 [1]
2.6 On-Chip Debug Support (OCDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31 [1]
2.7 Protected Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32 [1]
3 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 [1]
3.1 Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 [1]
3.2 Special Function Register Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 [1]
3.3 Data Memory Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 [1]
3.4 Program Memory Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 [1]
3.5 System Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 [1]
3.6 IO Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 [1]
3.7 External Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 [1]
3.8 Crossing Memory Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 [1]
3.9 The On-Chip Program Flash Module . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 [1]
3.9.1 Flash Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 [1]
3.9.2 Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 [1]
3.9.3 Error Correction and Data Integrity . . . . . . . . . . . . . . . . . . . . . . . . 3-25 [1]
3.9.4 Protection and Security Features . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 [1]
3.9.5 Flash Status Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 [1]
3.9.6 Operation Control and Error Handling . . . . . . . . . . . . . . . . . . . . . . 3-35 [1]

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Table of Contents Page
User’s Manual I-2 V2.2, 2004-01
3.10 Program Memory Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37 [1]
3.10.1 Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38 [1]
3.10.2 Flash Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39 [1]
3.10.3 IMB Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41 [1]
4 Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 [1]
4.1 Components of the CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 [1]
4.2 Instruction Fetch and Program Flow Control . . . . . . . . . . . . . . . . . . . . 4-5 [1]
4.2.1 Branch Detection and Branch Prediction Rules . . . . . . . . . . . . . . . . 4-7 [1]
4.2.2 Correctly Predicted Instruction Flow . . . . . . . . . . . . . . . . . . . . . . . . 4-7 [1]
4.2.3 Incorrectly Predicted Instruction Flow . . . . . . . . . . . . . . . . . . . . . . . 4-9 [1]
4.3 Instruction Processing Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 [1]
4.3.1 Pipeline Conflicts Using General Purpose Registers . . . . . . . . . . . 4-13 [1]
4.3.2 Pipeline Conflicts Using Indirect Addressing Modes . . . . . . . . . . . 4-15 [1]
4.3.3 Pipeline Conflicts Due to Memory Bandwidth . . . . . . . . . . . . . . . . 4-17 [1]
4.3.4 Pipeline Conflicts Caused by CPU-SFR Updates . . . . . . . . . . . . . 4-20 [1]
4.4 CPU Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26 [1]
4.5 Use of General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 4-29 [1]
4.5.1 GPR Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31 [1]
4.5.2 Context Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-33 [1]
4.6 Code Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37 [1]
4.7 Data Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39 [1]
4.7.1 Short Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39 [1]
4.7.2 Long Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41 [1]
4.7.3 Indirect Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-45 [1]
4.7.4 DSP Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-47 [1]
4.7.5 The System Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-53 [1]
4.8 Standard Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-57 [1]
4.8.1 16-bit Adder/Subtracter, Barrel Shifter, and 16-bit Logic Unit . . . . 4-61 [1]
4.8.2 Bit Manipulation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-61 [1]
4.8.3 Multiply and Divide Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-63 [1]
4.9 DSP Data Processing (MAC Unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-65 [1]
4.9.1 Representation of Numbers and Rounding . . . . . . . . . . . . . . . . . . 4-66 [1]
4.9.2 The 16-bit by 16-bit Signed/Unsigned Multiplier and Scaler . . . . . 4-67 [1]
4.9.3 Concatenation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-67 [1]
4.9.4 One-bit Scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-67 [1]
4.9.5 The 40-bit Adder/Subtracter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-67 [1]
4.9.6 The Data Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-68 [1]
4.9.7 The Accumulator Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-68 [1]
4.9.8 The 40-bit Signed Accumulator Register . . . . . . . . . . . . . . . . . . . . 4-69 [1]
4.9.9 The MAC Unit Status Word MSW . . . . . . . . . . . . . . . . . . . . . . . . . 4-70 [1]
4.9.10 The Repeat Counter MRW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-72 [1]
4.10 Constant Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-74 [1]

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Table of Contents Page
User’s Manual I-3 V2.2, 2004-01
5 Interrupt and Trap Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 [1]
5.1 Interrupt System Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 [1]
5.2 Interrupt Arbitration and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 [1]
5.3 Interrupt Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 [1]
5.4 Operation of the Peripheral Event Controller Channels . . . . . . . . . . 5-18 [1]
5.4.1 The PEC Source and Destination Pointers . . . . . . . . . . . . . . . . . . 5-22 [1]
5.4.2 PEC Transfer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24 [1]
5.4.3 Channel Link Mode for Data Chaining . . . . . . . . . . . . . . . . . . . . . . 5-26 [1]
5.4.4 PEC Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27 [1]
5.5 Prioritization of Interrupt and PEC Service Requests . . . . . . . . . . . . 5-29 [1]
5.6 Context Switching and Saving Status . . . . . . . . . . . . . . . . . . . . . . . . 5-31 [1]
5.7 Interrupt Node Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34 [1]
5.8 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35 [1]
5.9 OCDS Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40 [1]
5.10 Service Request Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41 [1]
5.11 Trap Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-43 [1]
6 General System Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 [1]
6.1 System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 [1]
6.1.1 Reset Sources and Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 [1]
6.1.2 Status After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 [1]
6.1.3 Application-Specific Initialization Routine . . . . . . . . . . . . . . . . . . . 6-11 [1]
6.1.4 System Startup Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 [1]
6.1.5 Hardware Configuration in External Start Mode . . . . . . . . . . . . . . 6-18 [1]
6.1.6 Default Configuration in Single-Chip Mode . . . . . . . . . . . . . . . . . . 6-23 [1]
6.1.7 Reset Behavior Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24 [1]
6.2 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26 [1]
6.2.1 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27 [1]
6.2.2 Clock Generation and Frequency Control . . . . . . . . . . . . . . . . . . . 6-30 [1]
6.2.3 Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37 [1]
6.2.4 Oscillator Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38 [1]
6.2.5 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38 [1]
6.2.6 Generation of an External Clock Signal . . . . . . . . . . . . . . . . . . . . 6-39 [1]
6.3 Central System Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-43 [1]
6.3.1 Status Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-45 [1]
6.3.2 Reset Source Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46 [1]
6.3.3 Peripheral Shutdown Handshake . . . . . . . . . . . . . . . . . . . . . . . . . 6-47 [1]
6.3.4 Flexible Peripheral Management . . . . . . . . . . . . . . . . . . . . . . . . . . 6-47 [1]
6.3.5 Debug System Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49 [1]
6.3.6 Register Security Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-51 [1]
6.4 Watchdog Timer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-55 [1]
6.5 Identification Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-60 [1]

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User’s Manual I-4 V2.2, 2004-01
7 Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 [1]
7.1 Input Threshold Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 [1]
7.2 Output Driver Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 [1]
7.3 Alternate Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 [1]
7.4 PORT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 [1]
7.5 PORT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 [1]
7.6 Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24 [1]
7.7 Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-29 [1]
7.8 Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-41 [1]
7.9 Port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-51 [1]
7.10 Port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-54 [1]
7.11 Port 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-65 [1]
7.12 Port 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-72 [1]
7.13 Port 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-82 [1]
8 Dedicated Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 [1]
9 The External Bus Controller EBC . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 [1]
9.1 External Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 [1]
9.2 Timing Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 [1]
9.2.1 Basic Bus Cycle Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 [1]
9.2.1.1 Demultiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 [1]
9.2.1.2 Multiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 [1]
9.2.2 Bus Cycle Phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 [1]
9.2.2.1 A Phase - CS Change Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 [1]
9.2.2.2 B Phase - Address Setup/ALE Phase . . . . . . . . . . . . . . . . . . . . . 9-7 [1]
9.2.2.3 C Phase - Delay Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 [1]
9.2.2.4 D Phase - Write Data Setup/MUX Tristate Phase . . . . . . . . . . . . 9-7 [1]
9.2.2.5 E Phase - RD/WR Command Phase . . . . . . . . . . . . . . . . . . . . . . 9-7 [1]
9.2.2.6 F Phase - Address/Write Data Hold Phase . . . . . . . . . . . . . . . . . 9-8 [1]
9.2.3 Bus Cycle Examples: Fastest Access Cycles . . . . . . . . . . . . . . . . . 9-8 [1]
9.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 [1]
9.3.1 Configuration Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 [1]
9.3.2 The EBC Mode Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 [1]
9.3.3 The EBC Mode Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 [1]
9.3.4 The Timing Configuration Registers TCONCSx . . . . . . . . . . . . . . 9-15 [1]
9.3.5 The Function Configuration Registers FCONCSx . . . . . . . . . . . . . 9-16 [1]
9.3.6 The Address Window Selection Registers ADDRSELx . . . . . . . . . 9-18 [1]
9.3.6.1 Definition of Address Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-18 [1]
9.3.6.2 Address Window Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-20 [1]
9.3.7 Ready Controlled Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21 [1]
9.3.7.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-21 [1]
9.3.7.2 The Synchronous/Asynchronous READY . . . . . . . . . . . . . . . . . 9-22 [1]

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9.3.7.3 Combining the READY Function with Predefined Wait States . 9-22 [1]
9.3.8 Access Control to TwinCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-23 [1]
9.3.9 External Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24 [1]
9.3.9.1 Initialization of Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24 [1]
9.3.9.2 Arbitration Master Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-24 [1]
9.3.9.3 Arbitration Slave Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-26 [1]
9.3.9.4 Bus Lock Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27 [1]
9.3.9.5 Direct Master Slave Connection . . . . . . . . . . . . . . . . . . . . . . . . 9-27 [1]
9.3.10 Shutdown Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-28 [1]
9.4 LXBus Access Control and Signal Generation . . . . . . . . . . . . . . . . . 9-29 [1]
9.5 EBC Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-29 [1]
10 The Bootstrap Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 [1]
10.1 Entering the Bootstrap Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 [1]
10.2 Loading the Startup Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 [1]
10.3 Exiting Bootstrap Loader Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 [1]
10.4 Choosing the Baudrate for the BSL . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 [1]
11 Debug System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 [1]
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 [1]
11.2 Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 [1]
11.3 OCDS Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 [1]
11.3.1 Debug Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 [1]
11.3.2 Debug Actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 [1]
11.4 Cerberus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 [1]
11.4.1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 [1]
11.5 Emulation Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 [1]
12 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 [1]
13 Device Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 [1]
14 The General Purpose Timer Units . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 [2]
14.1 Timer Block GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 [2]
14.1.1 GPT1 Core Timer T3 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 [2]
14.1.2 GPT1 Core Timer T3 Operating Modes . . . . . . . . . . . . . . . . . . . . . 14-8 [2]
14.1.3 GPT1 Auxiliary Timers T2/T4 Control . . . . . . . . . . . . . . . . . . . . . 14-15 [2]
14.1.4 GPT1 Auxiliary Timers T2/T4 Operating Modes . . . . . . . . . . . . . 14-18 [2]
14.1.5 GPT1 Clock Signal Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-27 [2]
14.1.6 GPT1 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-29 [2]
14.1.7 Interrupt Control for GPT1 Timers . . . . . . . . . . . . . . . . . . . . . . . . 14-30 [2]
14.2 Timer Block GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-31 [2]
14.2.1 GPT2 Core Timer T6 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-33 [2]
14.2.2 GPT2 Core Timer T6 Operating Modes . . . . . . . . . . . . . . . . . . . . 14-36 [2]

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14.2.3 GPT2 Auxiliary Timer T5 Control . . . . . . . . . . . . . . . . . . . . . . . . 14-39 [2]
14.2.4 GPT2 Auxiliary Timer T5 Operating Modes . . . . . . . . . . . . . . . . . 14-41 [2]
14.2.5 GPT2 Register CAPREL Operating Modes . . . . . . . . . . . . . . . . . 14-45 [2]
14.2.6 GPT2 Clock Signal Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-50 [2]
14.2.7 GPT2 Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-53 [2]
14.2.8 Interrupt Control for GPT2 Timers and CAPREL . . . . . . . . . . . . . 14-54 [2]
14.3 Interfaces of the GPT Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-55 [2]
15 Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 [2]
15.1 Defining the RTC Time Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 [2]
15.2 RTC Run Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 [2]
15.3 RTC Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 [2]
15.3.1 48-bit Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10 [2]
15.3.2 System Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10 [2]
15.3.3 Cyclic Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11 [2]
15.4 RTC Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12 [2]
16 The Analog/Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 [2]
16.1 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 [2]
16.1.1 Compatibility Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 [2]
16.1.2 Enhanced Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5 [2]
16.2 ADC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8 [2]
16.2.1 Fixed Channel Conversion Modes . . . . . . . . . . . . . . . . . . . . . . . . 16-11 [2]
16.2.2 Auto Scan Conversion Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12 [2]
16.2.3 Wait for Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13 [2]
16.2.4 Channel Injection Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14 [2]
16.3 Automatic Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-17 [2]
16.4 Conversion Timing Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-18 [2]
16.5 A/D Converter Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-21 [2]
16.6 Interfaces of the ADC Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-22 [2]
17 Capture/Compare Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 [2]
17.1 The CAPCOM Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 [2]
17.2 CAPCOM Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9 [2]
17.3 Capture/Compare Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10 [2]
17.4 Capture Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13 [2]
17.5 Compare Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-14 [2]
17.5.1 Compare Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-15 [2]
17.5.2 Compare Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-15 [2]
17.5.3 Compare Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-18 [2]
17.5.4 Compare Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-18 [2]
17.5.5 Double-Register Compare Mode . . . . . . . . . . . . . . . . . . . . . . . . 17-22 [2]
17.6 Compare Output Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . 17-25 [2]
17.7 Single Event Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-27 [2]

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17.8 Staggered and Non-Staggered Operation . . . . . . . . . . . . . . . . . . . . 17-29 [2]
17.9 CAPCOM Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-34 [2]
17.10 External Input Signal Requirements . . . . . . . . . . . . . . . . . . . . . . . . 17-36 [2]
17.11 Interfaces of the CAPCOM Units . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-37 [2]
18 Asynchronous/Synchronous Serial Interface (ASC) . . . . . . . . . . 18-1 [2]
18.1 Operational Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 [2]
18.2 Asynchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5 [2]
18.2.1 Asynchronous Data Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6 [2]
18.2.2 Asynchronous Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9 [2]
18.2.3 Transmit FIFO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9 [2]
18.2.4 Asynchronous Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-12 [2]
18.2.5 Receive FIFO Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-12 [2]
18.2.6 FIFO Transparent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-15 [2]
18.2.7 IrDA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-16 [2]
18.2.8 RxD/TxD Data Path Selection in Asynchronous Modes . . . . . . . 18-17 [2]
18.3 Synchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-19 [2]
18.3.1 Synchronous Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-20 [2]
18.3.2 Synchronous Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-20 [2]
18.3.3 Synchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-20 [2]
18.4 Baudrate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-22 [2]
18.4.1 Baudrate in Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . 18-22 [2]
18.4.2 Baudrate in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . 18-26 [2]
18.5 Autobaud Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-27 [2]
18.5.1 General Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-27 [2]
18.5.2 Serial Frames for Autobaud Detection . . . . . . . . . . . . . . . . . . . . . 18-28 [2]
18.5.3 Baudrate Selection and Calculation . . . . . . . . . . . . . . . . . . . . . . . 18-29 [2]
18.5.4 Overwriting Registers on Successful Autobaud Detection . . . . . 18-33 [2]
18.6 Hardware Error Detection Capabilities . . . . . . . . . . . . . . . . . . . . . . 18-34 [2]
18.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-35 [2]
18.8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-39 [2]
18.9 Interfaces of the ASC Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-56 [2]
19 High-Speed Synchronous Serial Interface (SSC) . . . . . . . . . . . . 19-1 [2]
19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 [2]
19.2 Operational Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 [2]
19.2.1 Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3 [2]
19.2.2 Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-8 [2]
19.2.3 Half-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-11 [2]
19.2.4 Continuous Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-12 [2]
19.2.5 Baudrate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-12 [2]
19.2.6 Error Detection Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-14 [2]
19.2.7 SSC Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-16 [2]

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19.2.8 Port Configuration Requirements . . . . . . . . . . . . . . . . . . . . . . . . 19-17 [2]
19.3 Interfaces of the SSC Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-18 [2]
20 IIC-Bus Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 [2]
20.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2 [2]
20.2 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5 [2]
20.3 IIC-Bus Module Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-12 [2]
20.3.1 Operation in Single-Master Mode . . . . . . . . . . . . . . . . . . . . . . . . 20-12 [2]
20.3.2 Operation in Multimaster Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 20-12 [2]
20.3.3 Operation in Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-13 [2]
20.3.4 Transmit/Receive Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-14 [2]
20.3.5 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-15 [2]
20.3.6 Notes for Programming the IIC-Bus Module . . . . . . . . . . . . . . . . 20-16 [2]
20.4 Interrupt Request Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-17 [2]
20.5 Port Connection and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 20-19 [2]
20.6 Interfaces of the IIC-Bus Module . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-21 [2]
20.7 IIC-Bus Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-22 [2]
21 TwinCAN Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 [2]
21.1 Kernel Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 [2]
21.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 [2]
21.1.2 TwinCAN Control Shell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4 [2]
21.1.2.1 Initialization Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4 [2]
21.1.2.2 Interrupt Request Compressor . . . . . . . . . . . . . . . . . . . . . . . . . 21-5 [2]
21.1.2.3 Global Control and Status Logic . . . . . . . . . . . . . . . . . . . . . . . . 21-6 [2]
21.1.3 CAN Node Control Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7 [2]
21.1.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7 [2]
21.1.3.2 Timing Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9 [2]
21.1.3.3 Bitstream Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-11 [2]
21.1.3.4 Error Handling Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-11 [2]
21.1.3.5 Node Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-12 [2]
21.1.3.6 Message Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . 21-13 [2]
21.1.3.7 Interrupt Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-13 [2]
21.1.4 Message Handling Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-15 [2]
21.1.4.1 Arbitration and Acceptance Mask Register . . . . . . . . . . . . . . . 21-16 [2]
21.1.4.2 Handling of Remote and Data Frames . . . . . . . . . . . . . . . . . . 21-17 [2]
21.1.4.3 Handling of Transmit Message Objects . . . . . . . . . . . . . . . . . . 21-18 [2]
21.1.4.4 Handling of Receive Message Objects . . . . . . . . . . . . . . . . . . 21-21 [2]
21.1.4.5 Single Data Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-23 [2]
21.1.5 CAN Message Object Buffer (FIFO) . . . . . . . . . . . . . . . . . . . . . . 21-24 [2]
21.1.5.1 Buffer Access by the CAN Controller . . . . . . . . . . . . . . . . . . . 21-26 [2]
21.1.5.2 Buffer Access by the CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-27 [2]
21.1.6 Gateway Message Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-28 [2]

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Table of Contents Page
User’s Manual I-9 V2.2, 2004-01
21.1.6.1 Normal Gateway Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-29 [2]
21.1.6.2 Normal Gateway with FIFO Buffering . . . . . . . . . . . . . . . . . . . 21-33 [2]
21.1.6.3 Shared Gateway Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-36 [2]
21.1.7 Programming the TwinCAN Module . . . . . . . . . . . . . . . . . . . . . . 21-40 [2]
21.1.7.1 Configuration of CAN Node A/B . . . . . . . . . . . . . . . . . . . . . . . 21-40 [2]
21.1.7.2 Initialization of Message Objects . . . . . . . . . . . . . . . . . . . . . . . 21-40 [2]
21.1.7.3 Controlling a Message Transfer . . . . . . . . . . . . . . . . . . . . . . . 21-41 [2]
21.1.8 Loop-Back Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-44 [2]
21.1.9 Single Transmission Try Functionality . . . . . . . . . . . . . . . . . . . . 21-45 [2]
21.1.10 Module Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-46 [2]
21.2 TwinCAN Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-47 [2]
21.2.1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-47 [2]
21.2.2 CAN Node A/B Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-49 [2]
21.2.3 CAN Message Object Registers . . . . . . . . . . . . . . . . . . . . . . . . . 21-64 [2]
21.2.4 Global CAN Control/Status Registers . . . . . . . . . . . . . . . . . . . . . 21-80 [2]
21.3 XC161 Module Implementation Details . . . . . . . . . . . . . . . . . . . . . . 21-82 [2]
21.3.1 Interfaces of the TwinCAN Module . . . . . . . . . . . . . . . . . . . . . . . 21-82 [2]
21.3.2 TwinCAN Module Related External Registers . . . . . . . . . . . . . . . 21-83 [2]
21.3.2.1 System Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-84 [2]
21.3.2.2 Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-85 [2]
21.3.2.3 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-90 [2]
21.3.3 Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-91 [2]
22 Serial Data Link Module SDLM . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 [2]
22.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 [2]
22.2 SDLM Kernel Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 [2]
22.2.1 J1850 Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 [2]
22.2.1.1 Frame Format Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3 [2]
22.2.1.2 J1850 Bits and Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5 [2]
22.2.1.3 Frame Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 [2]
22.2.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 [2]
22.2.2.1 4x Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8 [2]
22.2.2.2 Break Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8 [2]
22.2.3 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9 [2]
22.2.3.1 Message Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-10 [2]
22.2.3.2 Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-10 [2]
22.2.3.3 Transmit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11 [2]
22.2.4 In-Frame Response (IFR) Operation . . . . . . . . . . . . . . . . . . . . . . 22-12 [2]
22.2.5 Block Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-13 [2]
22.2.6 Bus Access in FIFO Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-15 [2]
22.2.7 Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-16 [2]
22.2.7.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-16 [2]
22.2.7.2 Transmission Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-17 [2]

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
Table of Contents Page
User’s Manual I-10 V2.2, 2004-01
22.2.7.3 Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-20 [2]
22.2.8 IFR Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-22 [2]
22.2.8.1 IFR Types 1, 2 via IFRVAL . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-22 [2]
22.3 SDLM Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-23 [2]
22.3.1 Global Control and Timing Registers . . . . . . . . . . . . . . . . . . . . . . 22-24 [2]
22.4 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-29 [2]
22.4.1 Transmission Related Registers . . . . . . . . . . . . . . . . . . . . . . . . . 22-39 [2]
22.4.2 Reception Related Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-43 [2]
22.5 SDLM Module Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-50 [2]
22.6 XC161 Module Implementation Details . . . . . . . . . . . . . . . . . . . . . . 22-51 [2]
22.6.1 Interfaces of the SDLM Module . . . . . . . . . . . . . . . . . . . . . . . . . . 22-51 [2]
22.6.2 SDLM Module Related External Registers . . . . . . . . . . . . . . . . . 22-53 [2]
22.6.2.1 System Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-54 [2]
22.6.2.2 Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-55 [2]
22.6.2.3 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-60 [2]
23 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 [2]
23.1 PD+BUS Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 [2]
23.2 LXBUS Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-16 [2]
Keyword Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i-1 [1+2]

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
The General Purpose Timer Units
User’s Manual 14-1 V2.2, 2004-01
GPT_X1, V2.0
14 The General Purpose Timer Units
The General Purpose Timer Unit blocks GPT1 and GPT2 have very flexible
multifunctional timer structures which may be used for timing, event counting, pulse
width measurement, pulse generation, frequency multiplication, and other purposes.
They incorporate five 16-bit timers that are grouped into the two timer blocks GPT1 and
GPT2. Each timer in each block may operate independently in a number of different
modes such as gated timer or counter mode, or may be concatenated with another timer
of the same block. Each block has alternate input/output functions and specific interrupts
associated with it.
Block GPT1 contains three timers/counters: The core timer T3 and the two auxiliary
timers T2 and T4. The maximum resolution is fGPT/4. The auxiliary timers of GPT1 may
optionally be configured as reload or capture registers for the core timer. These registers
are listed in Section 14.1.6.
•fGPT/4 maximum resolution
• 3 independent timers/counters
• Timers/counters can be concatenated
• 4 operating modes:
– Timer Mode
– Gated Timer Mode
– Counter Mode
– Incremental Interface Mode
• Reload and Capture functionality
• Separate interrupt lines
Block GPT2 contains two timers/counters: The core timer T6 and the auxiliary timer T5.
The maximum resolution is fGPT/2. An additional Capture/Reload register (CAPREL)
supports capture and reload operation with extended functionality. These registers are
listed in Section 14.2.7. The core timer T6 may be concatenated with timers of the
CAPCOM units (T0, T1, T7, and T8).
The following list summarizes the features which are supported:
•fGPT/2 maximum resolution
• 2 independent timers/counters
• Timers/counters can be concatenated
• 3 operating modes:
– Timer Mode
– Gated Timer Mode
– Counter Mode
• Extended capture/reload functions via 16-bit capture/reload register CAPREL
• Separate interrupt lines

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
The General Purpose Timer Units
User’s Manual 14-2 V2.2, 2004-01
GPT_X1, V2.0
14.1 Timer Block GPT1
From a programmer’s point of view, the GPT1 block is composed of a set of SFRs as
summarized below. Those portions of port and direction registers which are used for
alternate functions by the GPT1 block are shaded.
Figure 14-1 SFRs Associated with Timer Block GPT1
All three timers of block GPT1 (T2, T3, T4) can run in one of 4 basic modes: Timer Mode,
Gated Timer Mode, Counter Mode, or Incremental Interface Mode. All timers can count
up or down. Each timer of GPT1 is controlled by a separate control register TxCON.
Each timer has an input pin TxIN (alternate pin function) associated with it, which serves
as the gate control in gated timer mode, or as the count input in counter mode. The count
direction (up/down) may be programmed via software or may be dynamically altered by
a signal at the External Up/Down control input TxEUD (alternate pin function). An
overflow/underflow of core timer T3 is indicated by the Output Toggle Latch T3OTL,
whose state may be output on the associated pin T3OUT (alternate pin function). The
auxiliary timers T2 and T4 may additionally be concatenated with the core timer T3
(through T3OTL) or may be used as capture or reload registers for the core timer T3.
The current contents of each timer can be read or modified by the CPU by accessing the
corresponding timer count registers T2, T3, or T4, located in the non-bitaddressable SFR
space (see Section 14.1.6). When any of the timer registers is written to by the CPU in
the state immediately preceding a timer increment, decrement, reload, or capture
operation, the CPU write operation has priority in order to guarantee correct results.
mc_gpt0100_registers.vsd
Data Registers Control Registers Port Registers
T2 T2CON T2IC
T3 T3CON T3IC
T4 T4CON T4IC
ODP3
DP3
P3
E
P5
P5DIDIS
ALTSEL0P3 E
Interrupt Control
SYSCON3
Tx GPT1 Timer x Register
TxCON GPT1 Timer x Control Register
TxIC GPT1 Timer x Interrupt Ctrl. Reg.
SYSCON3 System Ctrl. Reg. 3 (Per. Mgmt.)
ODP3 Port 3 Open Drain Control Register
DP3 Port 3 Direction Control Register
P3 Port 3 Data Register
ALTSEL0P3 Port 3 Alternate Output Select Reg.
P5 Port 5 Data Register
P5DIDIS Port 5 Digital Input Disable Reg.

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
The General Purpose Timer Units
User’s Manual 14-3 V2.2, 2004-01
GPT_X1, V2.0
The interrupts of GPT1 are controlled through the Interrupt Control Registers TxIC.
These registers are not part of the GPT1 block. The input and output lines of GPT1 are
connected to pins of ports P3 and P5. The control registers for the port functions are
located in the respective port modules.
Note: The timing requirements for external input signals can be found in Section 14.1.5,
Section 14.3 summarizes the module interface signals, including pins.
Figure 14-2 GPT1 Block Diagram (n = 2 … 5)
T3
Mode
Control
2
n
: 1f
GPT
T2
Mode
Control
Aux. Timer T2
Reload
Capture
T4
Mode
Control Aux. Timer T4
Reload
Capture
Core Ti mer T3 T3OTL
U/D
T2EUD
T2IN
T3IN
T3EUD
T4IN
T4EUD
Toggle Latch
U/D
U/D
Interrupt
Request
(T2IRQ)
Interrupt
Request
(T3IRQ)
Interrupt
Request
(T4IRQ)
mc_gpt0101_bldiax1.vsd
T3OUT
Basic clock
T3CON.BPS1

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
The General Purpose Timer Units
User’s Manual 14-4 V2.2, 2004-01
GPT_X1, V2.0
14.1.1 GPT1 Core Timer T3 Control
The current contents of the core timer T3 are reflected by its count register T3. This
register can also be written to by the CPU, for example, to set the initial start value.
The core timer T3 is configured and controlled via its bitaddressable control register
T3CON.
GPT12E_T3CON
Timer 3 Control Register SFR (FF42H/A1H) Reset Value: 0000H
1514131211109876543210
T3
R
DIR
T3
CH
DIR
T3
ED
GE
BPS1 T3
OTL
T3
OE
T3
UDE
T3
UD T3R T3M T3I
rh rwh rwh rw rwh rw rw rw rw rw rw
Field Bits Typ Description
T3RDIR 15 rh Timer T3 Rotation Direction Flag
0 Timer T3 counts up
1 Timer T3 counts down
T3CHDIR 14 rwh Timer T3 Count Direction Change Flag
This bit is set each time the count direction of timer
T3 changes. T3CHDIR must be cleared by SW.
0 No change of count direction was detected
1 A change of count direction was detected
T3EDGE 13 rwh Timer T3 Edge Detection Flag
The bit is set each time a count edge is detected.
T3EDGE must be cleared by SW.
0 No count edge was detected
1 A count edge was detected
BPS1 [12:11] rw GPT1 Block Prescaler Control
Selects the basic clock for block GPT1
(see also Section 14.1.5)
00 fGPT/8
01 fGPT/4
10 fGPT/32
11 fGPT/16
T3OTL 10 rwh Timer T3 Overflow Toggle Latch
Toggles on each overflow/underflow of T3. Can be
set or reset by software (see separate description)

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
The General Purpose Timer Units
User’s Manual 14-5 V2.2, 2004-01
GPT_X1, V2.0
T3OE 9rwOverflow/Underflow Output Enable
0 Alternate Output Function Disabled
1 State of T3 toggle latch is output on pin T3OUT
T3UDE 8rwTimer T3 External Up/Down Enable
0 Input T3EUD is disconnected
1 Direction influenced by input T3EUD1)
T3UD 7rwTimer T3 Up/Down Control1)
T3R 6rwTimer T3 Run Bit
0 Timer T3 stops
1TimerT3runs
T3M [5:3] rw Timer T3 Mode Control (Basic Operating Mode)
000 Timer Mode
001 Counter Mode
010 Gated Timer Mode with gate active low
011 Gated Timer Mode with gate active high
100 Reserved. Do not use this combination.
101 Reserved. Do not use this combination.
110 Incremental Interface Mode
(Rotation Detection Mode)
111 Incremental Interface Mode
(Edge Detection Mode)
T3I [2:0] rw Timer T3 Input Parameter Selection
Depends on the operating mode, see respective
sections for encoding:
Table 14-7 for Timer Mode and Gated Timer Mode
Table 14-2 for Counter Mode
Table 14-3 for Incremental Interface Mode
1) See Table 14-1 for encoding of bits T3UD and T3EUD.
Field Bits Typ Description

XC161 Derivatives
Peripheral Units (Vol. 2 of 2)
The General Purpose Timer Units
User’s Manual 14-6 V2.2, 2004-01
GPT_X1, V2.0
Timer T3 Run Control
The core timer T3 can be started or stopped by software through bit T3R (Timer T3 Run
Bit). This bit is relevant in all operating modes of T3. Setting bit T3R will start the timer,
clearing bit T3R stops the timer.
In gated timer mode, the timer will only run if T3R = 1 and the gate is active (high or low,
as programmed).
Note: When bit T2RC or T4RC in timer control register T2CON or T4CON is set, bit T3R
will also control (start and stop) the auxiliary timer(s) T2 and/or T4.
Count Direction Control
The count direction of the GPT1 timers (core timer and auxiliary timers) can be controlled
either by software or by the external input pin TxEUD (Timer Tx External Up/Down
Control Input). These options are selected by bits TxUD and TxUDE in the respective
control register TxCON. When the up/down control is provided by software (bit
TxUDE = 0), the count direction can be altered by setting or clearing bit TxUD. When bit
TxUDE = 1, pin TxEUD is selected to be the controlling source of the count direction.
However, bit TxUD can still be used to reverse the actual count direction, as shown in
Table 14-1. The count direction can be changed regardless of whether or not the timer
is running.
Note: When pin TxEUD is used as external count direction control input, it must be
configured as input (its corresponding direction control bit must be cleared).
Table 14-1 GPT1 Timer Count Direction Control
Pin TxEUD Bit TxUDE Bit TxUD Count Direction Bit TxRDIR
X 00CountUp0
X 0 1 Count Down 1
0 10CountUp0
1 1 0 Count Down 1
0 1 1 Count Down 1
1 11CountUp0