Infineon Technologies ICE2PCS Series Guide

AADesign Guide for ICE2PCSxxApp
Never stop thinking.
Power Management & Supply
Design Guide for Boost Type CCM PFC with
ICE2PCSxx
Application note, Ver 1.0, May 2008

Edition 2008-08-01
Published by Infineon Technologies Asia Pacific,
168 Kallang Way,
349253 Singapore, Singapore
© Infineon Technologies AP 2005.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee
of characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement,
regarding circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types
in question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express
written approval of Infineon Technologies, if a failure of such components can reasonably be expected to
cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or
system. Life support devices or systems are intended to be implanted in the human body, or to support
and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.

Revision History: 2008-08 V1.0
Previous Version: none
Page Subjects (major changes since last revision)
Design Guide for Boost Type CCM PFC with ICE2PCSxx
License to Infineon Technologies Asia Pacific Pte Ltd AN-PS0029
Liu Jianwei
Luo Junyang
Jeoh Meng Kiat
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
mailto:[email protected]

ICE2PCSxx
Table of Contents Page
Application Note 4 2008-08-01
1Introduction ...................................................................................................................................5
2Boost PFC design with ICE2PCXX ..............................................................................................7
2.1 Target specification .........................................................................................................................7
2.2 Bridge rectifier .................................................................................................................................7
2.3 Power MOSFET and Gate Drive Circuit .........................................................................................7
2.4 Boost Diode.....................................................................................................................................8
2.5 Boost inductor .................................................................................................................................9
2.6 AC line current filter.......................................................................................................................11
2.7 Boost Output Bulk Capacitance ....................................................................................................12
2.8 Current Sense Resistor.................................................................................................................12
2.9 Output voltage sensing divider......................................................................................................13
2.10 Frequency setting (only for ICE2PCS01)......................................................................................13
2.11 AC Brown-out Shutdown (only for ICE2PCS02) ...........................................................................14
2.12 IC supply .......................................................................................................................................15
2.13 PCB layout guide ..........................................................................................................................16
3Voltage loop and current loop compensation..........................................................................17
3.1 How to achieve PFC function without sinusoidal reference sensing ............................................18
3.2 Current Loop Regulation and Transfer Function...........................................................................19
3.3 Voltage Loop Compensation.........................................................................................................22
3.4 Design Example ............................................................................................................................28
3.5 Vcomp and M1, M2 value at full load condition ............................................................................29

Application Note 5 2008-08-01
Abstract
ICE2PCS01/02 are the 2nd generation of Continuous Conduction Mode (CCM) PFC controllers, which
employ BiCMOS technology. Its control scheme does not need the direct sine-wave sensing reference
signal from the AC mains compared to the conventional PFC solution. Average current control is
implemented to achieve the unity power factor. In this application note, the design process for the boost PFC
with ICE2PCXX is presented and the design details for a 300W output power PFC with the universal input
voltage range of 85~265VAC are included.
1 Introduction
The Pin layout of ICE2PCS01 and ICE2PCS02 is shown in Figure 1.
1
6
7
8
4
3
2
5
GATEGND
ICOMP
ISENSE
VCC
VSENSE
FREQ VCOMP
1
6
7
8
4
3
2
5
GATEGND
ICOMP
ISENSE
VCC
VSENSE
VINS VCOMP
ICE2PCS01 ICE2PCS02
Figure 1 Pin Layout of ICE2PCS01 and ICE2PCS02
From the layout, it can be seen that most of Pins in ICE2PCS02 are the same as ICE2PCS01 except Pin 4.
In ICE2PCS01, Pin 4 is to set the switching frequency. However, for ICE2PCS02, Pin 4 is for AC brown out
detection and the switching frequency is fixed by internal oscillator at 65kHz. The typical application circuits
of ICE2PCS01 and ICE2PCS02 are shown in Figure 2 and Figure 3 respectively.

Application Note 6 2008-08-01
Figure 2 Typical application circuit of ICE2PCS01
Figure 3 Typical application circuit of ICE2PCS02
L1
T1
R1
R2
C
OUT
RSENSE
EMI Filte
r
R3
GATE GND VSENSE
ISENSE
C1 C2
R4
C3
VCOMP
VINS ICOMP
VCC Auxiliary Supply
ICE2PCS02
Rectifie
r
VIN=85V ...265V AC
V
OUT=400VDC
C4
R6
R5
D
2
D1
L1
T1
R1
R2
C
OUT
RSENSE
EMI Filte
r
R3
GATE GND VSENSE
ISENSE
C1 C2
R4
C3
VCOMP
FREQ
ICOMP
VCC
Auxiliary Supply ICE2PCS01
Rectifie
r
VIN=85V ...265V AC
RFREQ
V
OUT
=400VDC
D1

Application Note 7 2008-08-01
2 Boost PFC design with ICE2PCXX
2.1 Target specification
The fundamental electrical data of the circuit are the input voltage range Vin, the output power Pout, the
output voltage Vout, the operating switching frequency fSW and the value of the high frequency ripple of the
AC line current Iripple. Table 1 shows the relevant values for the system calculated in this Application Note.
The efficiency at rated output power Pout is estimated to 91 % over the complete input voltage range.
Input voltage 85VAC~265VAC
Input frequency 50Hz
Output voltage and current 390VDC, 0.76A
Output power 300W
Efficiency >90% at full load
Switching Frequency 65kHz
Maximum Ambient temperature around PFC 70ºC
Table 1 Design parameter for the proposed design
2.2 Bridge rectifier
In order to obtain 300W output power at 85 V minimum AC input voltage, the maximum input RMS current is
A
V
P
I
in
out
RMSin 92.3
%9085
300
min_
_=
⋅
=
⋅
=
η
(1)
and the sinusoidal peak value of AC current is
AII RMSinpkin 54.592.322 __ =⋅=⋅= (2)
For these values a bridge rectifier with an average current capability of 6A or higher is a good choice. Please
note here, that due to a power dissipation of approximately
WAVIVP RMSinFBR 84.792.3122 _=⋅⋅=⋅⋅= (3)
the rectifier bridge should be connected to an appropriate heatsink. Assuming a maximum junction
temperature TJmax of 125°C, a maximum ambient temperature TAmax of 70°C, the thermal junction-to-case
RthJC of approximate 2.5 K/W and the thermal case to heatsink RthCHS of approximate 1K/W, the heatsink
must have a maximum thermal resistance of
WKRR
P
TT
RthCHSthJC
BR
AJ
BRthHS /52.315.2
84.7
70125
maxmax
_=−−
−
=−−
−
=(4)
2.3 Power MOSFET and Gate Drive Circuit
Due to the switch mode operation, the loss is only valid during the on-time of the MOSFET. The duty cycle of
the transistor in boost converters operating in CCM at minimum AC input RMS voltage is
782.0
390
85
11 min_ =−=−=
out
in
on V
V
D(5)

Application Note 8 2008-08-01
Since rms-values have the same effect on a system as DC-values, it is possible to calculate a characteristic
duty cycle for the rms-value. Therefore, the on-state loss of the MOSFET in CCM-mode at a junction-
temperature of 125°C is
)125(
2
_CdsononRMSincond RDIP ⋅⋅= (6)
the MOSFET switching loss can be estimated as
SWoffonSW fEEP ⋅+= )( (7)
where, Eon and Eoff are the switch-on and switch-off energy loss which can be found in MOSFET datasheet,
fSW is the switching frequency.
For 300W design, if SPP20N60C3 is used, the conduction loss is
WP
cond 05.542.0782.092.3 2=⋅⋅=
assuming the switching current is about 6A and gate drive resistance Rg=3.6Ω, then the switching loss is
WkHzmWsmWsPSW 43.165*)015.0007.0(
=
+=
the total loss is
WPPP SWcondtotalMOS 48.6
_=+= (8)
the required heatsink for the MOSFET is
WKRR
P
TT
RthCHSMOSthJC
totalMOS
AJ
MOSthHS /89.616.0
48.6
70125
_
_
maxmax
_=−−
−
=−−
−
=(9)
thCHS
Ris the Rth of the insulation pad between MOSFET and heatsink.
Gate drive resistance is used to drive MOSFET as fast as possible but also keep dv/dt within EMI
specification. In this 300W example, 3.6Ωgate resistor is chosen for SPP20N60C3 MOSFET.
Beside gate drive resistance, one 10kΩresistor is also commonly connected between MOSFET gate and
source to discharge gate capacitor.
2.4 Boost Diode
The boost diode D1 has big influence on the system’s performance due to the reverse recovery behaviour.
So the Ultra-fast diode with very low trr and Qrr is necessary to reduce the switching loss. The new diode
technology of silicon carbide (SiC) Schottky shows its outstanding performance with almost no reverse
recovery behaviour. The switching loss due to the boost diode can be ignored with SiC Schottky diode. Only
conduction loss is calculated as below.
WAVDIVP onRMSinFdiode 71.1)782.01(92.32)1(
_
=
−
⋅
⋅=−⋅⋅= (10)
To decide the current rating of a SiC diode, there is a rule of thumb - the SiC diode can handle output power
Pout of 100 W to120 W in a CCM-PFC-system per one rated ampere. For example, the SDT04S60 from
Infineon Technologies is rated at a forward current IF = 4 A, so it is capable for a system of Pout = 4*100 W
= 400 W system in minimum. Therefore, this diode should be suitable for the proposed design.
The required heatsink for boost diode is
WKRR
P
TT
RthCHSdiodethJC
diode
AJ
diodethHS /06.2711.4
71.1
70125
_
maxmax
_=−−
−
=−−
−
=(11)

Application Note 9 2008-08-01
The SiC boost diodes often have a poor surge current handling capability. Therefore a so called bypass
diode is necessary such as the diode D3 as Figure 4. For the proposed system, 1N5408 is suitable.
L1
T1
R1
R2
COUT
RSENSE
Rectifier
D1
D3
Figure 4 inrush current bypass diode
2.5 Boost inductor
The peak current that the inductor must carry is the peak line current at the lowest input voltage plus the high
frequency ripple current. The high frequency ripple current peak to peak, IHF, can be related to maximum
input power and minmum input voltage as equation below.
min_
max_
2
in
in
HF V
P
kI ⋅⋅= (12)
Where, k must be kept reasonably small, and is usually optimized in the range of 15% to 25% for cost
effective design based on the current magnetic component status. If k is too high, the larger AC input filter is
required to filter out this ripple noise. If k is too low, the value of the inductance is too large and leads to big
size of the magnetic core.
For example, we choose k = 22%, then,
A
V
P
I
in
in
HF 2.12%22
min_
max_ =⋅⋅=
The peak current passing through inductor is
A
I
II HF
peakinpkL 14.6
2
2.1
54.5
2
__ =+=+= (13)
The boost choke inductance must be
SWHF
out
boost fI
VDD
L⋅
⋅−⋅
≥)1( (14)
D=0.5 will generate the maximum value for the above equation.
mH
kH
z
A
V
Lboost 25.1
652.1
390)5.01(5.0 =
⋅
⋅−⋅
≥
The magnetic core of the boost choke can be either magnetic powder or ferrite material.
(1) sendust powder toroid core
The required effective magnetic volume of the core, Ve, is

Application Note 10 2008-08-01
3322
max
_
06.1166.11)
8.0
14.6
(25.16257.1125)( cmme
T
A
mHe
B
I
LV pkL
boostre =−=⋅−⋅=≥
µµ
(15)
where, r
µ
is the relative permeability of the material. It should be noted that r
µ
changes with different
DC magnetizing force H, and so does the inductance. As an example, Figure 5 illustrates the relationship
between the Percent Permeability and the DC Magnetizing Force H.
0
µ
in (15) is the magnetic field constant which is equal to 1.257e-6; Bmax is the maximum magnetic flux
density for the selected magnetic material (for sendust, Bmax is up to 0.8T.)
Figure 5 Percent Permeability and DC Magnetizing Force H (from Changsung)
Select a core with similar Ve value from the magnetic core datasheet. For example, the core type
CS468125 from Chang Sung Corporation is selected. The parameters of CS468125 are Ve=15.584cm3,
Ae=1.34cm2, C=11.63cm, r
µ
=125. The turn number of the boost choke winding is
83
0
_=
⋅
=
er
boost
boosttoroid A
CL
N
µµ
(16)
where, C is the magnetic path length and Aeis the effective magnetic cross section area.
To check the actual r
µ
at low line, maximum power, the DC Magnetizing Force H is calculated
)(50
_Oe
C
NI
Hpkin ==

Application Note 11 2008-08-01
Then r
µ
= 125 * 50% = 62.5 according to Figure 5. The actual inductance can be re-calculated as
mH
C
AN
Ler
boost 625.0
0
2
==
µµ
. Hence, the corresponding ripple current will be higher than the
previously assumed value.
The copper loss of the winding wire can be calculated on Iin_RMS.
boostLRMSinboostL RIP _
2
__ ⋅= (17)
Select the proper wire type to fullfil the loss and thermal requirement for the choke.
(2) ferrite core
To make sure the ferrite core will not go into saturation, the turn number of the boost choke winding with
ferrite core is
minmax
_
_AB
LI
NboostpkL
boostferrite ⋅
⋅
≥(18)
where, Bmax is up to 0.3T according to ferrite material specification; Amin is the minimum magnetic cross
section area.
The winding wire copper loss calculation is the same as in the above section of sendust powder toroid
core.
2.6 AC line current filter
As decribed in section 2.5, there is high frequency ripple current peak to peak IHF passing through boost
choke. This ripple will also go into AC line power network. The current filter is necessary to reduce the
amplitude of high frequency current component. The filtering circuit consists of a capacitor and an inductor
as shown in Figure 6.
Current Filter
Rectifier
VIN=85V ...265VAC
Lfilter Cfilter
IHF
IHF_spec
Figure 6 AC line current filter
The required Lfilter is
filterSW
specHF
HF
filter Cf
I
I
L2
_
)2(
1
π
+
≥(19)
normally there is one EMI X2 capacitor which can act as Cfilter. In this example, if we define IHF_spec as 0.2A
peak to peak and asumming X2 capacitance 0.47µF, then
H
FkHz
A
A
Lfilter
µ
µπ
89
47.0)652(
1
2.0
2.1
2=
⋅⋅
+
≥

Application Note 12 2008-08-01
The leakage inductance of EMI common mode choke can be used for current filter. If the leakage inductance
is large enough, no need to add the additional differential mode inductor for filtering. Otherwise, a current
filter choke is necessary. The calculation method for the current filter choke is the same as for boost choke.
2.7 Boost Output Bulk Capacitance
The bulk capacitance has to fullfil two requirements, output double line frequency ripple and holdup time.
(1) output double line frequency ripple limit.
The inherent PFC always presents 2*fLripple. The amplitude of ripple voltage is dependant on output
current and bulk capacitance as below.
pprippleoutL
out
out Vf
I
C
__
*2 ⋅⋅
≥
π
(20)
where, Iout is the PFC output current, Vout_ripple_pp is the output voltage ripple (peak to peak), and fLis the
AC line frequency.
Please note that ICE2PCXX has enhance dynamic block which is active when Vout exceed ±5% of
regulated level. The enchanc dynamic block should be designed to work only during load or line change.
During steady state with constant load, the enhance dynamic block should not be triggered, otherwise
THD will be deteriorated. That means the target Vout_ripple_pp must be lower than 10% of Vout. For this
example, Vout=390VDC, then Vout_ripple_pp must be lower than 39V. if we define Vout_ripple_pp=12V, then
F
Vf
I
C
pprippleoutL
out
out
µ
π
220
2__
=
⋅⋅⋅
≥(21)
(2) holdup time requirement
After the PFC stage, there is commonly a PWM stage to provide isolated DC output for end user. Some
applications, especially computing, have the holdup time requirement. It means that PWM stage should
be able to provide the isolated output even if AC input voltage become zero for a short holdup time. The
common specification for this holdup time is 20ms. If minimum input voltage for PWM stage is defined as
250VDC, then the bulk capacitance will be
F
msW
VV
tP
C
outout
holdupout
out
µ 134
250390
203002
2
222
min_
2=
−
⋅⋅
=
−
⋅⋅
≥(22)
the final Cout capacitance should be higher value calculated from the above two requirements.
2.8 Current Sense Resistor
The current sense resistance is calculated based on the IC soft over current control threshold and peak
current carried by boost choke.
When the Isense signal reaches the soft over control threshold, IC will reduce the internal control voltage and
accordingly the duty cycle is reduced in the following cycles. Finally the boost choke current is limited.
According to IC datasheet, soft over current control threshold is -0.68V maximum. So the current sense
resistor should be
Ω==≤ 11.0
14.6
68.068.0
_A
V
I
V
R
pkL
sense (23)

Application Note 13 2008-08-01
According to Figure 2 and Figure 3, the transistor current as well as the diode current flows through Rsense.
That means, when AC is powered up, a large negative voltage drop at Rsense will be observed when large
inrush current in the range of about 150 A to 200 A flows through the resistor. It is therefore necessary to
limit the current into Pin 2 (ISENSE) to 1 mA, which is realized with resistor R3. A value of R3 = 220Ωis
sufficient for this resistor.
2.9 Output voltage sensing divider
The output voltage is set with the voltage divider represented by R1and R2in Figure 2 and Figure 3. First,
choose the value of the lower resistor R2. Then the value of the upper resistor R1is
21 R
V
VV
R
ref
refout ⋅
−
=(24)
where, Vref is IC internal reference voltage for voltage sensing, 3V typical.
If R2=6kΩ,
Ω=Ω⋅
−
=kkR 77410
3
3390
1
It is recommended to take resistor values with a tolerance of 1% for R1and R2. Due to the voltage stress of
R1, it is recommended to split this value into few resistors in series.
2.10 Frequency setting (only for ICE2PCS01)
The frequency of the ICE2PCS01 is adjustable in the range of 50 kHz up to 250 kHz. The external resistor
RFREQ according to Figure 7 programs a current which controls the oscillator.
Figure 7 Resistor-frequency characteristic

Application Note 14 2008-08-01
2.11 AC Brown-out Shutdown (only for ICE2PCS02)
Brown-out occurs when the input voltage VAC falls below the minimum input voltage of the design (i.e. 85V
for universal input voltage range) and the VCC has not entered into the VCCUVLO level yet. For a system
without input brown out protection (IBOP), the boost converter will increasingly draw a higher current from
the mains at a given output power which may exceed the maximum design values of the input current and
lead to over heat of MOSFET and boost diode. ICE2PCS02 provides a new IBOP feature whereby it senses
directly the input voltage for Input Brown-Out condition via an external resistor/capacitor/diode network as
shown in Figure 8. This network provides a filtered value of VIN which turns the IC on when the voltage at
Pin 4 (VINS) is more than 1.5V. The IC enters into the standby mode and gate is off when VINS goes below
0.7V. The hysteresis prevents the system to oscillate between normal and standby mode.
Figure 8 Block diagram of voltage loop
Because of the high input impedence of comparator of C4 and C5, R5 can be high ohmic resistance to
reduce the loss. From the datasheet, the bias current on VINS Pin is 1µA maximum. In order to have the
design consistence, the current passing through R5 and R6 has to be much higher than this bias current, for
example 6µA. Then R6 is:
Ω== k
uA
V
R117
6
7.0
6(25)
R6 is selected 120KΩ. R5 is selcted by
6
_
55.1
5.12 R
V
VV
RonAC ⋅
−⋅
=(26)
where, VAC_on is the minimum AC input voltage (RMS) to start PFC, for example 70VAC.
Ω=Ω⋅
−⋅
=Mk
V
VV
R8.7120
5.1
5.1702
5
Due to the voltage stress of R5, it is recommended to split this value into few resistors in series.
C4is used to modulate the ripple at the VINS pin. The timing diagram of VINS pin when IC enters brown-out
shutdown is shown in Figure 9.

Application Note 15 2008-08-01
Figure 9 Timing diagram of VINS Pin when IC enters brown-out shutdown
If the bottom level of the ripple voltage touches 0.7V, PFC is in standby mode and gate is off. The ripple
voltage defines PFC brown out off threshold of AC input voltage (RMS), VAC_off. C4can be obtained from the
following equation. Assuming offACAVEINS V
RR
R
V_
65
6
_⋅
+
=, where, VAC_off is the maximum AC input voltage
(RMS) to switch off PFC, for example 65VAC.
VeV
RR
RCR
t
offAC
edisch
7.0)7.02( 46
arg
_
65
6=⋅−⋅
+
⋅−
(27)
assuming tdischarge is equal to half cycle time of line frequency, ie.
L
edisch f
t2
1
arg =, then
nF
V
VV
kM
k
kHzC
V
VV
RR
R
RfC
offAC
L
140
7.0
7.065
1208.7
120
2
ln120502
7.0
7.02
ln2
1
4
1
_
65
6
64
=











−
Ω+Ω
Ω
⋅
Ω⋅⋅=











−
+
⋅
=
−
−
(28)
2.12 IC supply
The IC supply voltage operating range is 11~26V.
There are two stages during IC turned on. First Vcc capacitor is charged from 0V to 7V, the IC internal
regulator block starts to reset voltage at all external pins. The reset process will take about 10us. And then
when Vcc voltage is charged to Vcc_on threshold, IC starts the soft start with gate switching. In the case of
Vcc decoupling capacitance is too low such as 0.1uF, Vcc voltage may be charged up too fast and the time
interval from Vcc=7V to Vcc_on is less than the reset time. Then the IC will not go through a proper soft start
as the voltages at IC pins are not yet properly reset. To avoid such a problem, the delay circuitry is needed.

Application Note 16 2008-08-01
Power on
control
IC Vcc
Cvcc
10k
10k
Cdelay
0.47uF0.1uF
Q1
Q2
AUX supply
input
R1
R2
Figure 10 Vcc supply circuitry
Figure 10 is a typical circuitry to supply PFC controller. Q2 is NPN transistor and controlled by external
“Power on” signal. When “Power on” signal is “high”, Q2 is turned on provides base current for Q1. Q1 is
turned on accordingly to supply auxiliary power to IC Vcc. The reset delay time is adjustable by changing the
RC time constant of R1, R2 and Cdelay. The recommended values are shown in Figure 10 as 10kΩ, 10kΩand
0.47uF respectively.
The same reset process also happens during IC power down when Vcc is discharged from Vcc_off to 7V.
The reset time for power down is around 200us. Because IC is in power down mode with very low current
consumption, typically 300uA only, the required Vcc capacitance for power down reset can be calculated as:
nF
VV
sA
VV
tI
C
resetoffcc
resetdownpower
VCC 2.38
74.10
200650
min__
max__ =
−
⋅
=
−
⋅
≥
µµ
(29)
So the common Vcc decoupling capacitance 0.1uF is enough for reset delay requirement.
2.13 PCB layout guide
In order to avoid crosstalk on the board between power and signal path, and to keep the IC GND pin as
“clean” from noise as possible, the PCB layout for GND must be taken care of properly. Below are some
suggestions for GND connection and Figure 11 below illustrates as a good example.
(1) Star connection rule for main power stage GND: the PCB tracks of MOSFET source, output load
GND, IC auxiliary supply GND and shunt resistor are separated and connected together at bulk
capacitor negative Pin.
(2) Star connection rule for small signal IC GND: the IC external components which need to be
connected to the small signal GND bus highlighted in red color. Such GND bus is connected to IC
GND Pin.
(3) Connection between main power stage GND and small signal IC GND: in Figure 11, a single PCB
track in pink color directly connect IC GND pin to power stage star connection point - bulk capacitor
negative. This is to ensure that the voltage between IC Isense Pin and IC GND Pin does not observe
the switching rectangular noise current. The dark green and blue tracks denote for flowing paths of
high frequency rectangular switching current.
(4) Vcc decoupling capacitor Cvcc: the decoupling capacitor need to be placed close to IC Vcc and
GND Pins as much as possible. The GND track of Cvcc (green color in Figure 11) should be
connected at the point on the single PCB track connecting between IC GND Pin and power GND
point so that the large gate charging current will not pass through the small signal GND bus.
(5) Vsense capacitor Cvsense: to reduce noise in Vsense Pin, small capacitor up to 0.1uF can be added
between Vsense Pin and small signal GND bus.

Application Note 17 2008-08-01
L1
T1
R1
R2
COUT
RSENSE
EMI Filter
R3
GATE GND VSENSE
ISENSE
C2
R4
C3
VCOMP
FREQ
ICOMP
VCC
Auxiliary Supply
ICEXPCS01
Rectifier
VIN=85V ...265V AC
RFREQ
VOUT=400VDC
C1
Cvsense
Cvcc
Figure 11 Good PCB layout illustration
3 Voltage loop and current loop compensation
This section provides a model and a tool for evaluating and improving the control loop characteristics of
ICE2PCS02-based PFC pre-regulators in boost topology. The goal is not only to ensure a narrow bandwidth
in order to achieve a high Power Factor, but also to have enough phase margin so as to make sure the
system is stable over a large range of operating conditions. The design example is demonstrated as well.
Traditional diode rectifiers used in front of the electronic equipment draw pulsed current from the utility line,
which deteriorates the line voltage, produce radiated and conducted electromagnetic interference, leads to
poor utilization of the capacity of the power sources. In compliance with IEC 61000-3-2 harmonic regulation,
active power factor correction (PFC) circuit is getting more and more attention in recent years. For low power
up to 200W, discontinuous conduction mode (DCM) PFC is popular due to its lower cost. Furthermore, there
is only one control loop, i.e. voltage loop, in its transferring control blocks. The design is easy and simple for
DCM operation. However, due to its inherent high current ripple, DCM is seldom to be used for high power
applications. In high power applications, continuous conduction mode (CCM) PFC is more attractive.
V, I
OUT
I
I
L
I
IN
DCM operation CCM operation
Figure 12 DCM and CCM PFC principle

Application Note 18 2008-08-01
3.1 How to achieve PFC function without sinusoidal reference sensing
3.1.1 Boost converter modeling
Figure 13 shows the inductor current waveform for boost converter operating in continuous conduction mode.
diL
iL
TSW
ton toff
I0
Figure 13 inductor current waveform of boost converter operating in CCM mode
assuming Vin is boost converter input DC voltage, Vout is the boost converter output voltage, L is the boost
choke inductance, ton is the on time duration in one switching cycle, toff is the off time duration in one
switching cycle, doff is the off time duty cycle and Tsw is the time duration in one switching cycle.
During “on” interval,
L
V
dt
di in
L=(30)
During “off” interval,
L
VV
dt
di outin
L−
=(31)
And then the boost inductor current variation after one switching cycle is:
SW
offoutin
off
outin
on
in
LT
L
dVV
t
L
VV
t
L
V
di ⋅
⋅−
=⋅
−
+⋅= (32)
The instant boost inductor current after n switching cycle is:
SW
noffnoutnin
nLnL T
L
dVV
ii ⋅
⋅
−
+= −
___
1__ (33)
3.1.2 PFC IC control principle with boost topology
PFC IC control block is inserted in boost converter as shown in Figure 14.

Application Note 19 2008-08-01
Vin Boost converter iL
IC PWM modulation
doff=K*iL
doff
SW
noffnoutnin
nLnL T
L
dVV
ii ⋅
⋅
−
+= −
___
1__
Figure 14 PFC current loop principle
IC senses boost inductor average current, and calculate the off duty cycle to be proportional to inductor
current, and then send such off duty cycle back to boost converter. The negative feedback loop can be seen
from Figure 14. A small disturb increasing on iLwill result in a little bit increasing on off duty cycle. The
increasing off duty cycle will lead to decreasing of iLafter processing by boost converter. In the stead state,
Loutoffoutin iKVdVV ⋅⋅=⋅= (34)
Where, K is the modulation gain defined by IC. It can be seen that boost inductor current shape follows AC
input voltage and it is how PFC function to be achieved.
In the following sections, detail mathematical analysis of current loop and voltage loop will be described and
the transfer function for each block is given in order to design IC external compensation network
components.
3.2 Current Loop Regulation and Transfer Function
The detail block diagram of current loop for ICE2PCS02 is shown in the Figure 15. The boost converter
stage Kboost is elaborated in S-plane.
Boost Converter Power Stage
Kboost(s)
PWM
Comparator
Kc(S)
iL
Current Averaging
Kave(S)
M2
Vicomp
M1
Doff
Vin
Vout
+
-
X1/sL
Figure 15 Block diagram of current loop
3.2.1 Current Averaging Circuit
IC sense the boost inductor current via shunt resistor Rsense as shown in Figure 2. The sensing signal is
sent to Isense Pin. As the voltage in Isense Pin is negative signal together with switching ripple, IC need to
do signal averaging and convert the polarity to positive for following PWM modulation blocks. The output of
averaging block is Vicomp voltage at Icomp Pin. the block diagram of current averaging block is shown in
Figure 16.

Application Note 20 2008-08-01
Figure 16 current averaging block diagram
The transfer function of averaging circuit block can be derived as below.
21
1
1
1
1
)(
OTA
icomp
sense
L
icomp
AVE
gM
CK
s
M
RK
i
V
sK
⋅+
== (35)
where, K1is a ratio between R501 and R7 which is equal to 4, Cicomp is the capacitor at Icomp Pin, gOTA2 is
the trans-conductance of the error amplifier of OTA2 for current averaging, typical 1.0mS as shown in
Datasheet, M1 is the variable controlled by voltage loop.
The function of the averaging circuit is to filter out the switching current ripple. So the corner frequency of the
averaging circuit fAVE must be lower than the switching frequency fSW. Then,
AVE
OTA
icomp fK
Mg
C
π 2
1
12
⋅
≥(36)
3.2.2 PWM comparator block
The averaged Vicomp signal is sent to PWM comparator block and compared with internal triangular ramp
signal to derive duty cycle. The timing diagram of this block is shown in Figure 17.