Infineon AIROC CYW20829B0-P4TAI100 User manual

Datasheet Please read the Important Notice and Warnings at the end of this document 002-39262 Rev. **
www.infineon.com page 1 2024-01-23
CYW20829B0-P4TAI100, CYW20829B0-P4EPI100
AIROC™ Bluetooth® LE module
General description
The CYW20829B0-P4TAI100 is a fully integrated Bluetooth® LE wireless module. The CYW20829B0-P4TAI100
includes an onboard crystal oscillator, passive components, flash memory, and the CYW20829 silicon device.
Refer to the CYW20829 datasheet for additional details on the capabilities of the silicon device used in this
module.
The CYW20829B0-P4TAI100 supports high-performance analog-to-digital conversion audio input, I2S/PCM, CAN,
LIN for automotive use cases and other standard communication and timing peripherals. The
CYW20829B0-P4TAI100 includes a royalty-free Bluetooth® stack compatible with Bluetooth® 5.4 core spec in a
14.5 × 19 × 1.95 mm package.
The CYW20829B0-P4TAI100 includes 1 MB of onboard serial flash memory and is designed for standalone
operation. The CYW20829B0-P4TAI100 uses an integrated power amplifier to achieve Class I or Class II output
power capability.
The CYW20829B0-P4TAI100 is fully qualified by Bluetooth® SIG and is targeted at applications requiring
cost-optimized Bluetooth® wireless connectivity.
The CYW20829B0-P4TAI100 is offered in two certified versions CYW20829B0-P4TAI100, and
CYW20829B0-P4EPI100. The CYW20829B0-P4TAI100 includes an integrated trace antenna. The
CYW20829B0-P4EPI100 supports an external antenna through a RF solder pad output.
Module description
• Module size: 14.5 × 19 × 1.95 mm
• Bluetooth® 5.4 core spec qualified module
- QDID: TBD
-DeclarationID:TBD
• Certified to FCC, ISED, MIC, and CE regulations
• Castelated solder pad connections for ease-of-use
• 1-MB on-module serial flash memory
• Up to 26 GPIOs
• Temperature range: –30°C to +85°C
• 96-MHz Arm® Cortex®-M33 CPU with single-cycle multiply and memory protection unit (MPU)
• Maximum TX output power
- Programmable TX power: up to 10 dBm
• Bluetooth® LE connection range of up to 500 meters at 10 dBm[1]
• RX sensitivity:
- LE-1 Mbps: –98 dBm
- LE-2 Mbps: –95 dBm
- Coded PHY 500 kbps (LE-LR): –101 dBm
- Coded PHY 125 kbps (LE-LR): –106 dBm
Note
1. Connection range tested module-to-module using Bluetooth® Low Energy Long Range Coded PHY technology
in full line-of-sight environment, free of obstacles or interference sources with output power of +10.0 dBm.
Actual range will vary based on end product design, environment, receive sensitivity, and transmit output
power of the central device.

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AIROC™ Bluetooth® LE module
Power consumption
Power consumption
• Bluetooth® LE current consumption
- RX current: 5.6 mA @ LE 1 Mbps
- TX current: 5.2 mA @ 0 dBm
- Deep Sleep mode current with 64 KB SRAM retention: 4.5 µA
- HIDOFF (Deep Sleep): 0.5 µA
Functional capabilities
• Flexible clocking options
- 8-MHz internal main oscillator (IMO) with ±2% accuracy
- Ultra-low-power 32-kHz internal low-speed oscillator (ILO)
- Two oscillators: High-frequency (24-MHz) for radio PLL and low-frequency (32-kHz watch crystal) for LPO
- 48-MHz low power IHO (internal oscillator)
- Frequency-locked loop (FLL) for multiplying IMO frequency
- Integer and fractional peripheral clock dividers
• Quad SPI (QSPI)/serial memory interface (SMIF)
- eXecute-In-Place (XIP) from external quad SPI flash
- On-the-fly encryption and decryption
- Support for DDR
- Supports single, dual, and quad interfaces with throughput up to 384-Mbps
• Serial Communication
- Three run-time configurable Serial Communication Blocks (SCBs)
• First SCB: Configurable as SPI or I2C
• Second SCB: Configurable as SPI or UART
• Third SCB: Configurable as I2C or UART
•Audiosubsystem
- Two pulse density modulation (PDM) channels and one I2 S channel with time division multiplexed (TDM)
mode
• Timing and pulse-width modulation
- Seven 16-bit and two 32-bit Timer/Counter Pulse-Width Modulator (TCPWM) blocks, for MCU. Multiple PWMs
needed for color LEDs.
- PWM supports center-aligned, edge, and pseudo-random modes
•ADCandMIC
- Sigma-delta switched cap ADC for audio and DC measurements
• Up to 32 programmable GPIOs
- One I/O port (8 I/Os) enables Boolean operations on GPIO pins; available during system Deep Sleep
- Programmable drive modes, strengths, and slew rates
- Two overvoltage-tolerant (OVT) pins
- Up to six, used for SMIF

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AIROC™ Bluetooth® LE module
Benefits
• Security built into platform architecture
- ROM-based root of trust via uninterruptible “Secure Boot”
- Step-wise authentication of execution images
- Secure execution of code in execute-only mode for protected routines
- All debug and test ingress paths can be disabled
- Up to four protection contexts (One available for customer code)
- Secure debug support via authenticated debug token
- Encrypted image support for external SMIF memory
• Cryptography hardware
- Hardware Acceleration for symmetric cryptographic methods and hash functions
- True Random Number Generation (TRNG) function
Benefits
CYW20829B0-P4TAI100 provides all necessary components required to operate Bluetooth® LE communication
standards.
• Proven ready-to-use hardware design
• Cost optimized for applications without space constraints
• Nonvolatile memory for self-sufficient operation and over-the-air updates
• Bluetooth® SIG listed with QDID and declaration ID
• Fully certified module eliminates the time needed for design, development, and certification processes
• ModusToolbox™ provides an easy-to-use integrated design environment (IDE) to configure, develop, and
program a Bluetooth® application

Datasheet 4 002-39262 Rev. **
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AIROC™ Bluetooth® LE module
More information
More information
Infineon provides a wealth of data at www.infineon.com to help you to select the right module for your design,
and to help you to quickly and effectively integrate the module into your design.
References
•Overview:AIROC™ Bluetooth® LE & Bluetooth® portfolio, Module portfolio
•CYW20829 Bluetooth® silicon datasheet
•Developmentkits:
-CYW920829B0M2P4TAI100-EVK, CYW20829B0-P4TAI100 evaluation board
-CYW920829B0M2P4EPI100-EVK, CYW20829B0-P4EPI100 evaluation board
• Test and debug tools:
-CYSmart, Bluetooth® LE test and debug tool (Windows)
-CYSmart Mobile, Bluetooth® LE test and debug tool (Android/iOS Mobile App)
•Knowledgebasearticle
-KBA97095 - EZ-Bluetooth® LE module placement
-KBA213976 - FAQ for Bluetooth® LE and regulatory certifications with EZ-BLE modules
-KBA210802 - Queries on Bluetooth® LE qualification and declaration processes
-KBA218122 - 3D Model Files for EZ-BLE/EZ-BT modules
Development environments
ModusToolbox™ software is a modern, extensible development environment supporting a wide range of Infineon
microcontroller devices. It provides a flexible set of tools and a diverse, high-quality collection of
application-focused software. These include configuration tools, low-level drivers, libraries, and operating
system support, most of which are compatible with Linux®, macOS®, and Windows®-hosted environments.
ModusToolbox™ software does not include proprietary tools or custom build environments. This means you
choose your compiler, your IDE, your RTOS, and your ecosystem without compromising usability or access to our
industry leading CAPSENSE™, AIROC™, Bluetooth®, Wi-Fi, security, and low-power features.
Technical support
•Infineon community: Whether you are a customer, partner, or a developer interested in the latest innovations,
the developer community offers you a place to learn, share, and engage with both Infineon experts and other
embedded engineers around the world.
• Visit our support page and contact a local sales representatives. If you are in the United States, you can talk
to our technical support team by calling our toll-free number: [phone]. Select option 2 at the prompt.

Datasheet 5 002-39262 Rev. **
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AIROC™ Bluetooth® LE module
Table of contents
Table of contents
General description ...........................................................................................................................1
Module description............................................................................................................................1
Power consumption...........................................................................................................................2
Functional capabilities.......................................................................................................................2
Benefits............................................................................................................................................3
More information ..............................................................................................................................4
References........................................................................................................................................4
Development environments ...............................................................................................................4
Technical support..............................................................................................................................4
Table of contents ...............................................................................................................................5
1 Overview .......................................................................................................................................7
1.1 Functional block diagram.......................................................................................................................................7
1.2 Module description.................................................................................................................................................7
1.2.1 Module dimensions and drawing........................................................................................................................7
2 Pad connection interface.................................................................................................................9
3 Recommended host PCB layout......................................................................................................11
4 Module connections ......................................................................................................................12
5 Connections and optional external components..............................................................................16
5.1 Power connections (VBAT).....................................................................................................................................16
5.1.1 Considerations and optional components for Brown Out (BO) conditions....................................................16
5.2 External reset (XRES) ............................................................................................................................................17
5.3 Critical components list........................................................................................................................................19
5.4 Antenna design .....................................................................................................................................................19
6 Functional description ..................................................................................................................20
6.1 CPU and memory subsystem ...............................................................................................................................20
6.1.1 CPU .....................................................................................................................................................................21
6.1.2 Interrupts............................................................................................................................................................21
6.1.3 Datawire .............................................................................................................................................................21
6.1.4 Cryptography accelerator (Cryptolite)..............................................................................................................22
6.1.5 Protection units .................................................................................................................................................22
6.1.6 AES-128...............................................................................................................................................................22
6.1.7 Vector unit (VU) ..................................................................................................................................................22
6.1.8 Controller area network flexible data-rate (CAN FD) .......................................................................................22
6.1.9 Local interconnect network (LIN) .....................................................................................................................23
6.1.10 Real time clock (RTC).......................................................................................................................................23
6.1.11 Memory.............................................................................................................................................................23
6.1.12 Boot code .........................................................................................................................................................23
6.1.13 Memory map ....................................................................................................................................................24
7 System resources..........................................................................................................................25
7.1 Power system........................................................................................................................................................25
7.1.1 Power modes .....................................................................................................................................................25
7.1.2 CYW20829 clock system.....................................................................................................................................26
7.1.3 Internal main oscillator (IMO) ...........................................................................................................................27
7.1.4 Internal low-speed oscillator (ILO) ...................................................................................................................27
7.1.5 External crystal oscillators (ECO)......................................................................................................................28
7.1.6 Watchdog timers (WDT, MCWDT) ......................................................................................................................28
7.1.7 Clock dividers.....................................................................................................................................................28
7.1.8 Trigger routing ...................................................................................................................................................28
7.1.9 Reset ...................................................................................................................................................................29
7.2 Bluetooth® LE radio and subsystem ....................................................................................................................30
7.3 Programmable analog-to-digital converter (ADC)..............................................................................................30

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AIROC™ Bluetooth® LE module
Table of contents
7.3.1 Sigma delta ADC.................................................................................................................................................30
7.4 Programmable digital...........................................................................................................................................30
7.5 Fixed-function digital............................................................................................................................................31
7.5.1 Timer/counter/pulse-width modulator (TCPWM) block..................................................................................31
7.5.2 Serial communication blocks (SCB)..................................................................................................................32
7.5.3 QSPI interface serial memory interface (SMIF).................................................................................................32
7.6 GPIO.......................................................................................................................................................................33
7.7 Special-function peripherals................................................................................................................................34
7.7.1 Audio subsystem................................................................................................................................................34
8 Electrical characteristics ...............................................................................................................35
8.1 Absolute maximum ratings ..................................................................................................................................35
8.2 Operating conditions............................................................................................................................................36
8.2.1 XRES....................................................................................................................................................................38
8.2.2 GPIO....................................................................................................................................................................39
8.3 Analog peripherals................................................................................................................................................41
8.3.1 AUD ADC .............................................................................................................................................................41
8.4 Digital peripherals.................................................................................................................................................43
8.5 Audio subsystem...................................................................................................................................................46
8.6 System resources..................................................................................................................................................51
8.6.1 Power-on reset...................................................................................................................................................51
8.6.2 Voltage monitors................................................................................................................................................52
8.6.3 SWD and trace interface ....................................................................................................................................53
8.6.4 Internal main oscillator .....................................................................................................................................53
8.6.5 Internal low-speed oscillator ............................................................................................................................54
8.6.6 FLL ......................................................................................................................................................................54
8.6.7 Crystal oscillator ................................................................................................................................................55
8.6.8 Clock source switching time..............................................................................................................................55
8.6.9 QSPI ....................................................................................................................................................................56
8.6.10 Smart I/O ..........................................................................................................................................................56
8.6.11 JTAG boundary scan........................................................................................................................................57
8.7 Bluetooth® LE........................................................................................................................................................58
9 Environmental specifications ........................................................................................................66
9.1 Environmental compliance ..................................................................................................................................66
9.2 RF certification......................................................................................................................................................66
9.3 Safety certification................................................................................................................................................66
9.4 Environmental conditions....................................................................................................................................66
9.5 ESD and EMI protection........................................................................................................................................66
10 Regulatory information ...............................................................................................................67
10.1 FCC.......................................................................................................................................................................67
10.2 ISED......................................................................................................................................................................68
10.3 European declaration of conformity..................................................................................................................69
10.4 MIC Japan............................................................................................................................................................70
11 Packaging ..................................................................................................................................71
12 Ordering information ..................................................................................................................73
13 Acronyms ...................................................................................................................................74
14 Document conventions................................................................................................................78
14.1 Units of measure.................................................................................................................................................78
Revision history ..............................................................................................................................79

Datasheet 7 002-39262 Rev. **
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AIROC™ Bluetooth® LE module
Overview
1Overview
1.1 Functional block diagram
Figure 1 illustrates the CYW20829B0-P4TAI100 functional block diagram.
Figure 1 Functional block diagram (GPIOs)
1.2 Module description
The CYW20829B0-P4TAI100 module is a complete module designed to be soldered to the application’s main
board.
1.2.1 Module dimensions and drawing
Infineon reserves the right to select components from various vendors to achieve the Bluetooth® module
functionality. Such selections will still guarantee that all mechanical specifications and module certifications are
maintained. Designs should be held within the physical dimensions shown in the mechanical drawings in
Figure 2. All dimensions are in millimeters (mm).
Table 1 Module design dimensions
Dimension item Specification
Module dimensions Length (X) 14.5 ± 0.15 mm
Width (Y) 19 ± 0.15 mm
Antenna connection location dimensions Length (X) 14.5 mm
Width (Y) 4.62 mm
PCB thickness Height (H) 0.50 ± 0.05 mm
Shield height Height (H) 1.45-mm typical
Maximum component height Height (H) 1.45-mm typical
Total module thickness (bottom of module to highest
component) Height (H) 1.95-mm typical
CYW20829
Silicon Device
Passive Components
(RES, CAP, IND)
1 MB
SERIAL FLASH
24 MHz
XTAL
XRES
Up to 2
SCBs
(I2C, SPI,
UART)
SCB
Deep
Sleep
(I2C, SPI)
CAN-FD
ADC
UP to 9
TCPWMs
Up to 26 GPIOs

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AIROC™ Bluetooth® LE module
Overview
See Figure 2 for the mechanical reference drawing for CYW20829B0-P4TAI100.
Figure 2 Module mechanical drawing
Notes
2. No metal should be located beneath or above the antenna area. Only bare PCB material should be located
beneath the antenna area. For more information on recommended host PCB layout, see “Recommended
host PCB layout” on page 11.
3. The CYW20829B0-P4TAI100, CYW20829B0-P4EPI100 includes castellated pad connections, denoted as the
circular openings at the pad location above.

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AIROC™ Bluetooth® LE module
Pad connection interface
2Padconnectioninterface
As shown in the bottom view of Figure 2, the CYW20829B0-P4TAI100 connects to the host board via solder pads
on the backside of the module. Table 2 and Figure 3 detail the solder pad length, width, and pitch dimensions
of the CYW20829B0-P4TAI100 module.
Figure 3 Solder pad dimensions (seen from bottom)
To maximize RF performance, the host layout should follow these recommendations:
1. Antenna Area Keepout: The host board directly below the antenna area of the module (see Figure 2) must not
contain ground or signal traces. This keepout area requirement applies to all layers of the host board.
2. Module Placement: The ideal placement of the Bluetooth® module is in a corner of the host board with the PCB
trace antenna located at the far corner. This placement minimizes the additional recommended keepout area
stated in item 2. Refer to AN96841 for module placement best practices.
Table 2 Connection description
Part number Name Connections Connection type Pad length
dimension
Pad width
dimension Pad pitch
CYW20829B0-P4TAI100 SP 41 Solder pads 1.02 mm 0.61 mm 0.90 mm
CYW20829B0-P4EPI100 SP 41 Solder pads 1.02 mm 0.61 mm 0.90 mm

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AIROC™ Bluetooth® LE module
Pad connection interface
Figure 4 Recommended host PCB keepout area around the CYW20829B0-P4TAI100 antenna

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AIROC™ Bluetooth® LE module
Recommended host PCB layout
3 Recommended host PCB layout
Figure 5 provides details that can be used for the recommended host PCB layout pattern for the
CYW20829B0-P4TAI100. Dimensions are in millimeters unless otherwise noted. Pad length of 1.27 mm (0.64 mm
from center of the pad on either side) shown in Figure 4 is the minimum recommended host pad length. The host
PCB layout pattern can be completed using either Figure 5. It is not necessary to use all figures to complete the
host PCB layout pattern.
Figure 5 CYW20829B0-P4TAI100 host layout (dimensioned)

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AIROC™ Bluetooth® LE module
Module connections
4 Module connections
Table 3 details the solder pad connection definitions and available functions for the pad connections for the
CYW20829B0-P4TAI100 module. Table 3 lists the solder pads on the CYW20829B0-P4TAI100 module, the silicon
device pin, and denotes what functions are available for each solder pad.
Table 3 Pin assignments
Module pad name Pin
number Silicon pin name Pin
number I/O Power
domain Description
Microphone Microphone
MIC_P 24 MIC_P 54 IVDDA Microphone positive input
MIC_N 25 MIC_N 55 Microphone negative input
MIC_BIAS 23 MIC_BIAS 53 O Microphone bias supply
GND_A 22, 26 Analog ground for
microphone
Power supply
VBAT 15 2.75 V~3.6 V
Ground pins
GND
1, 2, 14,
21, 33,
39, 41
Radio I/O
RFIO 40 I/O External antenna port (only
for CYW20829B0-P4EPI100)

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AIROC™ Bluetooth® LE module
Module connections
Table 4 GPIO pin descriptions
Module
pad name
Pad
number
Silicon
pin name
Silicon
pin
number
Direction
Default POR state Power domain Description
P0.0 6 P0.0 32 I/O Floating VDDO
General input and output
port.
See Table 5 for alternate
functions.
P0.1 7 P0.1 33 I/O Floating VDDO
P0.2 8 P0.2 34 I/O Floating VDDO
P0.3 9 P0.3 35 I/O Floating VDDO
P0.4 10 P0.4 36 I/O Floating VDDO
P0.5 11 P0.5 37 I/O Floating VDDO
P1.0 4 P1.0 38 I/O Floating VDDO
P1.1 5 P1.1 39 I/O Floating VDDO
P1.2 12 P1.2 40 I/O Floating VDDO
P1.3 13 P1.3 41 I/O Floating VDDO
P1.4 18 P1.4 43 I/O Floating VDDO
P1.5 19 P1.5 44 I/O Floating VDDO
P1.6 20 P1.6 45 I/O Floating VDDO
P3.0 27 P3.0 1 I/O Floating VDDO
P3.1 28 P3.1 2 I/O Floating VDDO
P3.2 29 P3.2 3 I/O Floating VDDO
P3.3 30 P3.3 4 I/O Floating VDDO
P3.4 16 P3.4 5 I/O Floating VDDO
P3.5 17 P3.5 6 I/O Floating VDDO
P3.6 31 P3.6 8 I/O Floating VDDO
P3.7 32 P3.7 9 I/O Floating VDDO
P4.0 37 P4.0 13 I/O Floating VDDO
P4.1 38 P4.1 14 I/O Floating VDDO
P5.0/
WCO_OUT 34 P5.0/
WCO_OUT 10 I/O Floating VDDO
P5.1/
WCO_IN 35 P5.1/
WCO_IN 11 I/O Floating VDDO
P5.2 36 P5.2 12 Floating VDDO
XRES 3 XRES 23 I Floating VDDO
Notes
4. The CYW20829B0-P4TAI100 contains a single SPI (SPI1) peripheral supporting both master or slave configu-
rations. SPI2 is used for on-module serial memory interface.
5. In Master mode, any available GPIO can be configured as SPI1_CS.

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AIROC™ Bluetooth® LE module
Module connections
Each port pin has multiple alternate functions. These are defined in Table 5.
Table 5 Multiple alternate functions[6]
Port/Pin Analog ACT #0 ACT #1 ACT #4 ACT #5 ACT #6 ACT #7 ACT #8 ACT #9 ACT #10 ACT #11 ACT #12 ACT #13 ACT #14 ACT #15 DS #2 DS #3 DS #5 DS #6 DS #7
P0.0 tcpwm[0].
line_
compl[0]:3
tcpwm[0].
line_
compl[262]:0
pdm.
pdm_
clk[1]:0
tdm.tdm_
tx_
mck[0]:0
tdm.tdm_
rx_
mck[0]:0
keyscan.
ks_
col[2]
scb[0].
spi_
select1:0
P0.1 tcpwm[0].
line[1]:3 tcpwm[0]. line[256]:1 pdm. pdm_
data[1]:0
tdm.tdm_
tx_sck[0]:0 keyscan. ks_
col[3]
scb[0].
spi_
select2:0
P0.2 tcpwm[0].
line_
compl[1]:3
tcpwm[0].
line_
compl[256]:1
peri.tr_io_
input[4]:0 tdm.tdm_ tx_
fsync[0]:0
keyscan.
ks_
col[11]
scb[0].
i2c_scl:0 scb[0]. spi_
mosi:0
P0.3 tcpwm[0].
line[0]:4 tcpwm[0]. line[257]:1 scb[1].spi_ select3:0 tdm.tdm_ tx_sd[0]:0 keyscan. ks_
col[12]
scb[0].
i2c_sda:0 scb[0]. spi_
miso:0
P0.4 tcpwm[0].
line_
compl[0]:4
tcpwm[0].
line_
compl[257]:1
srss.ext_
clk:0 cpuss. trace_
data[3]:1
scb[1].spi_
select2:0 peri.tr_io_ input[0]:0 tdm.tdm_ rx_sck[0]:0 keyscan. ks_
row[0]
scb[0].
spi_clk:0
P0.5 tcpwm[0].
line[1]:4 tcpwm[0]. line[258]:1 cpuss. trace_
data[2]:1
scb[1].spi_
select1:0 peri.tr_io_ input[1]:0 tdm.tdm_ rx_
fsync[0]:0
smif.
spihb_
select1
keyscan.
ks_
row[1]
scb[0].
spi_
select0:0
P1.0 tcpwm[0].
line_
compl[1]:4
tcpwm[0].
line_
compl[258]:1
cpuss.
trace_
data[1]:1
scb[1].
uart_cts:0 scb[1].spi_ select0:0 peri.tr_ io_
output[0]:0
tdm.tdm_
rx_sd[0]:0 keyscan. ks_
row[2]
cpuss.
swj_
swo_
tdo
P1.1 tcpwm[0].
line[0]:5 tcpwm[0].l ine[259]:1 cpuss. trace_
data[0]:1
scb[1].
uart_rts:0 scb[1].spi_ clk:0 peri.tr_ io_
output[1]:0
keyscan.
ks_
row[3]
cpuss.
swj_
swdoe_
tdi
P1.2 tcpwm[0].
line_
compl[0]:5
tcpwm[0].
line_
compl[259]:1
cpuss.
trace_
clock:1
scb[1].
uart_rx:0 scb[2].i2c_ scl:1 scb[1].spi_ mosi:0 peri.tr_io_ input[2]:0 keyscan. ks_
row[4]
cpuss.
swj_
swdio_
tms
P1.3 tcpwm[0].
line[1]:5 tcpwm[0]. line[260]:1 scb[1]. uart_tx:0 scb[2].i2c_ sda:1 scb[1].spi_ miso:0 peri.tr_io_ input[3]:0 keyscan. ks_
row[5]
cpuss.clk_
swj_
swclk_tclk
P1.4 tcpwm[0].
line_
compl[1]:5
tcpwm[0].
line_
compl[260]:1
lin[0].lin_
en[1]:0 keyscan. ks_
col[4]
P1.5 tcpwm[0].
line[0]:6 tcpwm[0]. line[261]:1 lin[0].lin_ rx[1]:0 keyscan. ks_
col[5]
P1.6 tcpwm[0].
line_
compl[0]:6
tcpwm[0].
line_
compl[261]:1
lin[0].lin_
tx[1]:0 keyscan. ks_
col[6]
srss.cal_
wave
P2.0 smif.
spihb_
select0
P2.1 smif.
spihb_
data3
P2.2 smif.
spihb_
data2
P2.3 smif.
spihb_
data1
Note
6. The notation for a signal is of the form IPName[x].signal_name[u]:y.
IPName = Name of the block (such as tcpwm), x = Unique instance of the IP, Signal_name = Name of the signal, u = Signal number where there are more than one signals for a particular signal name, y = Designates copies of the signal name.
For example, the name tcpwm[0].line_compl[3]:4 indicates that this is instance 0 of a tcpwm block, the signal is line_compl # 3 (complement of the line output) and this is the fourth occurrence (copy) of the signal. Signal copies are provided to allow flexibility in routing
and to maximize utilization of on-chip resources.

Datasheet 15 002-39262 Rev. **
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AIROC™ Bluetooth® LE module
Module connections
P2.4 smif.
spihb_
data0
P2.5 smif.
spihb_
clk
P3.0 adcmic.
gpio_
adc_in[0]
tcpwm[0].
line[0]:0 tcpwm[0]. line[256]:0 cpuss. trace_
data[3]:0
scb[2].
uart_cts:0 scb[1].spi_ select0:1 btss. uart_
cts:0
keyscan.
ks_col[13]
P3.1 adcmic.
gpio_
adc_in[1]
tcpwm[0].
line_
compl[0]:0
tcpwm[0].
line_
ompl[256]:0
cpuss.
trace_
data[2]:0
scb[2].
uart_rts:0 scb[1].spi_ clk:1 lin[0].lin_ en[0]:0 btss. uart_
rts:0
keyscan.
ks_col[14] cpuss.rst_ swj_trstn
P3.2 adcmic.
gpio_
adc_in[2]
tcpwm[0].
line[1]:0 tcpwm[0]. line[257]:0 cpuss. trace_
data[1]:0
scb[2].
uart_rx:0 scb[2].i2c_ scl:0 scb[1].spi_ mosi:1 pdm. pdm_
clk[0]:0
peri.tr_io_
input[6]:0 lin[0].lin_ rx[0]:0 canfd[0]. ttcan_rx[0] adcmic. clk_pdm:0 btss. uart_
rxd:0
keyscan.
ks_col[15]
P3.3 adcmic.
gpio_
adc_in[3]
tcpwm[0].
line_
compl[1]:0
tcpwm[0].
line_
ompl[257]:0
cpuss.
trace_
data[0]:0
scb[2].
uart_tx:0 scb[2].i2c_ sda:0 scb[1].spi_ miso:1 pdm. pdm_
data[0]:0
peri.tr_io_
input[7]:0 lin[0].lin_ tx[0]:0 canfd[0]. ttcan_tx[0] adcmic. pdm_
data:0
btss.
uart_
txd:0
keyscan.
ks_col[16]
P3.4 adcmic.
gpio_
adc_in[4]
tcpwm[0].
line[0]:1 tcpwm[0]. line[258]:0 cpuss. trace_
clock:0
scb[1].spi_
select3:1 keyscan. ks_col[7]
P3.5 adcmic.
gpio_
adc_in[5]
tcpwm[0].
line_
compl[0]:1
tcpwm[0].
line_
ompl[258]:0
scb[1].spi_
select2:1 keyscan. ks_col[8]
P3.6 adcmic.
gpio_
adc_in[6]
tcpwm[0].
line[1]:1 tcpwm[0]. line[259]:0 scb[1].spi_ select1:1 keyscan. ks_col[9]
P3.7 adcmic.
gpio_
adc_in[7]
tcpwm[0].
line_
compl[1]:1
tcpwm[0].
line_
ompl[259]:0
keyscan.
ks_col[10]
P4.0 tcpwm[0].
line_
compl[1]:2
tcpwm[0].
line_
ompl[261]:0
keyscan.
ks_row[6] scb[0]. i2c_scl:1 scb[0]. spi_
mosi:1
P4.1 tcpwm[0].
line[0]:3 tcpwm[0]. line[262]:0 keyscan. ks_row[7] scb[0]. i2c_sda:1 scb[0]. spi_
miso:1
P5.0/
WCO_OUT tcpwm[0]. line[0]:2 tcpwm[0]. line[260]:0 srss.ext_ clk:1 scb[2]. uart_cts:1 scb[1].spi_ select0:2 pdm. pdm_
clk[0]:1
adcmic.
clk_pdm:1 btss. uart_
cts:1
keyscan.
ks_col[17]
P5.1/
WCO_IN tcpwm[0]. line_compl
[0]:2
tcpwm[0].
line_
ompl[260]:0
pdm.
pdm_
data[0]:1
adcmic.
pdm_
data:1
keyscan.
ks_col[0]
P5.2 tcpwm[0].
line[1]:2 tcpwm[0]. line[261]:0 keyscan. ks_col[1]
Table 5 Multiple alternate functions[6] (continued)
Port/Pin Analog ACT #0 ACT #1 ACT #4 ACT #5 ACT #6 ACT #7 ACT #8 ACT #9 ACT #10 ACT #11 ACT #12 ACT #13 ACT #14 ACT #15 DS #2 DS #3 DS #5 DS #6 DS #7
Note
6. The notation for a signal is of the form IPName[x].signal_name[u]:y.
IPName = Name of the block (such as tcpwm), x = Unique instance of the IP, Signal_name = Name of the signal, u = Signal number where there are more than one signals for a particular signal name, y = Designates copies of the signal name.
For example, the name tcpwm[0].line_compl[3]:4 indicates that this is instance 0 of a tcpwm block, the signal is line_compl # 3 (complement of the line output) and this is the fourth occurrence (copy) of the signal. Signal copies are provided to allow flexibility in routing
and to maximize utilization of on-chip resources.

Datasheet 16 002-39262 Rev. **
2024-01-23
AIROC™ Bluetooth® LE module
Connections and optional external
components
5 Connections and optional external components
5.1 Power connections (VBAT)
The CYW20829B0-P4TAI100 contains one power supply connection, VBAT, which accepts a supply input range of
2.75 V to 3.6 V for CYW20829B0-P4TAI100. Table 16 provides this specification. The maximum power supply
ripple for this power connection is 100 mV, as shown in Table 16.
It is not required to place any power supply decoupling or noise reduction circuitry on the host PCB. If desired,
an external ferrite bead between the supply and the module connection can be included, but is not necessary. If
used, the ferrite bead should be positioned as close as possible to the module pin connection and the
recommended ferrite bead value is 330 , 100 MHz.
5.1.1 Considerations and optional components for Brown Out (BO) conditions
Power supply design must be completed to ensure that the CYW20829B0-P4TAI100 module does not encounter
a Brown Out condition, which can lead to unexpected functionality, or module lock up. A Brown Out condition
may be met if power supply provided to the module during power up or reset is in the following range:
VILVDDIN VIH
Refer to Table 17 for the VIL and VIH specifications.
System design should ensure that the condition above is not encountered when power is removed from the
system. In the event that this cannot be guaranteed (that is, battery installation, high-value power capacitors
with slow discharge), it is recommended that an external voltage detection device be used to prevent the Brown
Out voltage range from occurring during power removal. Refer to Figure 6 for the recommended circuit design
when using an external voltage detection IC.
Figure 6 Reference circuit block diagram for external voltage detection IC
In the event that the module does encounter a Brown Out condition, and is operating erratically or is not
responsive, power cycling the module will correct this issue and once reset, the module should operate correctly.
Brown Out conditions can potentially cause issues that cannot be corrected, but in general, a power-on-reset
operation will correct a Brown Out condition.

Datasheet 17 002-39262 Rev. **
2024-01-23
AIROC™ Bluetooth® LE module
Connections and optional external
components
5.2 External reset (XRES)
The CYW20829B0-P4TAI100 has an integrated power-on reset circuit, which completely resets all circuits to a
known power-on state. This action can also be evoked by an external reset signal, forcing it into a power-on reset
state. The XRES signal is an active-low signal, which is an input to the CYW20829B0-P4TAI100 module
(solder pad 3). The CYW20829B0-P4TAI100 module does not require an external pull-up resistor on the XRES input
During power-on operation, the XRES connection to the CYW20829B0-P4TAI100 is required to be held low 50 ms
after the VBAT power supply input to the module is stable. This can be accomplished in the following ways:
• The host device should connect a GPIO to the XRES of the CYW20829B0-P4TAI100 module and pull XRES low
until VBAT is stable. XRES is recommended to be released 50 ms after VBAT is stable.
• If the XRES connection of the CYW20829B0-P4TAI100 module is not used in the application, a 10-µF capacitor
may be connected to the XRES solder pad of the CYW20829B0-P4TAI100 to delaythe XRES release. The capacitor
value for this recommended implementation is approximate, and the exact value may differ depending on the
VBAT power supply ramp time of the system. The capacitor value should result in an XRES release timing of 50 ms
after VBAT stability.
• The XRES release timing may be controlled by an external voltage detection IC. XRES should be released 50 ms
after VBAT is stable.

Datasheet 18 002-39262 Rev. **
2024-01-23
AIROC™ Bluetooth® LE module
Connections and optional external
components
Figure 7 illustrates the CYW20829B0-P4TAI100 schematic.
Figure 7 CYW20829B0-P4TAI100 schematic diagram

Datasheet 19 002-39262 Rev. **
2024-01-23
AIROC™ Bluetooth® LE module
Connections and optional external
components
5.3 Critical components list
Table 6 details the critical components used in the CYW20829B0-P4TAI100 module.
5.4 Antenna design
Table 7 details trace antenna used in the CYW20829B0-P4TAI100 module. For more information, see Table 7.
Table 8 details the qualified dipole antenna used in the CYW20829B0-P4EPI100 module. Any antenna of
equivalent or less gain can be used without additional application and testing for FCC regulations. For more
information, see Table 8.
Table 6 Critical component list
Component Reference designator Description
Silicon U1 56-pin QFN Bluetooth® LE silicon device - CYW20829
Silicon U2 8-pin TDF8N, 1 MB Serial Flash
Crystal Y1 24 MHz, 8 pF
Table 7 Trace antenna specifications
Item Description
Frequency range 2400 MHz–2500 MHz
Peak gain –0.5-dBi typical
Return loss 10-dB minimum
Table 8 Dipole antenna specifications
Item Description
Manufacture Pulse
Part number W1010
Frequency range 2400 MHz–2500 MHz
Peak gain 2.0-dBi typical

Datasheet 20 002-39262 Rev. **
2024-01-23
AIROC™ Bluetooth® LE module
Functional description
6 Functional description
The following sections provide an overview of the features, capabilities and operation of each functional block
identified in the block diagram in Figure 1. For more detailed information, refer to the following documentation:
• Board Support Package (BSP) documentation
BSPs are available on GitHub. They are aligned with Infineon kits and provide files for basic device
functionality such as hardware configuration files, startup code, and linker files. The BSP also includes other
libraries that are required to support a kit. Each BSP has its own documentation, but typically includes an API
reference such as the example here. This search link finds all currently available BSPs on the Infineon GitHub
site.
• Hardware Abstraction Layer (HAL) API reference manual
The Infineon HAL provides a high-level interface to configure and use hardware blocks on Infineon MCUs. It is
a generic interface that can be used across multiple product families. You can leverage the HAL’s simpler and
more generic interface for most of an application, even if one portion requires finer-grained control. The HAL
API Reference provides complete details. Example applications that use the HAL download it automatically
from the GitHub repository.
6.1 CPU and memory subsystem
AIROC™ CYW20829 has multiple bus masters, as Figure 1 shows. They are: CPU, datawire, QSPI, and a Crypto
block. Generally, all memory and peripherals can be accessed and shared by all bus masters through multi-layer
Arm® AMBA high-performance bus (AHB) arbitration. An interprocessor communication block (IPC) provides
communication between the CPU and the Bluetooth® LE sub-system.