Infineon iMOTION IRDM983-025MB User manual

Reference Manual Please read the Important Notice and Warnings at the end of this document Revision 2.0
www.infineon.com/iMOTION 2015-03-22
IRDM983-025 / -035MB
Reference Manual
iMOTION™ Motion Controller Module for PM AC Fan
Quality Requirement Category: Industry
Features
Complete 250V - 500V 3-phase inverter system in one chip
Permanent Magnet Sinusoidal Motors Control by Hall sensors
Only two low cost Hall elements required
High efficiency control by quadratic phase advance curve
Internal clock based on external RC
15V single power supply
3.3V Integrated Voltage Regulator
Integrated protection features:
Dynamic overcurrent , Overtemperature ,
Overspeed, Rotor lock, Undervoltage lockout
Full Three Phase Gate Driver
Integrated Bootstrap Diodes
No heatsink required
12x12 mm² PQFN package
Applications
PM fan motor control
Description
IRDM983-025MB, IRDM983-035MB are the complete PM motor controller including six power MOSFET, high voltage
integrated circuit, high precision analog circuit and integrated digital control algorithm. The controller implements
a Hall sensor based control algorithm for 3-phase sinusoidal permanent magnet motor fan applications.
Other than the IRDM982 the IRDM983 only requires two hall sensors.
The integrated digital controller does not require any programming.
Instead there are 16 load curves stored in the internal ROM that can be selected via two resistor pairs.
The IRDM983 is packaged in the 12 x 12 PQFN package and designed to dissipate the power loss through a PCB
without the use of an external heatsink.
There are two products available depending on the power rating of the internal high voltage MOSFETs:
1) IRDM983-025MB –employs six MOSFETs 500V 2A and 600V high voltage IC
2) IRDM983-035MB –employs six MOSFETs 500V 3A and 600V high voltage IC

IRDM983-025/035MB Reference Manual
Complete Motion Controller Module for PM AC fan
Features
Complete 500V 3-phase inverter system in one
chip
No heat-sink required
Permanent Magnet Sinusoidal Motors Control by
two Hall sensors
Internal clock based on external RC
High efficiency control by quadratic phase
advance curve
15V single power supply
3.3V Integrated Voltage Regulator
Selectable 4 or 12 pulse output per revolution
Low standby power
Dynamic overcurrent limit per temperature
Over-temperature control
Over-speed protection
Rotor lock detection/protection
Full Three Phase Gate Driver
Integrated Bootstrap Diodes
Under-voltage lockout
Typical Applications
Fan motor control
Product Summary
Topology
3 Phase AC
VOFFSET
≤ 500 V
Control
Current phase & CEMF shift
control
Feedback
DC bus shunt, 2 Hall sensor
Temperature
sensor
Integrated
Package
12
mm x 12mm PQFN
Typical Connection Diagram
IRDM983-025MB
IRDM983-035MB
High Voltage
Smart IC
VCC
HALL1+
HALL1-
HALL2+
HALL2-
VSP
VBU
VBV
VBW
VBUS
VSS
U
V
W
PG
COM
EFF
XTAL
CLKIN
VDD
DCBUS+
DCBUS-
PG
VSP
Hall Sensor
15V
PGSEL
DIR
DIR

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Revision History
1) IRDM983 DATASHEET REVISION 1 (MAY 5, 2015)
2) INITIAL RELEASE –AUGUST 8, 2015
3) IRDM983 REFERENCE MANUAL REVISION 2 (MARCH 22, 2015)

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Table of Contents
1.0 INTRODUCTION.................................................................................................................4
2.0 LEAD DEFINITIONS ...........................................................................................................7
3.0 PERIPHERALS AND INPUTS/OUTPUTS ..........................................................................9
4.0 POWER UP SEQUENCE AND FAULTS..........................................................................47
APPENDIX A REGISTER FILE...............................................................................................52
APPENDIX B. TEST MODE AND UART COMMUNICATION PROTOCOL...........................57
APPENDIX C . PACKAGE OUTLINE......................................................................................64
APPENDIX D . PACKAGE MARKING.....................................................................................65
APPENDIX E. SOLDERING TEMPERATURE PROFILE.......................................................67

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1.0 Introduction
IRDM983-025MB, IRDM983-035MB are the complete PM motor controller including six power
MOSFET, high voltage integrated circuit, high precision analog circuit and digital control
algorithm. There are two products depending on power rating of internal high voltage MOSFET
listed below:
1) IRDM983-025MB –employs six MOSFET 500V/Rdson=4ohms and 600V high voltage IC
2) IRDM983-035MB –employs six MOSFET 500V/Rdson=2ohms and 600V high voltage IC
All two products are packaged in the 12 x 12 PQFN package and designed to dissipate the power
loss through a mating PCB without an external heatsink. All two products contain exactly same
control algorithm and analog functions. The controller implements a two Hall sensor based control
algorithm for 3-phase sinusoidal permanent magnet motor fan applications. The control also
employs high efficiency PM motor control algorithm based on a quadratic load curve stored in
internal ROM. 16 possible curves are selectable.
The IRDM983-025MB, IRDM983-035MB have an on-chip voltage regulator to derive the 3.3V,
required by the digital logic, from the 15V (VCC15) supply. The 3.3VDC regulated voltage pin is
available externally for connection to Hall-effect sensors. The IC provides low power standby
(less than 7mW) mode of operation that 3.3V power is cut off when VSP (Voltage Set Point)
becomes less than 1.15V to provide further power efficient operation.
An integrated A/D Converter is used to acquire EFF Parameters, temperature (internal
temperature sensing), and the VSP input that sets the motor duty command. An internal
temperature sensor is interfaced to the ADC and resulting digital conversion data is used to
control the dynamic over-current set-points as well as max over-temperature limit.
The IRDM983-025MB, IRDM983-035MB protections include a supply under-voltage lockout (3.3V
and 15VDC), over-speed protection, over-temperature limit and Over-current limitation
protections. The reset circuitry includes a Power-On reset block and a reset input.
All devices do not require any programming. Default coefficients and system parameters are
stored in internal ROM. The EFF input pin, used to adapt to specific motor and load to improve
efficiency, can be used by means of two resistor pairs to choose one of 16 pre-stored load curves
in ROM. DIR is a digital input pins which specify the motor direction command (CW or CCW).
The PGSEL and DIR are digital input pins which specify speed feedback type (1 or 3 pulses per
electrical revolution) and the motor direction command.
The IRDM983-025MB, IRDM983-035MB has an on-chip PLL to generate internal clocks. The PLL
requires an external low frequency reference clock (32768 Hz). The clock can be provided
through an RC or a low-cost crystal (typically used in wrist-watches).
The IRDM983-025MB, IRDM983-035MB integrates high and low side gate drivers for applications
up to 500V, it includes integrated Bootstrap diodes, and six power MOSFETs. The simplified
block diagram is shown in Figure 1.1 in terms of hardware elements while the control elements
are depicted in Figure 1.2 in the following pages.

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Simplified Block Diagram
ADC
VSP
REGISTER
FILE
Dynamic
Overcurrent
Limit
XTAL/RC
Drive
UNDERVOLTAGE
&
STANDBY
OVERCURRENT
CLOCK
PRESCALER
System Clock
(20MHz)
15VDC
3.3VDC (Digital)
3.3VDC (Analog)
U DRIVER (L)
V DRIVER (L)
W DRIVER (L)
PRE
DRIVERS
U DRIVER (H)
U DRIVER (H)
U DRIVER (H)
POWER-ON
RESET
VCC
VDD
XTAL
CLKIN
VSS
COM
LDU
LDV
LDW
HDU
VBU
VSU
HDV
VBV
VSV
HDW
VBW
VSW
HIGH VOLTAGE
PG
VSP
DIGITAL (3.3V)
ANALOG (3.3V/15V)
HIGH VOLTAGE
Clock
Synthesis DCO
AADVEFF
DIR
PLLBYPASS
HALL1+
HALL1-
HALL2+
HALL2-
Internal
Temp
sensing
TEMP
VOLTAGE
REGULATOR
VBUS
High Voltage
IC
PSEL
ALGORITHM
&
CONTROL
BLOCK U
V
W
Figure 1.1 Simplified Block Diagram

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Control Block Diagram
Overcurrent
Comparator
Frequency Measure
&
Glitch filter
2 Hall
Sensor
PG pulse Gen
20kHz PWM Carrier
Frequency
Generation
Modulator
PGSEL selects
1 or 3 pulses per
electrical revolution
PG
VSP
9bit
DIR
Angle
advance
Frequency
Modulator
Angle Reset
PWM
Carrier
6 PWM
Signals
VMOD
Hall sensor frequency
Efficiency setting
EFFpin
Lead Angle
between
Hall sensor
and applied voltage
Block commutation to
Sinusoidal switch
over
Sinusoidal Enable High side
Off
Low On COM
Pin
1usec
Filter
Temp
sensor
Thermal/
Dynamic
OC control
45rpm
250mV OC
45rpm
Internal Parameter
External Parameter
140C/105C
PWM off
1.25V/1.4V
Standby
Mode
(<10mW)
>3000rpm
Overspeed
PWM off
Deadtime
Angle
Speed
Speed
Angle
60
degree
45
rpm 500
rpm
100%
0%
2.1V 5.4V VSP
VMOD
1250
rpm
Filter
Current
Limit
Figure 1.2 Control Block Diagram

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2.0 Lead Definitions
Symbol
Pin #
Description
VSP
10
Voltage Set Point analog input. Provides the value of the PWM modulation index to the controller.
PG
14
Provides speed feedback to through pulsed per revolution. It is an open drain output 15V tolerant.
DIR
15
Motor Direction Input (internally pulled up high = UVW)
EFF
9
VoltageCurveGain Parameter Input
XTAL
40
Clock buffer output
CLKIN
1
Clock buffer input
VSS
11
Logic ground
COM
16,17
Analog input ITRIP and power ground and low side MOSFET source
VCC
13
15V Supply Voltage
PGSEL
12
Pulses per revolution select (Internally pulled up high = 12 pulses per revolution on a 8 poles motor)
HALL1+
4
Hall sensor U positive input
HALL1-
3
Hall sensor U negative input
HALL2+
6
Hall sensor V positive input
HALL2-
5
Hall sensor V negative input
TST1
8
Pin for factory testing –connect to VDD in normal application
TST2
7
Pin for factory testing –connect to VSS in normal application
VDD
2
3.3V output
U
18,19
U phase output
V
20,21
V phase output
W
22,23,24,
25,26
W phase output
VBU
37
Phase U High side Bootstrap capacitor positive
VBV
38
Phase V High side Bootstrap capacitor positive
VBW
39
Phase W High side Bootstrap capacitor positive
VSU
36
Phase U High side Bootstrap capacitor negative
VSV
35
Phase V High side Bootstrap capacitor negative
VSW
34
Phase W High side Bootstrap capacitor negative
DCP
27,28,29,
30,31,32,
33
DC Bus voltage

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Lead Assignments
Back Side View
1011
12131415
16
17
18
19
20
21
22
23
24 25 26 27 28 29 30 31 32
33
34
35
36
37
38
39
40
9 8 7 6 5 4 3 2 1
XTAL
CLKIN
VDD
TST1
TST2
HALL2-
HALL2+
HALL1-
HALL1+
EFF
VSP VSS
PGSEL
PG
DIR
VCC
COM
VBW
VBV
VBU
VSU
VSV
VSW
DCP
DCP
W
V
U
W

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3.0 Peripherals and Inputs/Outputs
The IRDM983-025MB, IRDM983-035MB have several on-chip peripherals including: A/D
Converter (for conversion of the analog inputs: VSP, internal temperature and EFF. This section
provides the description of the main features and each pin functions.
3.1 VSP Analog Input pin
The VSP input has a triple purpose. One is the analog input representing the amount of duty of
PWM output signal which is a part of the Host Processor Interface that includes the signals VSP
and PG and DIR. The 2nd mode is a standby mode to reduce power consumption where VSP is
less than 1.15V/1.40V (hysteresis). The 3rd mode is a Trap test mode recognition which transfers
the system operation to six step modulation mode only for a final motor assembly testing
purpose. There are two parallel input paths to the ADC. The VSP input structure is also shown in
Figure 3.1.
In the normal operating mode, the VSP input ranges from 0 to 5.0V and converted into 0-511
value range. The converted value (0-511) represents a point in the duty curve. At VSP=1.9V
which corresponds 0% duty and internal ADC value=199.
Hysteresis: delta 250mV
Hardware
comparator
VSP
VSS VSPST BY LO W = 1.15V
VSPSTBYHIGH =1.4V
10V
To ADC, Application
Test Mode input
To ADC, Duty input
Hardware
comparator
Total
impedance
150K+/-40%
Impedance
ratio
0.33
Impedance
ratio
0.166
Figure 3.1 VSP Input structure
A motor start/stop command is issued based upon the value of the VSP input. The converted
value is compared against a fixed threshold. The threshold is set to 1.9 V. For any values of VSP
below the threshold the PWM modulation will be 0% and all gate drivers are off.
The motor will run with VSP above the threshold 1.9 V and the duty saturates beyond 5.0V.
When VSP <1.15V, then the system goes into a standby mode where all internal circuitry is
basically shut off.
The VSP pin has a typical input impedance of 150K ohm. With an external 1kohm series resistor,
the VSP input may sustain the voltage exceeding a 10.0V with a condition that the input current is
within 10mA. However, the exceeding amount voltage beyond 10.0V is not guaranteed under any
conditions.

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10
100%
(ADC=511)
0%
(ADC=199)
1.9V 5.0V VSP
VMOD
Figure 3.2 VSP Range and Thresholds
VSP standby description
When VSP becomes less than 1.15V, the system goes into the standby mode and all circuit
except a few analog circuits are powered off. Basically it disengages internal and external 3.3V
power supply and wait for the system to become active.
When VSP becomes less than 1.15V, the system waits for 5 seconds before entering the standby
mode. (See Figure 3.4)
Hysteresis: delta 250mV
Hardware
comparator
VSP
VSS
33VCAP
3.3V regulator
15V (VCC)
To digital logic, analog
3.3V circuit
VSPSTBYLOW = 1.15V
VSPSTBYHIGH =1.4V
5 second hold
circuit (acting
only during
shutdown of the
3.3V regulator)
10V
Total
impedance
150K+/-
40%
To ADC
Figure 3.3 VSP standby and simplified analog circuit

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VSP
Mode
Change
Active
Standby
Less than 5sec greater than 5sec
1.4V
1.15V
Figure 3.4 VSP stand by to active mode example
Once the system goes into a standby mode, all digital power and 3.3V analog power are shut off
and only comparator circuit to monitor VSP analog input voltage is activated. In this standby
mode, typical power consumption will be at around 7mW. Once VSP becomes above 1.4V, then
the system becomes active as all digital and 3.3V analog circuits are activated.
VSP Trapezoidal (6 steps) Test Mode
VSP input can change the normal operating mode to the Trap Test Mode. As per Figure 3.1,
there are 2 channels to monitor Vsp input signal. The mapping of the 2 Vsp channels is as follow:
One channel is mapped as [0V 5.0V] to [0 511] and it is used for normal operating
mode voltage set point.
The other channel is mapped as [0V 9,9V] to [0 511] and it is used to detect the
request to enter in specific trapezoidal (trap) test mode.
The used threshold to enter the trap test mode is 8.8V converted to digital number 454.
The algorithm is described in the following steps:
1. To enter or exit the trap test mode, a counter is used to count ADC conversions where
Vsp is greater or lower than the threshold of 8.8V (454).
2. When in normal mode, if 1376 consecutive ADC conversions are greater than 8.8V (454)
then the system enters in trap test mode
3. When in normal mode, if at least 1 conversion is below the 8.8V (454) threshold then the
counter to enter test mode is reset and the system stays in normal mode
4. When in Trap test mode, if 551 consecutive conversions will be lower than 8.8V (454)
then the system exits test mode and reverts back to normal operating mode
5. When in Trap test mode, if at least 1 conversion is above the 8,8V threshold then the
counter to exit test mode is reset and the system stays in trap test mode
Here are some remarks regarding the algorithm to enter the trap test mode:
1. During Trap test mode entering the DcBus should be properly set to 0V. Because the system
is in normal mode and will react to Vsp maximum value.
2. 1376 scans mean 500 ms. In fact each scan of the ADC takes 363.3 us. So to enter trap test
mode, Vsp must be greater than 8.8V for more than 500 ms.
3. 551 scans mean 200 ms. This means that to exit trap test mode Vsp must be lower than 8.8V
more than 200 ms.
4. The reference voltage of the ADC is the most important source for the threshold accuracy
that is roughly +/-10%. Example Threshold at 8,8V (= 454 raw number) is min 8,0V and max
9,68V

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These following numbers have been put to the metal option area (described in the appendix) so
they could be changed by changing one metal layer only:
a. threshold (454)
b. timing thresholds (1376 and 551)
c. possibility to disable completely this function
Figure 3.5 Trap test mode modulation
The modulation in trap test mode is shown in figure 3.5 where DIR = 1. In the figure both forward
direction and reverse rotating direction cases are shown.
The modulation depends on the speed in the forward direction and depends on motor poles
number.
Modulation initially is 80% (effective 78% considering the dead time)
Modulation changes from 80% (effective 78% considering the dead time) to 95%
(effective 93% considering the dead time) when motor speed becomes bigger than 45
rpm in forward direction (according to DIR pin setting)
For 8 poles motor, modulation changes back from 95% to 80% when motor speed
becomes lower than 24 rpm in forward direction (according to DIR pin setting)
In reverse direction, modulation is always 80%
In Figure 3.6 an example of duty depending on the speed is shown for DIR=1.

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Figure 3.6 Duty in trap test mode depends on forward speed
VSP signal path to PWM
The detailed signal path of VSP is shown in Figure below. VSP starts with analog input to ADC
block followed by filtering and averaging process, and final PWM block. The data range and each
function units are described in this Figure.
ADC
Vsp is sampled
Updated every
363,3 us
(1211 x 6)@20MHz Vsp9bit [0 511]
4 samples
accumulator
There is NO
division by 4
Updated every
363,3 us
Vsp11bit [0 2044]
Low Pass Filter
tau = 10 ms
The filter
output is
updated every
50 us
Vsp11bit [0 2044]
Vsp [0V 5,4V]
Vsp conversion into
Voltage amplitude for the
PWM Modulator
The output of this block is
updated every 50 us TargetVMod13bit
[0 6736]
Divide by 4
The output of this
block is updated
every 50 us TargetVMod11bit
[0 1684]
TargetVMod * 3750/4096
every 50 us
Rectangular
modulation
PWM Modulator
With Dead Time
insertion
It is updated
every 50us
TargetVMod11bit
[0 1684] 6 PWM
commands
OverCurrent
clamp module
on PWM
commands
signals
Cycle by
cycle
operation
Every 50 us it
is reset
6 PWM
Outputs
Angle12bit [0 4095]
Rectangular
modulation
Sinusoidal
modulation
Anti
Shoot
Through
Figure 3.7 VSP signal path
Between the ADC and PWM block, there are two filtering blocks as shown in the following Figure.
The 4 times moving average filtering eliminates a potential PWM blanking due to internal stop
action followed by start when internal filtered VSP becomes less than a digital corresponding
value of 199 to analog VSP=1.9V and immediately recover to start condition. Four registers are
updated at each 363.3usec conversion of VSP input which is a part of consecutive six channels
conversion by 20MHz clock (each conversion takes 1211 clock cycles). At each VSP register

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14
update, synchronization to ADC section takes place with two filtering blocks, namely 4 times
averaging and 10msec filter block, by 20 kHz clock domain. The start and stop internal command
is issue at the output of 10msec digital filter based on the certain digital value.
ADC 4 samples sum (9 to 11 bit
conversion)
10msec
Filtering PWM
Start/Stop logic:
If >= 796 START
If < 796 STOP
#2 VSP
#3 VSP
#4 VSP
#1 VSP
Synchronization
20Mhz clock,
363.3usec for
each VSP
update 20kHz PWM
clock domain START enables PWM
STOP disables PWM
Figure 3.8 VSP digital filtering
There is a functional block named “VSP conversion into Voltage amplitude for the PWM
modulator”. This block converts VSP 11 bit value into usable digital form of Voltage command for
PWM modulator at every 50us update rate. The detailed signal flow inside of this functional block
is shown in Figure 3.9. The output signal of this functional block is called TargetVMod and 13bit
data range.
Vsp11bit [0 2044] -
796
Multiply by 691
Divide by 128
0
Vsp11bit >= 796
TargetVMod13bit
[0 6736]
Figure 3.9 VSP conversion to PWM voltage command
PWM modulator
Figure 3.10 shows the PWM modulator which receives the voltage command and angle
command from the previous functional blocks. The modulator is based on the Space vector
modulation scheme with a two phase modulation. This module employs one Cordic rotator
(multiplexed and used twice per cycle) to perform trigonometric function of sinusoid followed by
the TimeCalculator which produces two active vectors time period amplitude aligned with a given
60 degree quadrant, namely HalfTa and HalfTb. These two active vector time periods, HalfTa and
HalfTb, summed to HalfT0 give half of the PWM cycle period (25 microseconds). HalfTa, HalfTb
and HalfT0 are fed to Compare Generator block which generates time instance of the gate signal
event as a result of carrier frequency up/down counter comparison. The deadtime is inserted also
by this functional block. The final element of PWM modulator is Minimum Pulse Width on High
Side Limiter which eliminates the high side pulse width smaller than 400 nanoseconds.

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15
Sector Finder
Calculates the sector
(0,1,2,3,4,5) based on
angle input
Calculates the angle to be
bound to 60 degrees
Calculates the (60-angle)
to be bound to 60
degrees
One multiplexed
Cordic rotator
Calculates
Sin(angle60)
and
Sin(60-angle60)
It takes 18 sys
clocks cycles to
generate the outpust
TimeCalculator
It calculates the time HalfTa,
the time HalfTb and the time
HalfT0
These timings are based on
PWMPeriod sys clock length
At 20 MHz the PWMPeriod is
1000 (that is 50 us)
HalfTa, HalfTb and HalfT0 are
used to generate compare
values and
HalfTa+HalfTb+HalfT0=500
Calculation time is 12 sysclk
cycles
Compare Generator
Based on sector, it generates
the compare value for each
PWM command signal.
Dead time is inserted in this
block and it is simmetric
The modulation is 2 phases
space vector Minimum Pulse Width on high side limiter
This block deletes all small
pulses that would be
commanded by previous block
on high side.
So if cmpux >496 it is clamped
to 500.
Value 496 is (PWMPeriod/2)-4
Sector
Angle [0 4095]
Sector
Angle60 [0 682]
(60-Angle60) [0 682]
sysclk 20 MHz 50 ns
period
TargetVMod11bit [0 1686]
Sin(angle60)
[0 4095]
Sin(60-angle60)
[0 4095]
HalfTb
HalfTa
HalfT0
DeadTime = 20
cmpuh
cmpul
cmpvh
cmpvl
cmpwh
cmpwl
MinimumPulseWidth = 8
CMPuh
CMPvh
CMPwh
Figure 3.10 PWM modulator detailed block diagram

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3.2 Temperature Sensing
The IRDM983-025MB, IRDM983-035MB have an internal temperature sensor. It updates at every
363,3usec and selects appropriate overcurrent threshold value which goes into the hardware
over-current limit comparator (see below Figure).
This logic described below is the over-temperature limit control at a temperature below 100C
degree. The conversion equations from temperature to digital ADC value are:
)15.273(532.0  COUT TADC
15.273)532.0/(  OUTCADCT
V_ADCin
Internal
Diode
Thermister
ADCout = k * Tc + offset
ADCout
Tc: <92C 92-<96C 96-<100C
Max(mV): 570 450 300
Typ(mV): 500 375 250
Min(mV): 430 300 200
Rotor Lock
3bit Ilim select
Temp is updated at every
6*1211 / 20Mhz (363.3us)
Min=250mV
Comparatorvalue
select
High Side
PWM Off
Low side
On
Or
All PWM off
Comparator
500K
COM
2PF
ADC
Tc
5V zener
25K
25K
25K
25K
VCC ESD
Super
clamp
Figure 3.11 Internal Temperature Sensing Structure and Current Limit
Tc
<92C
between 92-96
between 96-100
Min (mV)
570
450
300
Typ (mV)
500
375
250
Max (mV)
430
300
200
Figure 3.12 Internal Temperature Sensing Structure and Current Limit IRDM983

IRDM983-025/035MB
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17
Over-temperature processing
Over-temperature fault turns off PWM completely so long as the sensed temperature exceeds
100C Celsius degrees. When over-temperature is engaged, there is a hysteresis to disengage
over-temperature at 80C degree. Temperature acquisition to ADC is updated every 363,3 usec at
20MHz as a part of six channel ADC conversion. Once converted to ADC value, it is checked
against a window limiter and if exceeds its limit which are 160C and -40C boundary, the
converted value is discarded and do not pass to the next registers. Once passed the limit-
rejecter, the value is transferred to four FIFO registers and passed on to the preceding digital
control algorithm section by synchronization logic. In the algorithm section, four TEMP values are
averaged followed by a 10msec digital filter by 20kHz clock operation. Then it is passed to eight
consecutive PWM periods to further qualify the over-temperature condition. All this process is
described in the following Figure.
4 times
average 10msec Filtering
Synchronization
20kHz PWM
clock domain
Overtemp logic
8 times PWM
period persist
ADC #2 TEMP
#3 TEMP
#4 TEMP
#1 TEMP
20Mhz clock,
363.3 usec for
each TEMP
update
160C
-40C
Limit-Rejector
Figure 3.13 Overtemperature processing

IRDM983-025/035MB
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18
3.3 Hall sensor interface pins, Commutation and PWM
The IRDM983-025MB, IRDM983-035MB has direct interface pins for two Hall sensors. The Hall
sensors are non-buffered type and have a differential output. The IRDM983-025MB, IRDM983-
035MB are designed to work with particularly HW-101A by Asahi Kasei Microdevices. Each
differential Hall signals are buffered by high gain operational amplifier with a preceding 1.5usec
analog filter shown in Figure below. The third Hall sensor signal Hall 3 (or Hall W) is virtually
generated.
HALL1,2+
900kohm
900kohm
1.8pF
HALL1,2-
High Gain
OP amp
Hysteresis
comparator
Hyst: 75 mV typ
Gain: 80dB typ
Figure 3.14 Hall sensor input circuit
Two Hall sensor input signals go through multiple stage of digital filtering shown in Figure 3.15.
The first stage of digital filter is based on the 20MHz counter to continuously count up to 60
counts to qualify the signal. The U’, V’, and W’ are the filtered signals in Figure below. Then this
signal is fed to the qualification filter (Figure 3.16) which further qualifies the Hall input signal by
eliminating noise and multiple bouncing signals at a transition. The signal U”, V”, W” are the
qualified signal in Figure and used for sinusoidal two phase SVPWM and speed information
generation.
3.0usec
Digital Filter
6bit up/downCounter (60
count) based filter
Th+ = 60
Th- = 1
Fsample = 20Mh
Third Hall sensor
Virtual signal generation
150usec Digital Filter
3 consecutivestate
qualifying filter
1111
0000
Otherwise hold
Fsample = 50usec
Qualification Filter
Hall U
1.5usec Analog
Filter
Hall V
H1+
H1-
H2+
H2-
Hall U’
Hall V’
Hall W’
Hall U’’
Hall V’’
Hall W’’
Hall U’’’
Hall V’’’
Hall W’’’
 Sinusoidal SVPWM
Waveform generation
 Speedgeneration
 PG pulse generation
 180degree Block Commutation
 Rotation Detection (RDMS)
 Zero Speed state
generation
 Illegal state detect
DIR
Command
1.5usec Analog
Filter
L H L L
L H H
H
L H L L
L H H
H
Rising
edge
Falling
edge
Hall U’ Hall U’’Hall V’
DIR=H DIR=L
Hall U’’Hall V’
L H L L
L H H
H
L H L L
L H H
H
Rising
edge
Falling
edge
Ha ll V’ H all V’’Hall W ’
DIR=H DIR=L
Ha ll V’’Ha ll W’
L H L L
L H H
H
L H L L
L H H
H
Rising
edge
Falling
edge
Ha ll W’ Hall W’’Hall U ’
DIR=H DIR=L
Hall W’’Hall U ’
Figure 3.15 Hall sensor input filtering

IRDM983-025/035MB
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19
HALL U’
HALL V’
HALL W’
HALL U”
Figure 3.16 Hall sensor input qualification filter
3.4 Block commutation within +/-45rpm
At starting a motor, up to 45rpm toward the same direction of DIR pin state, the IRDM983-025MB,
IRDM983-035MB operates by a block commutation mode based on the Hall signal U’, V’, and W’.
When motor rotates reverse and opposite direction of DIR pin state, then regardless of the motor
speed, the PWM operation is based on a block commutation. Figure 3.17 shows the speed range
where a block commutation applies as indicated arrow lines depending on a DIR state. These
signals are filtered by 150usec digital filter with 50usec sampling as shown in Figure. These
signals are also used for identifying an illegal state such as (000) or (111) Hall state and rotation
detection. The block commutation signal waveform are shown in Figure 5.3.3 and Figure 5.3.4
and based on half cycle PWM while positive voltage (180degree) applied to a motor with 30
degree phase leading to the CEMF phase to neutral signal.
The PWM duty of block commutation is always 80% of commanded VSP.
Speed
45rpm
<0>
45rpm
DIR=H, Motor=UVW
Motor=UWV
DIR=L,
Motor=UWVMotor=UVW
Figure 3.17 Block commutation speed range