Infineon 82C900 Installation and operating instructions

A
pp
lication Note, V 1.0, Feb. 2004
82C900
Standalone TwinCAN Controller
Microcontrollers
AP29002
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Edition 2004-02-01
Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 2006.
All Rights Reserved.
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AP29002
Standalone TwinCAN Controller
Table of Contents
Application Note 3 V 1.0, 2004-02
Table of Contents Page
1 Product Overview.......................................................................................... 2
2 CAN protocol overview.................................................................................. 2
3 Using special features of the 82C900 ........................................................... 2
3.1 Using the 82C900 with SSC interface ........................................................... 2
3.2 Using the parallel interface of the 82C900 .................................................... 2
3.3 Hardware Gateway functionality.................................................................... 2
3.4 Normal Gateway Mode.................................................................................. 2
3.5 Shared Gateway ........................................................................................... 2
3.6 Stand Alone mode......................................................................................... 2
3.7 SPI Master Mode .......................................................................................... 2
3.8 Configuration via CAN-Bus ........................................................................... 2
3.9 Using the parallel port as general purpose I/O.............................................. 2
3.10 The FIFO-capability of the 82C900 ............................................................... 2
3.11 Using the FIFO-buffering in a gateway application........................................ 2
3.12 Power Saving Modes .................................................................................... 2

AP29002
Standalone TwinCAN Controller
Product Overview
Application Note 4 V 1.0, 2004-02
1Product Overview
The TwinCAN module in the 82C900 permits the connection and autonomous handling
of two independent CAN buses. It supports the maximum CAN baud rate of 1M baud
and complies with CAN protocol version 2.0B (active).
The full-CAN module has 32 message objects, which can be independently assigned
to one of the two buses. The scalable FIFO mechanism for reception and transmission
greatly improves the real-time behavior of the system. The device provides built-in
automatic gateway functionality for data exchange between both CAN buses,
minimizing the CPU's message handling load. The gateway feature can also be used
for automatic reply to received messages.
The powerful interrupt structure permits application-specific interrupt generation. The
enhanced acceptance filtering dedicates one acceptance mask to each message
object. In addition, a 16-bit frame count/time-stamp is implemented for each message
object. The 82C900's analyzing mode, during which no dominant bits are sent, makes
it ideal for diagnostic applications.
Figure 1 82C900 Architectural Overview

AP29002
Standalone TwinCAN Controller
Product Overview
Application Note 5 V 1.0, 2004-02
The Infineon 82C900 comes with many useful features, such as:
•Handles two independent CAN buses autonomously
•32 message objects can be independently assigned to one of the two buses
•Complies with CAN protocol version 2.0B (active)
•Baud rate up to 1Mbaud
•Scalable FIFO mechanism
•Built-in automatic gateway functionality
•Remote frame monitoring
•One acceptance filtering mask per message object
•16 bit frame count/time-stamp per message object
•Analyzing mode
•Parallel and serial interface
•Can be configured via external serial EEPROM
•Clock output pin
•Power saving features
•28-pin P-DSO package
•Temperature range -40° to +125° C
The Standalone TwinCAN device provides two interface channels for communication
with a host microcontroller: a multiplexed address/data bus and a synchronous serial
channel (SSC). The SSC may also be used to read out the initial TwinCAN register
configuration from a serial EEPROM without requiring a host microcontroller. A Sleep
Mode and a Power-Down Mode can be activated in order to minimize power
consumption. The device's clock can be controlled by CAN messages.

AP29002
Standalone TwinCAN Controller
CAN protocol overview
Application Note 6 V 1.0, 2004-02
2CAN protocol overview
CAN is an asynchronous serial bus system with one logical bus line. A CAN bus
consists of two or more nodes. The number of nodes on the bus may be changed
dynamically without disturbing the communication of other nodes. This allows easy
connection and disconnection of bus nodes (e.g. node for software upgrade, bus
monitoring…).
The bus logic corresponds to a “wired-AND” mechanism, recessive bits are overwritten
by dominants bits. As long as no bus node is sending a dominant bit, the bus line is in
the recessive state, but a dominant bit from any node generates the dominant Bus
State.
The maximum bus speed is 1Mbaud, which can be achieved with a bus length of up to
40m. At least 30 nodes may be connected without additional equipment.
Figure 2 Structure of a Standard data Frame generated by a CAN node

AP29002
Standalone TwinCAN Controller
CAN protocol overview
Application Note 7 V 1.0, 2004-02
In this kind of frame, the identifier field has a length up to 11 bits giving 2048 message
identifiers. But “extended CAN” specifications allow a 29 bits identifier field giving 536
Million messages identifiers. In this application note, only “standard CAN” will be used
but C167CR and CS also support “extended CAN” specifications.
For bus arbitration, Carrier Sense Multiple Access / Collision Detection with Non-
Destructive Arbitration is used. It means that if a node wants to transmit a message, it
checks first that the bus is in the idle state (“Carrier Sense”). If this is the case the node
becomes the bus master and sends its message. If many nodes start their
transmission at the same time (“Multiple Access”) collision is avoided by bit wise
arbitration (Collision Detection with Non-Dest’ructive Arbitration).
Each node sends the bits of its message identifier and monitors the bus level. A node
which sends a recessive identifier bit but reads back a dominant one loses bus
arbitration and switches to receive mode.
The CAN protocol allows a high data integrity with several means for error checking
and can detect:
•Cyclic Redundancy Check (CRC) Errors
•Acknowledge Errors
•Form Errors
•Bit Errors
•Stuff Errors

AP29002
Standalone TwinCAN Controller
Using special features of the 82C900
Application Note 8 V 1.0, 2004-02
3Using special features of the 82C900
The following chapter contains descriptions and example applications to all the
important features of the 82C900. The examples are all developed using the 82C900
Starter Kit, Dave 2.1 and the Keil-compiler. The examples that require a host interface
use the C167CR Starter Kit. The clock frequency of the crystal on the 82C900 Starter
Kit is 24 MHz.
3.1 Using the 82C900 with SSC interface
The SSC interface provides an economical way to connect the 82C900 to a
microcontroller. The SSC interface is developed by Infineon and is 100% SPI
compatible. Basically there are only 5 port pins necessary for communication via SSC
(plus one for each interrupt you want to use). The default baud rate of the SSC
interface on the 82C900 is 100 KBaud. But it can work with a speed up to 6.25 MBaud
in slave- and 12.5 MBaud in master mode.
Figure 3 Important connections for the SSC-Data transfer. For RDY and SLS,
any available Port of the microcontroller can be used.
82C900
CTRL3
CTRL2
CTRL1
CTRL0
24MHz
22pF 22pF
MODE0
MODE1
RDY
µC
PX.X
PX.Y
SCLK
MTSR
MRST
100K
100K
RDY
/SLS
SCLK
MTSR
MRST

AP29002
Standalone TwinCAN Controller
Using special features of the 82C900
Application Note 9 V 1.0, 2004-02
An example using the SSC Slave mode of the 82C900 was implemented using the
82C900 evaluation board and an Infineon C167CR as the host microcontroller. The
82C900 evaluation board was connected directly to the Phytec KitCON167 evaluation
board for the C167CR.
Note: Please note that this example can also be implemented on many other Infineon
Microcontrollers, such as the C161PI. If you want to use the Phytec C161O
KitCon board, the board needs to be connected with wires because P3.4 of the
KitCon board is used for other functions. So another port pin has to be used for
the /RDY signal. But if wires are used noise can be a problem, if the wires are to
long or the connectors are not good enough.
The jumper configurations on the 82C900 starterkit are shown in Table 1.
Table 1 Jumper settings for SSC-Slave-Mode
JP10 1-2 connected: SLS on CTRL0
JP32 Open (MODE0 = ‘1’)
JP33 Close (MODE1 = ‘0’)
JP38 All open
JP39 3-7 closed,
1-2 depending which interrupts are used
8 open
JP40 All open

AP29002
Standalone TwinCAN Controller
Using special features of the 82C900
Application Note 10 V 1.0, 2004-02
The following example sets up the SSC interface of an Infineon 16 bit microcontroller.
The code was actually tested on the C167CR and C161PI microcontrollers (on Phytec
KitCon evaluation boards). The Code is generic and should work on most other
Infineon 16-bit controllers.
void SSC_Init(void)
{
SSCEN = 0;
// SSC baudrate generator/reload register
// baudrate = 100 KBaud
SSCBR = 0x0031;
// load P3.13 output latch (SCLK) with the
// desired clock idle level(high)
P3 |= 0x2000;
// set P3.13 direction control (SCLK output)
DP3 |= 0x2000;
// ---------- SSC Control Register ----------
/// Master Mode
/// transfer data width is 8 bit
/// transfer/receive MSB first
/// shift transmit data on the leading clock edge, latch on
/// trailing edge
/// idle clock line is high, leading clock edge is
/// high-to-low transition
/// ignore receive error
/// ignore phase error
SSCCON = 0xC057;
DP3 &= 0xFEFF; // reset P3.8 dir control (MRST input)
P3 |= 0x0200; // set P3.9 output latch (MTSR)
DP3 |= 0x2240; // set P3 dir control
}
As you can see from the source code, there is nothing special about the SSC
initialization.
For transferring data to a register we need to specify its 11-bit address. But since the
SSC interface on the 82C900 is only able to handle 8 bits at a time and one of these is
used for Read/Write indication, the rest of the address has to be specified in a different
way. Therefore, when using the SSC interface, the 82C900’s address space is divided
into pages. Every page is 128 bytes wide.

AP29002
Standalone TwinCAN Controller
Using special features of the 82C900
Application Note 11 V 1.0, 2004-02
So before being able to transfer data to a register, we need to select the page first:
void SSC_SetPage(byte PageNumber)
{
SLS = 0; // set SLS=0, new communication sequence
while(RDY==0){}; // wait for RDY==1 (82C900 is ready)
SSCRIR = 0; // reset receive interrupt request
SSCTB = PAGE_WRITEMASK | PAGE;
// mask for write, load transmit buffer register with
// PAGE register address
while(!SSCRIR){}; // wait for end of transmission
while(RDY==0){}; // wait for RDY==1 (82C900 is ready)
SSCRIR = 0; // reset receive interrupt request
SSCTB = PageNumber;
// load transmit buffer register with pagenumber
while(!SSCRIR){}; // wait for end of transmission
while(RDY==0){}; // wait for RDY==1 (82C900 is ready)
SLS = 1; // set SLS=1, communication sequence end
}
The 82C900 extends the SSC interface by a ready signal (RDY). This is necessary,
because both CAN and SSC interfaces use the same memory area. As long as there
is CAN access to the registers, the SSC will be suspended by using the RDY signal to
avoid collisions.

AP29002
Standalone TwinCAN Controller
Using special features of the 82C900
Application Note 12 V 1.0, 2004-02
The following C function transfers 1 data byte to the address specified as a parameter:
void SSC_SendByte(word StartAddress, byte Data)
{
SSC_SetPage(StartAddress >> 7);
// extract 4 MSBs (= page number) from StartAddress
SLS = 0; // set SLS=0, new communication sequence
while(RDY==0){}; // wait for RDY==1 -> 82C900 is ready
SSCRIR = 0; // reset receive interrupt request
SSCTB = PAGE_WRITEMASK | StartAddress;
// mask for write, load transmit buffer register
// with StartAddress
while(!SSCRIR){}; // wait for end of transmission
while(RDY==0){}; // wait for RDY==1 -> 82C900 is ready
SSCRIR = 0; // reset receive interrupt request
SSCTB = Data; // load transmit buffer register with Data
while(!SSCRIR){}; // wait for end of transmission
while(RDY==0){}; // wait for RDY==1 -> 82C900 is ready
SLS = 1; // set SLS=1, communication sequence end
}
First the four MSB bits are extracted from the address as they specify the page. Then
the page is set in the 82C900’s PAGE register using the SSC_SetPage function
described before. After that, the write indication bit is added to the remaining 7 address
bits and address byte is being transferred via the SSC. Then the data byte is
transferred completing the communication sequence.
This procedure is the same for all Infineon microcontrollers containing a SSC
peripheral.
Reading a byte from the 82C900 works similar to writing:
First the four MSB bits are extracted from the address as they specify the page. Then
the page is set in the 82C900’s PAGE register using the SSC_SetPage function
described before.

AP29002
Standalone TwinCAN Controller
Using special features of the 82C900
Application Note 13 V 1.0, 2004-02
After that the address and a dummy byte are transferred to the 82C900. The C
function shown below the returns the data byte read from the 82C900
byte SSC_ReadByte(word StartAddress)
{
SSC_SetPage(StartAddress >> 7);
// extract 4 MSBs (= page number) from StartAddress
StartAddress &= PAGE_READMASK; // mask for read
SLS = 0; // set SLS=0, new communication sequence
while(RDY==0){}; // wait for RDY==1 -> 82C900 is ready
SSCRIR = 0; // reset receive interrupt request
SSCTB = StartAddress;
// load transmit buffer register with StartAddress
while(!SSCRIR){}; // wait for end of transmission
while(RDY==0){}; // wait for RDY==1 -> 82C900 is ready
SSCRIR = 0; // reset receive interrupt request
SSCTB = StartAddress;
// load transmit buffer register with StartAddress (dummy)
while(!SSCRIR){}; // wait for end of transmission
while(RDY==0){}; // wait for RDY==1 -> 82C900 is ready
SLS = 1; // set SLS=1, communication sequence end
return SSCRB; // return received byte
}

AP29002
Standalone TwinCAN Controller
Using special features of the 82C900
Application Note 14 V 1.0, 2004-02
Application Example
With the SSC data transfer routines shown in chapter 3.1 you are able to create a
CAN application with the 82C900. The application example sets up two CAN message
objects, one for receiving and one for transmitting.
As soon as a CAN message that has the same CAN identifier as this receive object is
received, an interrupt service routine is called. This interrupt service routine copies the
data received from the CAN message to the transmit object and transmits it on the
same CAN node. The source code for this example is in the SSC directory of the code
for this ApNote.
void main(void)
{
Project_Init();
SLS = 1; // slave not selected
// set up CAN node A, 1 Mbaud
SSC_SendByte(ACR, 0x41); // set bit CCE in ACR
SSC_SendByte(ABTR+1, 0x23);
// set DIV8X=0, TSEG2=3, TSEG1=4
SSC_SendByte(ABTR, 0x02); // set SJW=1, BRP=2
SSC_SendByte(AIMR0, 0x01);
// take IMC0 into account for INTID generation
SSC_SendByte(ACR, 0x00); // clear INIT, CCE in ACR
This part of the code initializes the microcontroller and sets up CAN node A in the
82C900 for operation at 1 MBaud. To be able to change the configuration, bit CCE in
ACR must be set and then be reset again after the configuration has been changed.

AP29002
Standalone TwinCAN Controller
Using special features of the 82C900
Application Note 15 V 1.0, 2004-02
As a next step, the CAN message object for receiving must be set up. This is also
done by configuring a number of registers in the 82C900, the ‘CAN Message Object
Registers’:
//set up CAN message object 0 (RX), node A, interrupt node 1
// /OUT1 (associated with interupt node 1) is connected to P2.11 calling
the ISR when message object is received
SSC_SendByte(MSG_OBJ_BASE(0)+MSGCTRn,0x7F);
// set MSGVAL to '01' => reset
SSC_SendByte(MSG_OBJ_BASE(0)+MSGCTRn,0xFD);
// set INTPND to '01' => reset
SSC_SendByte(MSG_OBJ_BASE(0)+MSGCTRn+1,0x7F);
// set RMTPND to '01' => reset
SSC_SendByte(MSG_OBJ_BASE(0)+MSGCTRn+1,0xDF);
// set TRXQ to '01' => reset
SSC_SendByte(MSG_OBJ_BASE(0)+MSGCTRn+1,0xFD);
// set NEWDAT to '01' => reset
SSC_SendByte(MSG_OBJ_BASE(0)+MSGCFGn,0x10);
// select Node A, set DIR=0 (receive), 1 data byte (DLC=1)
SSC_SendByte(MSG_OBJ_BASE(0)+MSGCFGn+2,0x01);
// trigger interrupt node 1 when receiving message
SSC_SendByte(MSG_OBJ_BASE(0)+MSGCTRn+1,0xF7);
// set MSGLST to '01' => reset
SSC_SendByte(MSG_OBJ_BASE(0)+MSGCTRn,0xFB);
// set RXIE, receive interrupt is enabled
SSC_SendByte(MSG_OBJ_BASE(0)+MSGARn+2,0x04);
// identifier of receive object (0) is 0x0001
SSC_SendByte(MSG_OBJ_BASE(0)+MSGCTRn,0xBF);
// set MSGVAL, message object is valid
To be able to configure the message object, it must first be made invalid by resetting
MSGVAL in register MSGCTRn. Then you can configure the message object, set the data
direction, data length and associated interrupt node.
In the 82C900 there are two interrupt pins available, that can be associated with up to
4 interrupt nodes each by configuring the GLOBCTR register. Then you can associate
the single message objects with one interrupt node each. The corresponding interrupt
pin will be triggered, when the associated event occurs.
In this application the receive interrupt is enabled and the identifier of the receive
message object is set to 0x0001. After that the message is set valid.

AP29002
Standalone TwinCAN Controller
Using special features of the 82C900
Application Note 16 V 1.0, 2004-02
Now the transmit message object is set up by setting the corresponding register in the
82C900. It works similar to the receive object, only the data direction and identifier are
different and no interrupt node is needed.
//set up CAN message object 1 (TX), node A
SSC_SendByte(MSG_OBJ_BASE(1)+MSGCTRn,0x7F);
// set MSGVAL to '01' => reset
SSC_SendByte(MSG_OBJ_BASE(1)+MSGCTRn,0xFD);
// set INTPND to '01' => reset
SSC_SendByte(MSG_OBJ_BASE(1)+MSGCTRn+1,0x7F);
// set RMTPND to '01' => reset
SSC_SendByte(MSG_OBJ_BASE(1)+MSGCTRn+1,0xDF);
// set TRXQ to '01' => reset
SSC_SendByte(MSG_OBJ_BASE(1)+MSGCFGn,0x18);
// clear NODE in MSGCFGn, set DIR=1 (transmit),
// 1 data byte (DLC=1)
SSC_SendByte(MSG_OBJ_BASE(1)+MSGARn+2,0x08);
// identifier to 0x0002
SSC_SendByte(MSG_OBJ_BASE(1)+MSGCTRn+1,0xF7);
// set CPUUPD to '01' => reset
SSC_SendByte(MSG_OBJ_BASE(1)+MSGCTRn+1,0xFE);
// set NEWDAT to '10' => set
SSC_SendByte(MSG_OBJ_BASE(1)+MSGCTRn,0xBF);
// set MSGVAL to '10' => set
while (1){};
}

AP29002
Standalone TwinCAN Controller
Using special features of the 82C900
Application Note 17 V 1.0, 2004-02
void INT_viIsrEx3(void) interrupt CC11INT
{
unsigned char databuffer, checkTXRQ;
databuffer = SSC_ReadByte(MSG_OBJ_BASE(0)+MSGDRn0);
// get data from received message
checkTXRQ = SSC_ReadByte(MSG_OBJ_BASE(1)+MSGCTRn+1) | 0x10;
// checkTXRQ holds LSB of TXRQ
if(checkTXRQ)
// TXRQ='01', no transmission requested, ok to send
{
SSC_SendByte(MSG_OBJ_BASE(1)+MSGCTRn+1,0xFB);
// set CPUUPD
SSC_SendByte(MSG_OBJ_BASE(1)+MSGDRn0,databuffer);
// put data into transmit message object
SSC_SendByte(MSG_OBJ_BASE(1)+MSGCTRn+1,0xF7);
// reset CPUUPD
SSC_SendByte(MSG_OBJ_BASE(1)+MSGCTRn+1,0xEF);
// set TRXQ to '10' => set
}
else
}
// TXRQ='10', transmission requested, not ok to send
{
SSC_SendByte(MSG_OBJ_BASE(1)+MSGCTRn,0x7F);
// set MSGVAL to '01' => reset
SSC_SendByte(MSG_OBJ_BASE(1)+MSGDRn0,databuffer);
// put data into transmit message object
SSC_SendByte(MSG_OBJ_BASE(1)+MSGCTRn+1,0xF7);
// reset CPUUPD
SSC_SendByte(MSG_OBJ_BASE(1)+MSGCTRn,0xBF);
// set MSGVAL to '10' => set
SSC_SendByte(MSG_OBJ_BASE(1)+MSGCTRn+1,0xEF);
// set TRXQ to '10' => set
}
}

AP29002
Standalone TwinCAN Controller
Using special features of the 82C900
Application Note 18 V 1.0, 2004-02
µC
8-B it D ata/Address-B us
/C S x
/R D Y
/R D
/W R
P0L P0-P7
RD Y
CTRL3
CTRL2
ALE CTRL1
CTRL0
82C900
24M H z
22pF 22pF
MODE0
MODE1
3.2 Using the parallel interface of the 82C900
The 82C900 can also be configured via parallel interface. The host CPU must support
an 8-Bit Infineon or Motorola compatible multiplexed bus and 4 control signals: /ALE,
/CS, /WR and /RD for an Infineon compatible parallel bus.
Figure 4 Schematic for the parallel data transfer
In this example, the C167CR is used as the host microcontroller, with the KitCon167
evaluation board. This board can be connected directly to the 82C900 Starter Kit via
the KitCon-connector. CS3 from the C167CR is used as the chip select signal to the
82C900. Therefore the ADDRSEL3 and BUSCON3 registers of the C167CR are
configured with the appropriate bus settings.
Note: Connecting the 82C900 directly to the kitCON161PI evaluation board from
Phytec will not work due to an address decoder on this board which modifies the
bus signals.

AP29002
Standalone TwinCAN Controller
Using special features of the 82C900
Application Note 19 V 1.0, 2004-02
Table 2 shows the jumper settings for the 82C900 evaluation board in this example.
Table 2 Jumper Settings for Parallel-Mode
JP10 1-2 connected: /CS on CTRL0
JP32 Close (MODE0 = ‘0’)
JP33 Close (MODE1 = ‘0’)
JP38 All close
JP39 1-2 depending which interrupts are used
3-8 open
JP40 3-6 close(with using /CS3)
others open
JP42 2-3 closed
The 82C900 is configured for a long read access by setting bit LAE in the GLOBCTR-
Register to ‘1’ (default ‘0’).
Configurations for the /CS3 signal on the C167CR
For this example a 4K memory window with start address 0x200000 is used. In this
address range the address/data-bus is an 8-Bit multiplexed bus. To select the 82C900
/CS3 is used. To fulfill the timing for long read access the following important
configurations must be made for BUSCON3 (fCPU=20MHz for the C167CR,
f82C900=24MHz).
Table 3 Startup file configuration
_MCTC3 = 7 7 Waitstates (/RD at least 360ns)
_RWDC3 = 0 /RD/WR delay at least 10ns
_BTYP3 = 1 8-Bit multiplexed bus
_CSREN3/_CSWEN3 = 1 CS is dependent of RD/WR signal