Infineon ICE2HS01G Installation and operating instructions

Never stop thinking.
Power Management & Supply
Design Guide for LLC Converter
with ICE2HS01G
Application Note, V1.0, July 2011

Edition 2011-07-06
Published by Infineon Technologies Asia Pacific,
168 Kallang Way,
349253 Singapore, Singapore
© Infineon Technologies AP 2010.
All Rights Reserved.
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Design Guide for LLC Converter with ICE2HS01
Revision History: 2011-07 V1.0
Previous Version: NA
Design Guide for LLC Converter with ICE2HS01G
License to Infineon Technologies Asia Pacific Pte Ltd A N - P S 0057
Liu Jianwei
Li Dong

Page
Application Note 4 2011-07-06
Table of Content
1Abstract.............................................................................................5
2Design Procedure ............................................................................5
2.1Target Specifications....................................................................................................................5
2.2Design of Power Stage .................................................................................................................6
2.2.1System specifications......................................................................................................................6
2.2.2Selection of resonant factor m ........................................................................................................6
2.2.3Voltage gain ....................................................................................................................................7
2.2.4Transformer turns ratio....................................................................................................................7
2.2.5Effective load resistance .................................................................................................................7
2.2.6Resonant network ...........................................................................................................................7
2.2.7Transformer design .........................................................................................................................9
2.2.8SR MOSFET .................................................................................................................................10
2.3Design of Control Parameters and Protections.......................................................................10
2.3.1Frequency setting:.........................................................................................................................10
2.3.2Minimum/Maximum frequency setting: .........................................................................................10
2.3.3Frequency setting for OCP:...........................................................................................................11
2.3.4Dead time ......................................................................................................................................12
2.3.5Softstart time, OLP blanking time and auto-restart time ...............................................................13
2.3.6Load pin setting.............................................................................................................................13
2.3.7Current sense................................................................................................................................13
2.3.8VINS pin setting ............................................................................................................................15
2.3.9Latch off function and burst mode selection .................................................................................15
2.4Design of Synchronous Rectification (SR) control .................................................................16
2.4.1On-time control - SRD pin and CL pin ..........................................................................................18
2.4.2Turn-on delay delayon T_- Vres pin.................................................................................................20
2.4.3Advanced Turn off delay delayoff T_- Delay pin ..............................................................................21
2.4.4A review of the control scheme .....................................................................................................21
2.4.5SR Protections ..............................................................................................................................22
2.5Design summary .........................................................................................................................22
3Tips on PCB layout ........................................................................24
3.1Star connection for Power stage...............................................................................................24
3.2Star connection for IC.................................................................................................................25

Application Note 5 2011-07-06
1 Abstract
ICE2HS01G is our 2nd generation half-bridge LLC controller designed especially for high efficiency with its
synchronous rectification (SR) control for the secondary side. With its new driving techniques, SR can be
realized for half-bridge LLC converter operated with secondary switching current in both CCM and DCM
conditions. No individual SR controller IC is needed at the secondary side.
A typical application circuit of ICE2HS01G is shown in Figure 1. For best performance, it is suggested to use
half-bridge driver IC in the primary side with ICE2HS01G.
TL431
OPTO
QPH
CRES
CO1 CO2
RBA1
RBA2
ROVS2
ROVS3
ROVS1
Roc Coc
QPL
CBUS
RTCSS RFMIN
Rreg
ROCP
RFT2
RFT1
RSS1
CSS1
QSH
QSL
IC Driver
IC Driver
Pulse
Trans.
RINS1
RINS2
HG LG
RINS3
VINSVCC
CVCC
HV
VCC
GND
CS
CCS1
RCS1
DCS2
RCS2 CCS2
CL CCL
SRD
RCL
RSRD
QSRD
SHG
SLG
Lres
HV IC
LOADFREQSSTimer
CT
Delay
EnA
TD
Vref
Vmc
Vres
ICE2HS01G
REnA
Rdelay
RTD
Rmc1 Rres1
Rmc2
Rres2
Vout
CEnA
QS1
QS2
QS3
QS4
DCS1
Figure 1 Typical application circuit
In this application note, the design procedure for LLC resonant converter with ICE2HS01 is presented,
together with an example of a 300W converter with 400VDC. Detailed calculation of the values of the
components around the IC is also included, together with tips on the PCB layout.
2 Design Procedure
2.1 Target Specifications

Application Note 6 2011-07-06
The design example is based on the typical application circuit in Figure 1, where individual resonant
choke is implemented. The target specifications are summarized in Table 1.
Input voltage in
V400VDC
Output voltage and current oo IV ,12VDC, 25A
Output power in P~ 300W
Efficiency
η
>96% at 100% load
>97% at 50% load
>96% at 20% load
Resonant frequency r
f85kHz
Hold up time h T20ms
Bulk capacitor out C270uF
Table 1 Target application specifications
2.2 Design of Power Stage
2.2.1 System specifications
The maximum input power can be calculated as:
[1]
Based on the required 20ms hold-up time, the minimum input voltage can be given as:
[2]
2.2.2 Selection of resonant factor m
In order to achieve the highest efficiency possible, the value of resonant factor
r
rm
r
p
LLL L
L
m+ == is to
be set as big as possible, so that the magnetizing inductance m
Lis big and therefore magnetizing current
is small, which results in low core loss and conduction loss. On the other hand, the magnetizing current
should be big enough to discharge the ds
Cof primary side MOSFET during the transitions, to realize
ZVS to ensure safe switching and save switching loss. In this design example, 13=mis selected as a
start. The ZVS of primary side MOSFET will be confirmed later with the determination of the deadtime of
switching.
W
IV
POO
in 5.312
96.0
25*12
*===
η
V
CTP
VV
out
hin
nominin 2.337
10*270
10*20*5.312*2
400
2
6
3
2
2
_min_ =−=−= −
−

Application Note 7 2011-07-06
2.2.3 Voltage gain
It is for efficiency optimization to operate the LLC converter around the resonant frequency at nominal
input voltage, where the voltage gain 1
=
nom
M, on condition that the secondary-side leakage inductance
is neglected due to the implementation of individual resonant choke.
The worst case we need to consider for resonant network and transformer design is the full load
operation at minimum input voltage min_in
V. The maximum voltage gain at min_in Vcan be calculated as:
19.11*
2.337
400
min_
_
max === nom
in
nomin M
V
V
M[3]
2.2.4 Transformer turns ratio
Assuming the drain-source voltage drop of secondary-side MOSFET VVf1.0
=
, the transformer turns
ratio will be:
5.161*
)1.012(*2
400
)(2
_=
+
=
+
=nom
fo
nomin M
VV
V
n[4]
2.2.5 Effective load resistance
The effective load resistance can be given as:
Ω=== 106
25
12
*5.16*
88 2
2
2
2
ππ
o
o
eff I
V
nR [5]
2.2.6 Resonant network
Defining the normalised frequency to r fis
r
ff
F=, the load factor of the LLC converter is
eff
r
r
R
C
L
Q=,
the voltage gain of the converter can be written as:
QmFjFmF mF
QFMj )1)(1()1(
)1(
),( 22
2
−−+−
−
=[6]
Its magnitude is:
22 )),(Im()),(Re(),( QFMjQFMjQFG += [7]
The graph of voltage gain GVs Ffor different Qcan be plotted based on [7] with Mathcad:

Application Note 8 2011-07-06
Figure 2 Voltage gain GVs normalized frequency F
Among the curves, we find that the one with 267.0
=
Qcan achieve the required peak gain pk G, which
is 8% higher than max
Mfor design margin, i.e.
28.108.1 max == MGpk
From the curve, the corresponding 35.0
min
=
Fcan be located where 28.1
=
pk
Gis achieved.
Having found the proper Q, we can calculate the r
C, r Land p
Las follows:
nF
RfQ
C
effr
r66
106*10*85*268.0*2
1
***2
1
3===
π
π
[8]
uH
Cf
L
rr
r53
10*66*)10*85*2(
1
*)*2(
1
9232 === −
ππ
[9]
uHmLL rp 690==
2.2.6.1 Resonant choke design
The minimum rms voltage across the resonant network is:
[10]
Then the corresponding rms current flowing through the resonant choke r
Lcan be calculated as:
0.2 0.35 0.5 0.65 0.8 0.95 1.1 1.25 1.4
0.8
0.888
0.975
1.063
1.15
1.238
1.325
1.413
1.5
GF0.22, ()
GF0.267, ()
GF0.3, ()
GF0.35, ()
GF0.5, ()
GF0.65, ()
GF0.8, ()
Line
F
VVV inrmsin 79.1512.337*
22
min_min__ ===
ππ

Application Note 9 2011-07-06
[11]
The peak current is AII rmsrpkr 91.2*2 __ == . The OCP level is set with about 20% margin:
AII pkrpkocp 49.3*2.1 __ ==
The actual leakage inductance ( leak
L) measured at primary side with one of the secondary side winding
shorted is around 13uH. Therefore, the inductance for the independent resonant choke is:
If a magnetic core with specs of RM10/PC95 is selected, where 2
min_ 90mmAe=, and max
Bis selected
to be 0.08T to reduce core loss, the minimum turns can be given as:
[12]
2.2.7 Transformer design
From Figure 2, the normalized frequency 35.0
min
=
Fhas been located to achieve maximum gain
28.1=
pk
G. Accordingly the actual minimum frequency min
fis:
kHzfFf r3010*85*35.0* 3
min ===
The voltage across the primary winding can be calculated as )( fop VVnV
+
=
. The half switching cycle
period is around:
min
2
1
f
t=. According to Faraday’s law:
BAN
f
VVn
ep
fo Δ=
+
min
2
)(
The minimum number of turns at primary side can be found:
BAf
VVn
N
e
fo
pΔ
+
=*2
)(
min
min [13]
Where 2
161mmAe=with PQ3230 core. TB 62.0
=
Δ
is selected to avoid magnetic saturation.
Then minp
Ncan be calculated as:
33
62.0*10*161*10*30*2
)1.012(*5.16
63
min =
+
=−
p
N
The number of turns at primary side is selected as 33
min
=
p
N. The secondary side turns can be
calculated accordingly:
A
VP
I
rmsin
in
rmsin 06.2
79.151*96.0
300
*min__
max__ ===
η
4.19
10*90*08.0
49.3*10*40
6
6
minmax
__
min ==
⋅
⋅
=−
−
LL
pkrchoker
LAB
IL
N
uHLLL leakrchoker 40
_=−=

Application Note 10 2011-07-06
2== n
N
Np
s
2.2.8 SR MOSFET
The voltage stress on the drain-source of the MOSFET is:
VVVV fods 2.242*)( =+=
The RMS value of the current flowing through each MOSFET is:
AII ormsd 63.19
4
_==
π
2.3 Design of Control Parameters and Protections
2.3.1 Frequency setting:
The IC internal circuit provides a regulated 2V voltage at FREQ pin. The effective resistance presented
between the FREQ pin and GND, determines the current flowing out of the FREQ pin, which in turn
defines the switching frequency.
Figure 3 shows the curve illustrating the relationship of Switching Frequency FREQ Vs Effective
Resistor FREQ
Rconnected between the FREQ pin and gound.
Figure 3 FREQ Vs Effective Resistor FREQ
R
2.3.2 Minimum/Maximum frequency setting:

Application Note 11 2011-07-06
As discussed in section 2.2.7, the lowest switching min fwill be seen in full load operation at min_in V. In this
section, how the min
fis actually set by the IC is explained.
Based on the definition of oscillator as in the datasheet and the external circuit around pin FREQ in
Figure 1, the minimum switching frequency will be achieved when pin SS is 2V (usually after softstart),
opto-coupler transistor is open and only minF
Ris connected to pin FREQ. For kHzf 30
min =, the
corresponding FREQ
Rfound from Figure 3 is 50kΩ. A standard value resistor of 51kΩis selected
for minF
R.
The maximum operation frequency can possibly be seen when maximum input voltage, say 425V, is
applied, and the converter run in no load condition ( 0
=
Q), if burst mode is disabled. The gain in this
condition can be given as:
94.01*
425
400
max_
_
min === nom
in
nomin M
V
V
M[14]
From the gain equation, we get:
)0(,
)1(
)1(
),( min
2
2
==
−
−
=QM
mF mF
QFG [15]
The corresponding normalized frequency max
Fcan be found by:
13.2
1
1
min
=
+−
=mMm F
Therefore kHzkHzFf 18085*
max == .
For 180 kHz switching frequency, the corresponding equivalent resistance eq
Rat FREQ pin is 7.5kΩ
according to Figure 3. Under no load normal operation, pin SS is already 2V after soft start, and collector
of opto-coupler transistor is pulled to ground, therefore
regeq RRR FMIN //=
The reg
Ris calculated to be 8.8kΩ. A standard value resistor of 8.2kΩis selected for the actual design.
2.3.3 Frequency setting for OCP:
Assuming the maximum rms current during over-current should be limited by the IC to 1.2 times the
maximum normal operation, i.e.
The corresponding impedance of the resonant network during over-current can be estimated as:
[16]
During over-current, the load impedence is considered to be shorted, and thereofore the impedance of
the resonant network can be calculated as:
[17]
AII rmsinrmsocp 47.206.2*2.12.1 max___ ===
Ω=== 73
47.2*
2*400
_
π
ocp
rmsin
ocp I
V
Z
rocp
rocp
rocp
rocpocp Cf
Lf
Cfj
LfjZ *2
1
*2
*2*
1
*2*
π
π
π
π
−=+=

Application Note 12 2011-07-06
Solve the equation and find
Then eq
Ris 5kΩaccording to Figure 3. According to the definition of over-current protection,
ocpeq RRR FMIN //=,
Then ocp
Rcan be found as 5.6kΩ.
2.3.4 Dead time
The dead time selection should ensure ZVS of two primary-side MOSFET IPA60R199CP at maximum
switching frequency, where the magnetizing current to charge and discharge ds
Cis the minimum. The
magnetizing current at the end of each switching cycle can be calculated as:
[18]
The required time to charge and discharge the ds
Cis:
[19]
Then TD
Ris around 270kΩaccording to Figure 4.
Figure 4 DEAD
TVs TD R
kHzfocp 250=
A
fL NVV
I
ocpp
edsO
mag 288.0
10*250*10*690*4
5.16*)1.012(
4
*)(
36
min =
+
=
+
=−
ns
IVC IVC
T
mag
innomds
mag
innomds
DEAD 440
288.0
400*10*160*2
22 12
minmin
====
−

Application Note 13 2011-07-06
2.3.5 Softstart time, OLP blanking time and auto-restart time
According to the definition of the softstart of the IC in the datasheet, soft start is implemented by
sweeping the operating frequency from an initial high value until the control loop takes over. The softstart
time depends on a few components, such as the minF
R, the value of ocp
Rand the value of SS
C. For a
20ms target rising time of the output voltage, the customer can start with uFCSS 2.2
=
.
The Timer pin is used to set the blanking time OLP
Tand restart time restart Tfor over load protection. The
RC parallel circuit, T
Cand T R, are connected to this pin. Based on the definition in the datasheet, the
OLP blanking time with Ω= MRT1and uFCT1
=
can be calculated as:
ms
IRV
CRmsT
BLT
TH
TTOLP 240)
10*20*10
4
1ln(*10*10*100020)
*
1ln(**20 66
66 =−−=−−= − −
The restart time can be calculated as:
ms
V
V
CRT
TH
TL
TTrestart 20301000*)
4
525.0
ln(*10*10)ln(** 66 =−=−= −
2.3.6 Load pin setting
One of the functions of the LOAD pin is to detect the over-load or open-loop faults. Once the voltage at this pin
is higher than 1.8V, IC will start internal and external timer and determine the entering of protection mode. The
resistor divider 1FT
Rand 2FT Rshould be designed properly to ensure OLP is functional as required. The
bottom resistor 2FT
Rconnected to GND pin should be far bigger than the FMIN R, in order not to affect normal
regulation. As an example, assuming
Ω
=
MRFT 2
2, the target voltage at Load pin is 1.82V when
overload happens. The reference voltage at frequency pin is 2V. Then the voltage at LOAD pin
V
RR R
V
FTFT
FT
LOAD 82.12*
21
2=
+
=[20]
We can find Ω= MRFT 2.0
1.A small capacitor of 1nF is usually connected to decouple noise at LOAD
pin.
2.3.7 Current sense

Application Note 14 2011-07-06
Figure 5 Current sense circuit
Assuming capacitive current divider is adopted as current sense circuit. So 1cs Cis chosen to be far less
than r
C,e. g, around 100/
r
C, say 470pF. 1cs Ris normally of a few hundred Ωfor filtering purpose, say
200Ω.
We can obtain the following equation considering 1cs Cand r Cas current divider:
r
cs
ocp
rcs
cs
ocpC C
C
I
CC C
II cs
1
1
1
1≈
+
=[21]
One major design criterion for the current sense is to ensure Over-Current Protection (OCP). Accordingly,
we can also obtain:
2
8.0
*
22 21 cs
RC R
II cscs
π
π
== [22]
where 0.8V is the OCP first level.
Then we get:
Ω=== −
−
70
10*470
10*66
*
47.2*2
8.0
*
*2
8.0
12
9
1
2
ππ
cs
r
ocp
cs C
C
I
R[23]
Rcs2 is chosen as 68Ω.
2cs
Cis selected so that the current loop speed is fast enough and the ripple on CS pin is around 20% of
the average value. 22 *cscs CR is around
min
1
f.
nF
fR
C
cs
cs 490
10*30*68
1
*
1
3
min2
2==≈

Application Note 15 2011-07-06
2.3.8 VINS pin setting
The minimum operation input voltage needs to be specified for LLC resonant converter with the Vins pin.
The typical circuit of mains input voltage sense and process is shown Figure 6.
Figure 6 Mains input voltage sense
The mains input voltage is divided by INSH
Rand INSL R. With the internal current source hys Iis
connected between VINS and Ground, an adjustable hysteresis between the on and off input voltage can
be created as
[24]
Assuming the turn-on bus voltage INon
Vis 380V typically and the turn-off bus voltage INoff Vis 320V
typically.The INSH
Rand INSL Rcan be calculated as:
[25]
[26]
A standard resistor value for INSL
Ris 24kΩ.
The blanking time for leaving brown-out is around 500μs and for entering brown-out is around 50μs.
Please note that the calculation above is based on typical specification values of the IC.
2.3.9 Latch off function and burst mode selection
Internally, the EnA pin has a pull-up current source of 100μA. By connecting a resistor outside from this
pin to ground, certain voltage level is set up on this pin. If the voltage level on this pin is pulled down
below certain level during operation, IC is latched. If the external resistor has a negative temperature
coefficient, this pin can be used to implement over- temperature protection (OTP). In this design, EnA
Ris
selected at 1MΩto set the pin voltage to be 2V level and no OTP is designed.
Ω=
−
=
−
=−M
I
VV
R
INS
INoffINon
INSH 6
10*10
320380
6
INSHhyshys RIV *=
Ω=
−
=
−
=k
VV RV
R
thinoff
INSHth
INSL 5.23
25.1320
10*6*25.1 6

Application Note 16 2011-07-06
In addition to the latch-off enable function, this pin is also built for the selection of burst mode enable or
not during configuration before softstart. If the burst mode is enabled, the gate drives will be disabled if
LOAD pin voltage falls below 0.12V. However, if burst mode is not selected, the gate drives will not be
stopped by LOAD pin voltage.
The selection block works only after the first time IC VCC increases above UVLO. After CVCC is higher
than turn on threshod, a current source sele
I, in addition to the EnA I, is turned on to charge the capacitor
EnA
C. After 26μs, IC will compare the voltage on EnA pin and 1.0V, if voltage on EnA pin is higher than
1.0V, the burst mode function will be enabled. As the voltage on EnA pin depends on EnA
Rand EnA C, by
selecting different capacitance value, whether this IC works with burst mode can be decided.
With Ω= MREnA 1and nFCEnA 1=, the voltage at EnA pin at the time of 26us can be calculated as:
Therefire burst mode will be enabled. If EnA
Cis set to be 10n F, thus burst
mode will be disabled.
After the selection is done, the current source sele
Iis turned off. A blanking time of 320μs is given before
IC starts to sense the EnA pin voltage latch off enable purpose. This blanking time is used to let the EnA
pin votlage be stablized to avoid mistriggering of Latch-off Enable function.
2.4 Design of Synchronous Rectification (SR) control
Synchronous Rectification (SR) in a half-bridge LLC resonant converter is one of the key factor to achieve
high efficiency. SR control is a major benefit we offer with our new LLC controller IC ICE2HS01G.
Before going into details of SR control of the IC, it’s necessary to understand the ideal SR switching
mechanism for two typical working conditions, i.e. when operation frequency( sw
f) is below ( sw f<r f)
and above the resonant frequency ( sw
f>r f).Figure 7 illustrates the waveforms of HG V(primary high side
gate), LG
V(primary low side gate), SHG V( secondary high side gate), SLG V(secondary low side gate),
SH
I(current flowing through secondary high side MOSFET), SL I( current flowing through secondary low
side MOSFET) and PRI
I(current flowing through primary resonant tank).
VVeeRIV RC
EnAseleEnA 0.156.2)1(*10*10*100)1(* 96
6
6
10*10
10*26
66
10*26
>=−=−= −
−
−
−
−
−
usVVVEnA 26@0.126.0 <
=

Application Note 17 2011-07-06
Figure 7 Waveforms for LLC converter with sw
f>r f(left) and sw f<r f(right)
It can be seen from the waveforms in Figure 7 (left) that to ensure safe switching, the switch-on of the SR
MOSFET (see SLG
V) need to be a certain time AFTER the switch-on of the primary side switch(see LG V);
while switch-off of the SR MOSFET(see SLG
V) needs to be certain time BEFORE the switch-off of primary
side switch(see LG
V), in order to compensate the propagation delay of the gate signals from IC to the
actual MOSFET. In this operation condition ( sw
f>r f), the SR MOSFET conduction period (on-time)
depends on the primary gate switching frequency.
From Figure 7 (right), the current flowing through the SR MOSFET (see SL
I) goes to zero before the
switch-off of the primary switch. To avoid the current going into negative, the SR MOSFET need to be
turn off just before the current goes to zero. In this condition, the SR MOSFET on-time is almost constant
and nearly half of the resonant period.
The control of SR in ICE2HS01G consists of four main parts: on-time control, turn-on delay, advanced
turn-off delay and protections, with the block diagram shown in Figure 8.

Application Note 18 2011-07-06
Figure 8 Synchronous rectification control block diagram
2.4.1 On-time control - SRD pin and CL pin
With ICE2HS01’s control scheme, SR MOSFET ‘s turning-off depends on two conditions - turning-off of
the primary gate and the “off” instruction from SR on-time block, where the maximum on-time max_on
Tis
preset. Whichever “off” instruction comes first will trigger the turn-off of the SR MOSFET.
As illustrated in the previous chapter, the max_on
Tdepends on the resonant frequency when LLC
converter operates below resonant frequency ( sw
f<r f). Considering the primary side dead time DEAD T
and the SR gate turn-on delay delayon
T_( will be discussed later section 2.4.2), we can preset max_on Twith
a safe value as below:
usTT
f
TdelayonDEAD
res
on 31.525.032.088.5
2
1
_max_ =−−=−−< [27]
To achieve higher efficiency, a bigger max_on
Tis an advantage, because bigger on-time means longer SR
MOSFET conduction time and less body diode conduction time, which reduces conduction loss. In actual
design, max_on
Tcan be fine-tuned by looking at the similar waveforms in Figure 7, as long as safe
switching is guaranteed.

Application Note 19 2011-07-06
From Figure 9 below, SRD Ris selected to be 66kΩto achieve usTon 31.5
max_
=
. Usually customer
should start with a smaller SR on time for safety and then adjust it to achieve higher efficiency.
Figure 9 SR on time versus SRD resistance
A simple constant on time control does not provide the best efficiency of LLC HB converter for the whole
load range. In fact, the actual resonant period of secondary current reduces when the output load
decreases or input voltage increases. The primary winding current can reflects this change. The current
sense circuit can be designed to get such information and input to CS pin. In ICE2HS01G, a function
called current level (CL) pin is implemented. During heavy load and low input voltage, the CL pin voltage
(CL
V) is clamped at same voltage of SRD pin, 2V. Therefore, the SR on time in such conditions is
determined by SRD
Ronly and is equal to max_on T. In case of light load, with low CS voltage( CS V), the
CL
Vis reduced to be lower than 2V and extra current will be drawn from SRD pin, thereby the actual SR
on time is reduced. The relationship between CS
Vand CL Vis shown in Figure 10(top). The resistor CL R
can be adjusted to find the suitable reducing speed of SR on time for either better reliability or better
efficiency. CL
Ris normally around 10 times SRD R, which is 680kΩin this design. Below is the detailed
calculation for the 300W design example:
We obtain the CS Vfor full load condition, based on the circuit in Figure 5:
V
C
C
IR
V
r
cs
rmsincs
cs 635.0
10*66
10*470
*
06.2*68*2
*
*2
9
12
1
max__2 === −
−
ππ
The corresponding CL
Vis clamped at 2V according to Figure 10(top) and the SR on time is max_on T.
Then for CS
V= 0.4V where CL Vis exactly 2V, the corresponding load is 63% of the full load, which is
around 16A output current(Figure 10, bottom).

Application Note 20 2011-07-06
With CS V< 0.4V, CL Vstarts to drop below 2V, extra current is drawn from SRD pin, thereby the actual
SR on time is reduced with the load decreased.
For filter purpose, CL
Cis chosen to be 47nF.
Figure 10 SR on time versus SRD resistance
2.4.2 Turn-on delay
delayon
T_- Vres pin
When the input voltage is higher than resonant voltage, the LLC converter secondary switches are
working in CCM condition. Certain recovery time of the SR MOSFET body diode is required depending on
the current to turn-off. For better performance, the other SR MOSFET should be turn on after the
recovery phase. The turn-on delay function is built in ICE2HS01G for such purpose. When the sensed
input voltage at VINS pin is higher than the reference voltage set by Vres pin according to the resonant
voltage, SR turn-on delay is added, i.e, the SR MOSFETs are turn on 250ns after the corresponding
primary MOSFETs are turned on.
The nominal bus voltage at resonant point is:
[28]
The corresponding voltage at VINS pin is 1.59V. To allow the turn-on delay for input voltage above this
resonant point, we can set the voltage divider 1res
Rand 2res Rconnected at VRES pin accordingly. We
select Ω= kRres 12
1, and 2res
Rcan be calculated to be 5.2kΩ. To disable the turn-on delay during normal
operation, we can set the voltage at res
Vto be 1.07x1.59=1.7V. Accordingly, Ω= kRres 12
1,
and Ω= kRres 2.6
2.
VVVnV fOres 3.399)1.012(*5.16*2)(*2
=
+
=
+=